8f1ab438fffa3a0ea844f64c80b36d4562b0ab4d
[mesa.git] / src / gallium / drivers / radeonsi / si_state.h
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Christian König <christian.koenig@amd.com>
25 */
26
27 #ifndef SI_STATE_H
28 #define SI_STATE_H
29
30 #include "radeonsi_pm4.h"
31
32 struct si_state_blend {
33 struct si_pm4_state pm4;
34 uint32_t cb_target_mask;
35 uint32_t cb_color_control;
36 };
37
38 struct si_state_viewport {
39 struct si_pm4_state pm4;
40 struct pipe_viewport_state viewport;
41 };
42
43 struct si_state_rasterizer {
44 struct si_pm4_state pm4;
45 bool flatshade;
46 bool two_side;
47 unsigned sprite_coord_enable;
48 unsigned pa_sc_line_stipple;
49 unsigned pa_su_sc_mode_cntl;
50 unsigned pa_cl_clip_cntl;
51 unsigned pa_cl_vs_out_cntl;
52 float offset_units;
53 float offset_scale;
54 };
55
56 struct si_state_dsa {
57 struct si_pm4_state pm4;
58 unsigned alpha_ref;
59 unsigned db_render_override;
60 unsigned db_render_control;
61 uint8_t valuemask[2];
62 uint8_t writemask[2];
63 };
64
65 struct si_vertex_element
66 {
67 unsigned count;
68 uint32_t rsrc_word3[PIPE_MAX_ATTRIBS];
69 struct pipe_vertex_element elements[PIPE_MAX_ATTRIBS];
70 };
71
72 union si_state {
73 struct {
74 struct si_pm4_state *sync;
75 struct si_pm4_state *init;
76 struct si_state_blend *blend;
77 struct si_pm4_state *blend_color;
78 struct si_pm4_state *clip;
79 struct si_pm4_state *scissor;
80 struct si_state_viewport *viewport;
81 struct si_pm4_state *framebuffer;
82 struct si_state_rasterizer *rasterizer;
83 struct si_state_dsa *dsa;
84 struct si_pm4_state *fb_rs;
85 struct si_pm4_state *fb_blend;
86 struct si_pm4_state *dsa_stencil_ref;
87 struct si_pm4_state *vs;
88 struct si_pm4_state *vs_const;
89 struct si_pm4_state *ps;
90 struct si_pm4_state *ps_sampler_views;
91 struct si_pm4_state *ps_sampler;
92 struct si_pm4_state *ps_const;
93 struct si_pm4_state *spi;
94 struct si_pm4_state *vertex_buffers;
95 struct si_pm4_state *texture_barrier;
96 struct si_pm4_state *draw_info;
97 struct si_pm4_state *draw;
98 } named;
99 struct si_pm4_state *array[0];
100 };
101
102 #define si_pm4_block_idx(member) \
103 (offsetof(union si_state, named.member) / sizeof(struct si_pm4_state *))
104
105 #define si_pm4_state_changed(rctx, member) \
106 ((rctx)->queued.named.member != (rctx)->emitted.named.member)
107
108 #define si_pm4_bind_state(rctx, member, value) \
109 do { \
110 (rctx)->queued.named.member = (value); \
111 } while(0)
112
113 #define si_pm4_delete_state(rctx, member, value) \
114 do { \
115 if ((rctx)->queued.named.member == (value)) { \
116 (rctx)->queued.named.member = NULL; \
117 } \
118 si_pm4_free_state(rctx, (struct si_pm4_state *)(value), \
119 si_pm4_block_idx(member)); \
120 } while(0)
121
122 #define si_pm4_set_state(rctx, member, value) \
123 do { \
124 if ((rctx)->queued.named.member != (value)) { \
125 si_pm4_free_state(rctx, \
126 (struct si_pm4_state *)(rctx)->queued.named.member, \
127 si_pm4_block_idx(member)); \
128 (rctx)->queued.named.member = (value); \
129 } \
130 } while(0)
131
132 /* si_state.c */
133 struct si_pipe_shader_selector;
134
135 boolean si_is_format_supported(struct pipe_screen *screen,
136 enum pipe_format format,
137 enum pipe_texture_target target,
138 unsigned sample_count,
139 unsigned usage);
140 int si_shader_select(struct pipe_context *ctx,
141 struct si_pipe_shader_selector *sel,
142 unsigned *dirty);
143 void si_init_state_functions(struct r600_context *rctx);
144 void si_init_config(struct r600_context *rctx);
145
146 /* si_state_streamout.c */
147 struct pipe_stream_output_target *
148 si_create_so_target(struct pipe_context *ctx,
149 struct pipe_resource *buffer,
150 unsigned buffer_offset,
151 unsigned buffer_size);
152 void si_so_target_destroy(struct pipe_context *ctx,
153 struct pipe_stream_output_target *target);
154 void si_set_so_targets(struct pipe_context *ctx,
155 unsigned num_targets,
156 struct pipe_stream_output_target **targets,
157 unsigned append_bitmask);
158
159 /* si_state_draw.c */
160 void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *dinfo);
161
162 /* si_commands.c */
163 void si_cmd_context_control(struct si_pm4_state *pm4);
164 void si_cmd_draw_index_2(struct si_pm4_state *pm4, uint32_t max_size,
165 uint64_t index_base, uint32_t index_count,
166 uint32_t initiator, bool predicate);
167 void si_cmd_draw_index_auto(struct si_pm4_state *pm4, uint32_t count,
168 uint32_t initiator, bool predicate);
169 void si_cmd_surface_sync(struct si_pm4_state *pm4, uint32_t cp_coher_cntl);
170
171 #endif