src/gallium/drivers/radeonsi/si_state.h

   1 /*
   2  * Copyright 2012 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Christian König <christian.koenig@amd.com>
  25  */
  26
  27 #ifndef SI_STATE_H
  28 #define SI_STATE_H
  29
  30 #include "si_pm4.h"
  31 #include "../radeon/r600_pipe_common.h"
  32
  33 struct si_screen;
  34
  35 struct si_state_blend {
  36         struct si_pm4_state     pm4;
  37         uint32_t                cb_target_mask;
  38         bool                    alpha_to_one;
  39 };
  40
  41 struct si_state_viewport {
  42         struct si_pm4_state             pm4;
  43         struct pipe_viewport_state      viewport;
  44 };
  45
  46 struct si_state_rasterizer {
  47         struct si_pm4_state     pm4;
  48         bool                    flatshade;
  49         bool                    two_side;
  50         bool                    multisample_enable;
  51         bool                    line_stipple_enable;
  52         unsigned                sprite_coord_enable;
  53         unsigned                pa_sc_line_stipple;
  54         unsigned                pa_su_sc_mode_cntl;
  55         unsigned                pa_cl_clip_cntl;
  56         unsigned                pa_cl_vs_out_cntl;
  57         unsigned                clip_plane_enable;
  58         float                   offset_units;
  59         float                   offset_scale;
  60 };
  61
  62 struct si_state_dsa {
  63         struct si_pm4_state     pm4;
  64         float                   alpha_ref;
  65         unsigned                alpha_func;
  66         unsigned                db_render_control;
  67         uint8_t                 valuemask[2];
  68         uint8_t                 writemask[2];
  69 };
  70
  71 struct si_vertex_element
  72 {
  73         unsigned                        count;
  74         uint32_t                        rsrc_word3[PIPE_MAX_ATTRIBS];
  75         struct pipe_vertex_element      elements[PIPE_MAX_ATTRIBS];
  76 };
  77
  78 union si_state {
  79         struct {
  80                 struct si_pm4_state             *init;
  81                 struct si_state_blend           *blend;
  82                 struct si_pm4_state             *blend_color;
  83                 struct si_pm4_state             *clip;
  84                 struct si_pm4_state             *sample_mask;
  85                 struct si_pm4_state             *scissor;
  86                 struct si_state_viewport        *viewport;
  87                 struct si_state_rasterizer      *rasterizer;
  88                 struct si_state_dsa             *dsa;
  89                 struct si_pm4_state             *fb_rs;
  90                 struct si_pm4_state             *fb_blend;
  91                 struct si_pm4_state             *dsa_stencil_ref;
  92                 struct si_pm4_state             *es;
  93                 struct si_pm4_state             *gs;
  94                 struct si_pm4_state             *gs_rings;
  95                 struct si_pm4_state             *gs_sampler;
  96                 struct si_pm4_state             *gs_onoff;
  97                 struct si_pm4_state             *vs;
  98                 struct si_pm4_state             *vs_sampler;
  99                 struct si_pm4_state             *ps;
 100                 struct si_pm4_state             *ps_sampler;
 101                 struct si_pm4_state             *spi;
 102                 struct si_pm4_state             *vertex_buffers;
 103                 struct si_pm4_state             *draw_info;
 104                 struct si_pm4_state             *draw;
 105         } named;
 106         struct si_pm4_state     *array[0];
 107 };
 108
 109 #define SI_NUM_USER_SAMPLERS 16 /* AKA OpenGL textures units per shader */
 110
 111 /* User sampler views:   0..15
 112  * FMASK sampler views: 16..31 (no sampler states)
 113  */
 114 #define SI_FMASK_TEX_OFFSET             SI_NUM_USER_SAMPLERS
 115 #define SI_NUM_SAMPLER_VIEWS            (SI_FMASK_TEX_OFFSET + SI_NUM_USER_SAMPLERS)
 116 #define SI_NUM_SAMPLER_STATES           SI_NUM_USER_SAMPLERS
 117
 118 /* User constant buffers:   0..15
 119  * Driver state constants:  16
 120  */
 121 #define SI_NUM_USER_CONST_BUFFERS       16
 122 #define SI_DRIVER_STATE_CONST_BUF       SI_NUM_USER_CONST_BUFFERS
 123 #define SI_NUM_CONST_BUFFERS            (SI_DRIVER_STATE_CONST_BUF + 1)
 124
 125 /* Read-write buffer slots.
 126  *
 127  * Ring buffers:        0..1
 128  * Streamout buffers:   2..5
 129  */
 130 #define SI_RING_ESGS            0
 131 #define SI_RING_GSVS            1
 132 #define SI_NUM_RING_BUFFERS     2
 133 #define SI_SO_BUF_OFFSET        SI_NUM_RING_BUFFERS
 134 #define SI_NUM_RW_BUFFERS       (SI_SO_BUF_OFFSET + 4)
 135
 136 #define SI_NUM_VERTEX_BUFFERS   16
 137
 138
 139 /* This represents resource descriptors in memory, such as buffer resources,
 140  * image resources, and sampler states.
 141  */
 142 struct si_descriptors {
 143         struct r600_atom atom;
 144
 145         /* The size of one resource descriptor. */
 146         unsigned element_dw_size;
 147         /* The maximum number of resource descriptors. */
 148         unsigned num_elements;
 149
 150         /* The buffer where resource descriptors are stored. */
 151         struct r600_resource *buffer;
 152
 153         /* The i-th bit is set if that element is dirty (changed but not emitted). */
 154         unsigned dirty_mask;
 155         /* The i-th bit is set if that element is enabled (non-NULL resource). */
 156         unsigned enabled_mask;
 157
 158         /* We can't update descriptors directly because the GPU might be
 159          * reading them at the same time, so we have to update them
 160          * in a copy-on-write manner. Each such copy is called a context,
 161          * which is just another array descriptors in the same buffer. */
 162         unsigned current_context_id;
 163         /* The size of a context, should be equal to 4*element_dw_size*num_elements. */
 164         unsigned context_size;
 165
 166         /* The shader userdata register where the 64-bit pointer to the descriptor
 167          * array will be stored. */
 168         unsigned shader_userdata_reg;
 169 };
 170
 171 struct si_sampler_views {
 172         struct si_descriptors           desc;
 173         struct pipe_sampler_view        *views[SI_NUM_SAMPLER_VIEWS];
 174         uint32_t                        *desc_data[SI_NUM_SAMPLER_VIEWS];
 175 };
 176
 177 struct si_buffer_resources {
 178         struct si_descriptors           desc;
 179         unsigned                        num_buffers;
 180         enum radeon_bo_usage            shader_usage; /* READ, WRITE, or READWRITE */
 181         enum radeon_bo_priority         priority;
 182         struct pipe_resource            **buffers; /* this has num_buffers elements */
 183         uint32_t                        *desc_storage; /* this has num_buffers*4 elements */
 184         uint32_t                        **desc_data; /* an array of pointers pointing to desc_storage */
 185 };
 186
 187 #define si_pm4_block_idx(member) \
 188         (offsetof(union si_state, named.member) / sizeof(struct si_pm4_state *))
 189
 190 #define si_pm4_state_changed(sctx, member) \
 191         ((sctx)->queued.named.member != (sctx)->emitted.named.member)
 192
 193 #define si_pm4_bind_state(sctx, member, value) \
 194         do { \
 195                 (sctx)->queued.named.member = (value); \
 196         } while(0)
 197
 198 #define si_pm4_delete_state(sctx, member, value) \
 199         do { \
 200                 if ((sctx)->queued.named.member == (value)) { \
 201                         (sctx)->queued.named.member = NULL; \
 202                 } \
 203                 si_pm4_free_state(sctx, (struct si_pm4_state *)(value), \
 204                                   si_pm4_block_idx(member)); \
 205         } while(0)
 206
 207 #define si_pm4_set_state(sctx, member, value) \
 208         do { \
 209                 if ((sctx)->queued.named.member != (value)) { \
 210                         si_pm4_free_state(sctx, \
 211                                 (struct si_pm4_state *)(sctx)->queued.named.member, \
 212                                 si_pm4_block_idx(member)); \
 213                         (sctx)->queued.named.member = (value); \
 214                 } \
 215         } while(0)
 216
 217 /* si_descriptors.c */
 218 void si_set_sampler_view(struct si_context *sctx, unsigned shader,
 219                          unsigned slot, struct pipe_sampler_view *view,
 220                          unsigned *view_desc);
 221 void si_set_ring_buffer(struct pipe_context *ctx, uint shader, uint slot,
 222                         struct pipe_constant_buffer *input,
 223                         unsigned stride, unsigned num_records,
 224                         bool add_tid, bool swizzle,
 225                         unsigned element_size, unsigned index_stride);
 226 void si_init_all_descriptors(struct si_context *sctx);
 227 void si_release_all_descriptors(struct si_context *sctx);
 228 void si_all_descriptors_begin_new_cs(struct si_context *sctx);
 229 void si_copy_buffer(struct si_context *sctx,
 230                     struct pipe_resource *dst, struct pipe_resource *src,
 231                     uint64_t dst_offset, uint64_t src_offset, unsigned size);
 232 void si_upload_const_buffer(struct si_context *sctx, struct r600_resource **rbuffer,
 233                             const uint8_t *ptr, unsigned size, uint32_t *const_offset);
 234
 235 /* si_state.c */
 236 struct si_pipe_shader_selector;
 237
 238 boolean si_is_format_supported(struct pipe_screen *screen,
 239                                enum pipe_format format,
 240                                enum pipe_texture_target target,
 241                                unsigned sample_count,
 242                                unsigned usage);
 243 int si_shader_select(struct pipe_context *ctx,
 244                      struct si_pipe_shader_selector *sel);
 245 void si_init_state_functions(struct si_context *sctx);
 246 void si_init_config(struct si_context *sctx);
 247 unsigned cik_bank_wh(unsigned bankwh);
 248 unsigned cik_db_pipe_config(struct si_screen *sscreen, unsigned tile_mode);
 249 unsigned cik_macro_tile_aspect(unsigned macro_tile_aspect);
 250 unsigned cik_tile_split(unsigned tile_split);
 251 uint32_t si_num_banks(struct si_screen *sscreen, unsigned bpe, unsigned tile_split,
 252                       unsigned tile_mode_index);
 253 unsigned si_tile_mode_index(struct r600_texture *rtex, unsigned level, bool stencil);
 254
 255 /* si_state_draw.c */
 256 extern const struct r600_atom si_atom_cache_flush;
 257 extern const struct r600_atom si_atom_msaa_config;
 258 void si_emit_cache_flush(struct r600_common_context *sctx, struct r600_atom *atom);
 259 void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *dinfo);
 260
 261 /* si_commands.c */
 262 void si_cmd_context_control(struct si_pm4_state *pm4);
 263 void si_cmd_draw_index_2(struct si_pm4_state *pm4, uint32_t max_size,
 264                          uint64_t index_base, uint32_t index_count,
 265                          uint32_t initiator, bool predicate);
 266 void si_cmd_draw_index_auto(struct si_pm4_state *pm4, uint32_t count,
 267                             uint32_t initiator, bool predicate);
 268 void si_cmd_draw_indirect(struct si_pm4_state *pm4, uint64_t indirect_va,
 269                           uint32_t indirect_offset, uint32_t base_vtx_loc,
 270                           uint32_t start_inst_loc, bool predicate);
 271 void si_cmd_draw_index_indirect(struct si_pm4_state *pm4, uint64_t indirect_va,
 272                                 uint64_t index_va, uint32_t index_max_size,
 273                                 uint32_t indirect_offset, uint32_t base_vtx_loc,
 274                                 uint32_t start_inst_loc, bool predicate);
 275 void si_cmd_surface_sync(struct si_pm4_state *pm4, uint32_t cp_coher_cntl);
 276
 277 #endif