c49b029d71a4282c12ddb472fceb4aa1024a0610
[mesa.git] / src / gallium / drivers / radeonsi / si_state.h
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Christian König <christian.koenig@amd.com>
25 */
26
27 #ifndef SI_STATE_H
28 #define SI_STATE_H
29
30 #include "radeonsi_pm4.h"
31
32 struct si_state_blend {
33 struct si_pm4_state pm4;
34 uint32_t cb_target_mask;
35 uint32_t cb_color_control;
36 };
37
38 struct si_state_viewport {
39 struct si_pm4_state pm4;
40 struct pipe_viewport_state viewport;
41 };
42
43 struct si_state_rasterizer {
44 struct si_pm4_state pm4;
45 bool flatshade;
46 bool two_side;
47 unsigned sprite_coord_enable;
48 unsigned pa_sc_line_stipple;
49 unsigned pa_su_sc_mode_cntl;
50 unsigned pa_cl_clip_cntl;
51 unsigned pa_cl_vs_out_cntl;
52 float offset_units;
53 float offset_scale;
54 };
55
56 struct si_state_dsa {
57 struct si_pm4_state pm4;
58 float alpha_ref;
59 unsigned alpha_func;
60 unsigned db_render_override;
61 unsigned db_render_control;
62 uint8_t valuemask[2];
63 uint8_t writemask[2];
64 };
65
66 struct si_vertex_element
67 {
68 unsigned count;
69 uint32_t rsrc_word3[PIPE_MAX_ATTRIBS];
70 struct pipe_vertex_element elements[PIPE_MAX_ATTRIBS];
71 };
72
73 union si_state {
74 struct {
75 struct si_pm4_state *sync;
76 struct si_pm4_state *init;
77 struct si_state_blend *blend;
78 struct si_pm4_state *blend_color;
79 struct si_pm4_state *clip;
80 struct si_pm4_state *scissor;
81 struct si_state_viewport *viewport;
82 struct si_pm4_state *framebuffer;
83 struct si_state_rasterizer *rasterizer;
84 struct si_state_dsa *dsa;
85 struct si_pm4_state *fb_rs;
86 struct si_pm4_state *fb_blend;
87 struct si_pm4_state *dsa_stencil_ref;
88 struct si_pm4_state *vs;
89 struct si_pm4_state *vs_sampler_views;
90 struct si_pm4_state *vs_sampler;
91 struct si_pm4_state *vs_const;
92 struct si_pm4_state *ps;
93 struct si_pm4_state *ps_sampler_views;
94 struct si_pm4_state *ps_sampler;
95 struct si_pm4_state *ps_const;
96 struct si_pm4_state *spi;
97 struct si_pm4_state *vertex_buffers;
98 struct si_pm4_state *texture_barrier;
99 struct si_pm4_state *draw_info;
100 struct si_pm4_state *draw;
101 } named;
102 struct si_pm4_state *array[0];
103 };
104
105 #define si_pm4_block_idx(member) \
106 (offsetof(union si_state, named.member) / sizeof(struct si_pm4_state *))
107
108 #define si_pm4_state_changed(rctx, member) \
109 ((rctx)->queued.named.member != (rctx)->emitted.named.member)
110
111 #define si_pm4_bind_state(rctx, member, value) \
112 do { \
113 (rctx)->queued.named.member = (value); \
114 } while(0)
115
116 #define si_pm4_delete_state(rctx, member, value) \
117 do { \
118 if ((rctx)->queued.named.member == (value)) { \
119 (rctx)->queued.named.member = NULL; \
120 } \
121 si_pm4_free_state(rctx, (struct si_pm4_state *)(value), \
122 si_pm4_block_idx(member)); \
123 } while(0)
124
125 #define si_pm4_set_state(rctx, member, value) \
126 do { \
127 if ((rctx)->queued.named.member != (value)) { \
128 si_pm4_free_state(rctx, \
129 (struct si_pm4_state *)(rctx)->queued.named.member, \
130 si_pm4_block_idx(member)); \
131 (rctx)->queued.named.member = (value); \
132 } \
133 } while(0)
134
135 /* si_state.c */
136 struct si_pipe_shader_selector;
137
138 boolean si_is_format_supported(struct pipe_screen *screen,
139 enum pipe_format format,
140 enum pipe_texture_target target,
141 unsigned sample_count,
142 unsigned usage);
143 int si_shader_select(struct pipe_context *ctx,
144 struct si_pipe_shader_selector *sel,
145 unsigned *dirty);
146 void si_init_state_functions(struct r600_context *rctx);
147 void si_init_config(struct r600_context *rctx);
148
149 /* si_state_streamout.c */
150 struct pipe_stream_output_target *
151 si_create_so_target(struct pipe_context *ctx,
152 struct pipe_resource *buffer,
153 unsigned buffer_offset,
154 unsigned buffer_size);
155 void si_so_target_destroy(struct pipe_context *ctx,
156 struct pipe_stream_output_target *target);
157 void si_set_so_targets(struct pipe_context *ctx,
158 unsigned num_targets,
159 struct pipe_stream_output_target **targets,
160 unsigned append_bitmask);
161
162 /* si_state_draw.c */
163 void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *dinfo);
164
165 /* si_commands.c */
166 void si_cmd_context_control(struct si_pm4_state *pm4);
167 void si_cmd_draw_index_2(struct si_pm4_state *pm4, uint32_t max_size,
168 uint64_t index_base, uint32_t index_count,
169 uint32_t initiator, bool predicate);
170 void si_cmd_draw_index_auto(struct si_pm4_state *pm4, uint32_t count,
171 uint32_t initiator, bool predicate);
172 void si_cmd_surface_sync(struct si_pm4_state *pm4, uint32_t cp_coher_cntl);
173
174 #endif