2 * Copyright 2012 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 * Christian König <christian.koenig@amd.com>
31 #include "radeon/r600_pipe_common.h"
33 #include "pipebuffer/pb_slab.h"
35 #define SI_NUM_GRAPHICS_SHADERS (PIPE_SHADER_TESS_EVAL+1)
36 #define SI_NUM_SHADERS (PIPE_SHADER_COMPUTE+1)
38 #define SI_MAX_ATTRIBS 16
39 #define SI_NUM_VERTEX_BUFFERS SI_MAX_ATTRIBS
40 #define SI_NUM_SAMPLERS 32 /* OpenGL textures units per shader */
41 #define SI_NUM_CONST_BUFFERS 16
42 #define SI_NUM_IMAGES 16
43 #define SI_NUM_SHADER_BUFFERS 16
47 struct si_shader_selector
;
49 struct si_state_blend
{
50 struct si_pm4_state pm4
;
51 uint32_t cb_target_mask
;
52 /* Set 0xf or 0x0 (4 bits) per render target if the following is
53 * true. ANDed with spi_shader_col_format.
55 unsigned cb_target_enabled_4bit
;
56 unsigned blend_enable_4bit
;
57 unsigned need_src_alpha_4bit
;
58 unsigned commutative_4bit
;
59 bool alpha_to_coverage
:1;
61 bool dual_src_blend
:1;
62 bool logicop_enable
:1;
65 struct si_state_rasterizer
{
66 struct si_pm4_state pm4
;
67 /* poly offset states for 16-bit, 24-bit, and 32-bit zbuffers */
68 struct si_pm4_state
*pm4_poly_offset
;
69 unsigned pa_sc_line_stipple
;
70 unsigned pa_cl_clip_cntl
;
73 unsigned sprite_coord_enable
:8;
74 unsigned clip_plane_enable
:8;
77 unsigned multisample_enable
:1;
78 unsigned force_persample_interp
:1;
79 unsigned line_stipple_enable
:1;
80 unsigned poly_stipple_enable
:1;
81 unsigned line_smooth
:1;
82 unsigned poly_smooth
:1;
83 unsigned uses_poly_offset
:1;
84 unsigned clamp_fragment_color
:1;
85 unsigned clamp_vertex_color
:1;
86 unsigned rasterizer_discard
:1;
87 unsigned scissor_enable
:1;
88 unsigned clip_halfz
:1;
91 struct si_dsa_stencil_ref_part
{
96 struct si_dsa_order_invariance
{
97 /** Whether the final result in Z/S buffers is guaranteed to be
98 * invariant under changes to the order in which fragments arrive. */
101 /** Whether the set of fragments that pass the combined Z/S test is
102 * guaranteed to be invariant under changes to the order in which
103 * fragments arrive. */
106 /** Whether the last fragment that passes the combined Z/S test at each
107 * sample is guaranteed to be invariant under changes to the order in
108 * which fragments arrive. */
112 struct si_state_dsa
{
113 struct si_pm4_state pm4
;
114 struct si_dsa_stencil_ref_part stencil_ref
;
116 /* 0 = without stencil buffer, 1 = when both Z and S buffers are present */
117 struct si_dsa_order_invariance order_invariance
[2];
120 bool depth_enabled
:1;
121 bool depth_write_enabled
:1;
122 bool stencil_enabled
:1;
123 bool stencil_write_enabled
:1;
128 struct si_stencil_ref
{
129 struct r600_atom atom
;
130 struct pipe_stencil_ref state
;
131 struct si_dsa_stencil_ref_part dsa_part
;
134 struct si_vertex_elements
136 uint32_t instance_divisors
[SI_MAX_ATTRIBS
];
137 uint32_t rsrc_word3
[SI_MAX_ATTRIBS
];
138 uint16_t src_offset
[SI_MAX_ATTRIBS
];
139 uint8_t fix_fetch
[SI_MAX_ATTRIBS
];
140 uint8_t format_size
[SI_MAX_ATTRIBS
];
141 uint8_t vertex_buffer_index
[SI_MAX_ATTRIBS
];
144 bool uses_instance_divisors
;
146 uint16_t first_vb_use_mask
;
147 /* Vertex buffer descriptor list size aligned for optimal prefetch. */
148 uint16_t desc_list_byte_size
;
149 uint16_t instance_divisor_is_one
; /* bitmask of inputs */
150 uint16_t instance_divisor_is_fetched
; /* bitmask of inputs */
155 struct si_state_blend
*blend
;
156 struct si_state_rasterizer
*rasterizer
;
157 struct si_state_dsa
*dsa
;
158 struct si_pm4_state
*poly_offset
;
159 struct si_pm4_state
*ls
;
160 struct si_pm4_state
*hs
;
161 struct si_pm4_state
*es
;
162 struct si_pm4_state
*gs
;
163 struct si_pm4_state
*vgt_shader_config
;
164 struct si_pm4_state
*vs
;
165 struct si_pm4_state
*ps
;
167 struct si_pm4_state
*array
[0];
170 #define SI_NUM_STATES (sizeof(union si_state) / sizeof(struct si_pm4_state *))
172 union si_state_atoms
{
174 /* The order matters. */
175 struct r600_atom
*render_cond
;
176 struct r600_atom
*streamout_begin
;
177 struct r600_atom
*streamout_enable
; /* must be after streamout_begin */
178 struct r600_atom
*framebuffer
;
179 struct r600_atom
*msaa_sample_locs
;
180 struct r600_atom
*db_render_state
;
181 struct r600_atom
*dpbb_state
;
182 struct r600_atom
*msaa_config
;
183 struct r600_atom
*sample_mask
;
184 struct r600_atom
*cb_render_state
;
185 struct r600_atom
*blend_color
;
186 struct r600_atom
*clip_regs
;
187 struct r600_atom
*clip_state
;
188 struct r600_atom
*shader_pointers
;
189 struct r600_atom
*scissors
;
190 struct r600_atom
*viewports
;
191 struct r600_atom
*stencil_ref
;
192 struct r600_atom
*spi_map
;
193 struct r600_atom
*scratch_state
;
195 struct r600_atom
*array
[0];
198 #define SI_NUM_ATOMS (sizeof(union si_state_atoms)/sizeof(struct r600_atom*))
200 struct si_shader_data
{
201 struct r600_atom atom
;
202 uint32_t sh_base
[SI_NUM_SHADERS
];
205 /* Private read-write buffer slots. */
212 SI_VS_STREAMOUT_BUF0
,
213 SI_VS_STREAMOUT_BUF1
,
214 SI_VS_STREAMOUT_BUF2
,
215 SI_VS_STREAMOUT_BUF3
,
217 SI_HS_CONST_DEFAULT_TESS_LEVELS
,
218 SI_VS_CONST_INSTANCE_DIVISORS
,
219 SI_VS_CONST_CLIP_PLANES
,
220 SI_PS_CONST_POLY_STIPPLE
,
221 SI_PS_CONST_SAMPLE_POSITIONS
,
226 /* Indices into sctx->descriptors, laid out so that gfx and compute pipelines
230 * 1 - vertex const and shader buffers
231 * 2 - vertex samplers and images
232 * 3 - fragment const and shader buffer
234 * 11 - compute const and shader buffers
235 * 12 - compute samplers and images
238 SI_SHADER_DESCS_CONST_AND_SHADER_BUFFERS
,
239 SI_SHADER_DESCS_SAMPLERS_AND_IMAGES
,
243 #define SI_DESCS_RW_BUFFERS 0
244 #define SI_DESCS_FIRST_SHADER 1
245 #define SI_DESCS_FIRST_COMPUTE (SI_DESCS_FIRST_SHADER + \
246 PIPE_SHADER_COMPUTE * SI_NUM_SHADER_DESCS)
247 #define SI_NUM_DESCS (SI_DESCS_FIRST_SHADER + \
248 SI_NUM_SHADERS * SI_NUM_SHADER_DESCS)
250 /* This represents descriptors in memory, such as buffer resources,
251 * image resources, and sampler states.
253 struct si_descriptors
{
254 /* The list of descriptors in malloc'd memory. */
256 /* The list in mapped GPU memory. */
259 /* The buffer where the descriptors have been uploaded. */
260 struct r600_resource
*buffer
;
261 int buffer_offset
; /* can be negative if not using lower slots */
263 /* The size of one descriptor. */
264 ubyte element_dw_size
;
265 /* The maximum number of descriptors. */
266 uint32_t num_elements
;
268 /* Slots that are used by currently-bound shaders.
269 * It determines which slots are uploaded.
271 uint32_t first_active_slot
;
272 uint32_t num_active_slots
;
274 /* The SGPR index where the 64-bit pointer to the descriptor array will
276 ubyte shader_userdata_offset
;
279 struct si_buffer_resources
{
280 struct pipe_resource
**buffers
; /* this has num_buffers elements */
282 enum radeon_bo_usage shader_usage
:4; /* READ, WRITE, or READWRITE */
283 enum radeon_bo_usage shader_usage_constbuf
:4;
284 enum radeon_bo_priority priority
:6;
285 enum radeon_bo_priority priority_constbuf
:6;
287 /* The i-th bit is set if that element is enabled (non-NULL resource). */
288 unsigned enabled_mask
;
291 #define si_pm4_block_idx(member) \
292 (offsetof(union si_state, named.member) / sizeof(struct si_pm4_state *))
294 #define si_pm4_state_changed(sctx, member) \
295 ((sctx)->queued.named.member != (sctx)->emitted.named.member)
297 #define si_pm4_state_enabled_and_changed(sctx, member) \
298 ((sctx)->queued.named.member && si_pm4_state_changed(sctx, member))
300 #define si_pm4_bind_state(sctx, member, value) \
302 (sctx)->queued.named.member = (value); \
303 (sctx)->dirty_states |= 1 << si_pm4_block_idx(member); \
306 #define si_pm4_delete_state(sctx, member, value) \
308 if ((sctx)->queued.named.member == (value)) { \
309 (sctx)->queued.named.member = NULL; \
311 si_pm4_free_state(sctx, (struct si_pm4_state *)(value), \
312 si_pm4_block_idx(member)); \
315 /* si_descriptors.c */
316 void si_set_mutable_tex_desc_fields(struct si_screen
*sscreen
,
317 struct r600_texture
*tex
,
318 const struct legacy_surf_level
*base_level_info
,
319 unsigned base_level
, unsigned first_level
,
320 unsigned block_width
, bool is_stencil
,
322 void si_get_pipe_constant_buffer(struct si_context
*sctx
, uint shader
,
323 uint slot
, struct pipe_constant_buffer
*cbuf
);
324 void si_get_shader_buffers(struct si_context
*sctx
,
325 enum pipe_shader_type shader
,
326 uint start_slot
, uint count
,
327 struct pipe_shader_buffer
*sbuf
);
328 void si_set_ring_buffer(struct pipe_context
*ctx
, uint slot
,
329 struct pipe_resource
*buffer
,
330 unsigned stride
, unsigned num_records
,
331 bool add_tid
, bool swizzle
,
332 unsigned element_size
, unsigned index_stride
, uint64_t offset
);
333 void si_init_all_descriptors(struct si_context
*sctx
);
334 bool si_upload_vertex_buffer_descriptors(struct si_context
*sctx
);
335 bool si_upload_graphics_shader_descriptors(struct si_context
*sctx
);
336 bool si_upload_compute_shader_descriptors(struct si_context
*sctx
);
337 void si_release_all_descriptors(struct si_context
*sctx
);
338 void si_all_descriptors_begin_new_cs(struct si_context
*sctx
);
339 void si_all_resident_buffers_begin_new_cs(struct si_context
*sctx
);
340 void si_upload_const_buffer(struct si_context
*sctx
, struct r600_resource
**rbuffer
,
341 const uint8_t *ptr
, unsigned size
, uint32_t *const_offset
);
342 void si_update_all_texture_descriptors(struct si_context
*sctx
);
343 void si_shader_change_notify(struct si_context
*sctx
);
344 void si_update_needs_color_decompress_masks(struct si_context
*sctx
);
345 void si_emit_graphics_shader_pointers(struct si_context
*sctx
,
346 struct r600_atom
*atom
);
347 void si_emit_compute_shader_pointers(struct si_context
*sctx
);
348 void si_set_rw_buffer(struct si_context
*sctx
,
349 uint slot
, const struct pipe_constant_buffer
*input
);
350 void si_set_active_descriptors(struct si_context
*sctx
, unsigned desc_idx
,
351 uint64_t new_active_mask
);
352 void si_set_active_descriptors_for_shader(struct si_context
*sctx
,
353 struct si_shader_selector
*sel
);
354 bool si_bindless_descriptor_can_reclaim_slab(void *priv
,
355 struct pb_slab_entry
*entry
);
356 struct pb_slab
*si_bindless_descriptor_slab_alloc(void *priv
, unsigned heap
,
358 unsigned group_index
);
359 void si_bindless_descriptor_slab_free(void *priv
, struct pb_slab
*pslab
);
362 struct si_shader_selector
;
364 void si_init_atom(struct si_context
*sctx
, struct r600_atom
*atom
,
365 struct r600_atom
**list_elem
,
366 void (*emit_func
)(struct si_context
*ctx
, struct r600_atom
*state
));
367 void si_init_state_functions(struct si_context
*sctx
);
368 void si_init_screen_state_functions(struct si_screen
*sscreen
);
370 si_make_buffer_descriptor(struct si_screen
*screen
, struct r600_resource
*buf
,
371 enum pipe_format format
,
372 unsigned offset
, unsigned size
,
375 si_make_texture_descriptor(struct si_screen
*screen
,
376 struct r600_texture
*tex
,
378 enum pipe_texture_target target
,
379 enum pipe_format pipe_format
,
380 const unsigned char state_swizzle
[4],
381 unsigned first_level
, unsigned last_level
,
382 unsigned first_layer
, unsigned last_layer
,
383 unsigned width
, unsigned height
, unsigned depth
,
385 uint32_t *fmask_state
);
386 struct pipe_sampler_view
*
387 si_create_sampler_view_custom(struct pipe_context
*ctx
,
388 struct pipe_resource
*texture
,
389 const struct pipe_sampler_view
*state
,
390 unsigned width0
, unsigned height0
,
391 unsigned force_level
);
392 void si_update_fb_dirtiness_after_rendering(struct si_context
*sctx
);
394 /* si_state_binning.c */
395 void si_emit_dpbb_state(struct si_context
*sctx
, struct r600_atom
*state
);
397 /* si_state_shaders.c */
398 bool si_update_shaders(struct si_context
*sctx
);
399 void si_init_shader_functions(struct si_context
*sctx
);
400 bool si_init_shader_cache(struct si_screen
*sscreen
);
401 void si_destroy_shader_cache(struct si_screen
*sscreen
);
402 void si_get_active_slot_masks(const struct tgsi_shader_info
*info
,
403 uint32_t *const_and_shader_buffers
,
404 uint64_t *samplers_and_images
);
405 void *si_get_blit_vs(struct si_context
*sctx
, enum blitter_attrib_type type
,
406 unsigned num_layers
);
408 /* si_state_draw.c */
409 void si_init_ia_multi_vgt_param_table(struct si_context
*sctx
);
410 void si_emit_cache_flush(struct si_context
*sctx
);
411 void si_draw_vbo(struct pipe_context
*ctx
, const struct pipe_draw_info
*dinfo
);
412 void si_draw_rectangle(struct blitter_context
*blitter
,
413 void *vertex_elements_cso
,
414 blitter_get_vs_func get_vs
,
415 int x1
, int y1
, int x2
, int y2
,
416 float depth
, unsigned num_instances
,
417 enum blitter_attrib_type type
,
418 const union blitter_attrib
*attrib
);
419 void si_trace_emit(struct si_context
*sctx
);
422 static inline unsigned
423 si_tile_mode_index(struct r600_texture
*rtex
, unsigned level
, bool stencil
)
426 return rtex
->surface
.u
.legacy
.stencil_tiling_index
[level
];
428 return rtex
->surface
.u
.legacy
.tiling_index
[level
];
431 static inline unsigned si_get_constbuf_slot(unsigned slot
)
433 /* Constant buffers are in slots [16..31], ascending */
434 return SI_NUM_SHADER_BUFFERS
+ slot
;
437 static inline unsigned si_get_shaderbuf_slot(unsigned slot
)
439 /* shader buffers are in slots [15..0], descending */
440 return SI_NUM_SHADER_BUFFERS
- 1 - slot
;
443 static inline unsigned si_get_sampler_slot(unsigned slot
)
445 /* samplers are in slots [8..39], ascending */
446 return SI_NUM_IMAGES
/ 2 + slot
;
449 static inline unsigned si_get_image_slot(unsigned slot
)
451 /* images are in slots [15..0] (sampler slots [7..0]), descending */
452 return SI_NUM_IMAGES
- 1 - slot
;