2 * Copyright 2012 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 * Christian König <christian.koenig@amd.com>
31 #include "radeon/r600_pipe_common.h"
33 #define SI_NUM_SHADERS (PIPE_SHADER_TESS_EVAL+1)
34 #define SI_MAX_ATTRIBS 16
39 struct si_state_blend
{
40 struct si_pm4_state pm4
;
41 uint32_t cb_target_mask
;
42 bool alpha_to_coverage
;
45 /* Set 0xf or 0x0 (4 bits) per render target if the following is
46 * true. ANDed with spi_shader_col_format.
48 unsigned blend_enable_4bit
;
49 unsigned need_src_alpha_4bit
;
52 struct si_state_rasterizer
{
53 struct si_pm4_state pm4
;
54 /* poly offset states for 16-bit, 24-bit, and 32-bit zbuffers */
55 struct si_pm4_state pm4_poly_offset
[3];
58 bool multisample_enable
;
59 bool force_persample_interp
;
60 bool line_stipple_enable
;
61 unsigned sprite_coord_enable
;
62 unsigned pa_sc_line_stipple
;
63 unsigned pa_cl_clip_cntl
;
64 unsigned clip_plane_enable
;
65 bool poly_stipple_enable
;
68 bool uses_poly_offset
;
69 bool clamp_fragment_color
;
70 bool rasterizer_discard
;
74 struct si_dsa_stencil_ref_part
{
80 struct si_pm4_state pm4
;
82 struct si_dsa_stencil_ref_part stencil_ref
;
85 struct si_stencil_ref
{
86 struct r600_atom atom
;
87 struct pipe_stencil_ref state
;
88 struct si_dsa_stencil_ref_part dsa_part
;
91 struct si_vertex_element
94 uint32_t rsrc_word3
[SI_MAX_ATTRIBS
];
95 uint32_t format_size
[SI_MAX_ATTRIBS
];
96 struct pipe_vertex_element elements
[SI_MAX_ATTRIBS
];
101 struct si_state_blend
*blend
;
102 struct si_state_rasterizer
*rasterizer
;
103 struct si_state_dsa
*dsa
;
104 struct si_pm4_state
*poly_offset
;
105 struct si_pm4_state
*ls
;
106 struct si_pm4_state
*hs
;
107 struct si_pm4_state
*es
;
108 struct si_pm4_state
*gs
;
109 struct si_pm4_state
*vgt_shader_config
;
110 struct si_pm4_state
*vs
;
111 struct si_pm4_state
*ps
;
113 struct si_pm4_state
*array
[0];
116 union si_state_atoms
{
118 /* The order matters. */
119 struct r600_atom
*cache_flush
;
120 struct r600_atom
*render_cond
;
121 struct r600_atom
*streamout_begin
;
122 struct r600_atom
*streamout_enable
; /* must be after streamout_begin */
123 struct r600_atom
*framebuffer
;
124 struct r600_atom
*msaa_sample_locs
;
125 struct r600_atom
*db_render_state
;
126 struct r600_atom
*msaa_config
;
127 struct r600_atom
*sample_mask
;
128 struct r600_atom
*cb_render_state
;
129 struct r600_atom
*blend_color
;
130 struct r600_atom
*clip_regs
;
131 struct r600_atom
*clip_state
;
132 struct r600_atom
*shader_userdata
;
133 struct r600_atom
*scissors
;
134 struct r600_atom
*viewports
;
135 struct r600_atom
*stencil_ref
;
136 struct r600_atom
*spi_map
;
138 struct r600_atom
*array
[0];
141 #define SI_NUM_ATOMS (sizeof(union si_state_atoms)/sizeof(struct r600_atom*))
143 struct si_shader_data
{
144 struct r600_atom atom
;
145 uint32_t sh_base
[SI_NUM_SHADERS
];
148 /* User sampler views: 0..31
149 * Polygon stipple tex: 32
151 #define SI_NUM_USER_SAMPLERS 32 /* AKA OpenGL textures units per shader */
152 #define SI_POLY_STIPPLE_SAMPLER SI_NUM_USER_SAMPLERS
153 #define SI_NUM_SAMPLERS (SI_POLY_STIPPLE_SAMPLER + 1)
155 /* User constant buffers: 0..15
156 * Driver state constants: 16
158 #define SI_NUM_USER_CONST_BUFFERS 16
159 #define SI_DRIVER_STATE_CONST_BUF SI_NUM_USER_CONST_BUFFERS
160 #define SI_NUM_CONST_BUFFERS (SI_DRIVER_STATE_CONST_BUF + 1)
162 #define SI_NUM_IMAGES 16
164 #define SI_NUM_SHADER_BUFFERS 16
166 /* Read-write buffer slots.
169 * Streamout buffers: 2..5
171 #define SI_RING_TESS_FACTOR 0 /* for HS (TCS) */
172 #define SI_RING_ESGS 0 /* for ES, GS */
173 #define SI_RING_GSVS 1 /* for GS, VS */
174 #define SI_RING_GSVS_1 2 /* 1, 2, 3 for GS */
175 #define SI_RING_GSVS_2 3
176 #define SI_RING_GSVS_3 4
177 #define SI_NUM_RING_BUFFERS 5
178 #define SI_SO_BUF_OFFSET SI_NUM_RING_BUFFERS
179 #define SI_NUM_RW_BUFFERS (SI_SO_BUF_OFFSET + 4)
181 #define SI_NUM_VERTEX_BUFFERS SI_MAX_ATTRIBS
184 /* This represents descriptors in memory, such as buffer resources,
185 * image resources, and sampler states.
187 struct si_descriptors
{
188 /* The list of descriptors in malloc'd memory. */
190 /* The size of one descriptor. */
191 unsigned element_dw_size
;
192 /* The maximum number of descriptors. */
193 unsigned num_elements
;
195 /* The buffer where the descriptors have been uploaded. */
196 struct r600_resource
*buffer
;
197 unsigned buffer_offset
;
199 /* Offset in CE RAM */
202 /* The i-th bit is set if that element is enabled (non-NULL resource). */
203 uint64_t enabled_mask
;
205 /* elements of the list that are changed and need to be uploaded */
208 /* Whether the CE ram is dirty and needs to be reinitialized entirely
209 * before we can do partial updates. */
212 /* The shader userdata offset within a shader where the 64-bit pointer to the descriptor
213 * array will be stored. */
214 unsigned shader_userdata_offset
;
215 /* Whether the pointer should be re-emitted. */
219 struct si_sampler_views
{
220 struct si_descriptors desc
;
221 struct pipe_sampler_view
*views
[SI_NUM_SAMPLERS
];
222 void *sampler_states
[SI_NUM_SAMPLERS
];
225 struct si_buffer_resources
{
226 struct si_descriptors desc
;
227 enum radeon_bo_usage shader_usage
; /* READ, WRITE, or READWRITE */
228 enum radeon_bo_priority priority
;
229 struct pipe_resource
**buffers
; /* this has num_buffers elements */
232 #define si_pm4_block_idx(member) \
233 (offsetof(union si_state, named.member) / sizeof(struct si_pm4_state *))
235 #define si_pm4_state_changed(sctx, member) \
236 ((sctx)->queued.named.member != (sctx)->emitted.named.member)
238 #define si_pm4_bind_state(sctx, member, value) \
240 (sctx)->queued.named.member = (value); \
243 #define si_pm4_delete_state(sctx, member, value) \
245 if ((sctx)->queued.named.member == (value)) { \
246 (sctx)->queued.named.member = NULL; \
248 si_pm4_free_state(sctx, (struct si_pm4_state *)(value), \
249 si_pm4_block_idx(member)); \
252 /* si_descriptors.c */
253 void si_set_ring_buffer(struct pipe_context
*ctx
, uint shader
, uint slot
,
254 struct pipe_resource
*buffer
,
255 unsigned stride
, unsigned num_records
,
256 bool add_tid
, bool swizzle
,
257 unsigned element_size
, unsigned index_stride
, uint64_t offset
);
258 void si_init_all_descriptors(struct si_context
*sctx
);
259 bool si_upload_shader_descriptors(struct si_context
*sctx
);
260 void si_release_all_descriptors(struct si_context
*sctx
);
261 void si_all_descriptors_begin_new_cs(struct si_context
*sctx
);
262 void si_upload_const_buffer(struct si_context
*sctx
, struct r600_resource
**rbuffer
,
263 const uint8_t *ptr
, unsigned size
, uint32_t *const_offset
);
264 void si_shader_change_notify(struct si_context
*sctx
);
265 void si_update_compressed_colortex_masks(struct si_context
*sctx
);
266 void si_emit_shader_userdata(struct si_context
*sctx
, struct r600_atom
*atom
);
269 struct si_shader_selector
;
271 void si_init_atom(struct si_context
*sctx
, struct r600_atom
*atom
,
272 struct r600_atom
**list_elem
,
273 void (*emit_func
)(struct si_context
*ctx
, struct r600_atom
*state
));
274 boolean
si_is_format_supported(struct pipe_screen
*screen
,
275 enum pipe_format format
,
276 enum pipe_texture_target target
,
277 unsigned sample_count
,
279 void si_init_state_functions(struct si_context
*sctx
);
280 void si_init_screen_state_functions(struct si_screen
*sscreen
);
281 unsigned cik_bank_wh(unsigned bankwh
);
282 unsigned cik_db_pipe_config(struct si_screen
*sscreen
, unsigned tile_mode
);
283 unsigned cik_macro_tile_aspect(unsigned macro_tile_aspect
);
284 unsigned cik_tile_split(unsigned tile_split
);
285 unsigned si_array_mode(unsigned mode
);
286 uint32_t si_num_banks(struct si_screen
*sscreen
, struct r600_texture
*tex
);
287 unsigned si_tile_mode_index(struct r600_texture
*rtex
, unsigned level
, bool stencil
);
289 si_make_buffer_descriptor(struct si_screen
*screen
, struct r600_resource
*buf
,
290 enum pipe_format format
,
291 unsigned first_element
, unsigned last_element
,
294 si_make_texture_descriptor(struct si_screen
*screen
,
295 struct r600_texture
*tex
,
297 enum pipe_texture_target target
,
298 enum pipe_format pipe_format
,
299 const unsigned char state_swizzle
[4],
300 unsigned base_level
, unsigned first_level
, unsigned last_level
,
301 unsigned first_layer
, unsigned last_layer
,
302 unsigned width
, unsigned height
, unsigned depth
,
304 uint32_t *fmask_state
);
305 struct pipe_sampler_view
*
306 si_create_sampler_view_custom(struct pipe_context
*ctx
,
307 struct pipe_resource
*texture
,
308 const struct pipe_sampler_view
*state
,
309 unsigned width0
, unsigned height0
,
310 unsigned force_level
);
312 /* si_state_shader.c */
313 bool si_update_shaders(struct si_context
*sctx
);
314 void si_init_shader_functions(struct si_context
*sctx
);
315 bool si_init_shader_cache(struct si_screen
*sscreen
);
316 void si_destroy_shader_cache(struct si_screen
*sscreen
);
318 /* si_state_draw.c */
319 void si_emit_cache_flush(struct si_context
*sctx
, struct r600_atom
*atom
);
320 void si_draw_vbo(struct pipe_context
*ctx
, const struct pipe_draw_info
*dinfo
);
321 void si_trace_emit(struct si_context
*sctx
);