radeonsi: do per-pixel clipping based on viewport states
[mesa.git] / src / gallium / drivers / radeonsi / si_state.h
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Christian König <christian.koenig@amd.com>
25 */
26
27 #ifndef SI_STATE_H
28 #define SI_STATE_H
29
30 #include "si_pm4.h"
31 #include "radeon/r600_pipe_common.h"
32
33 #define SI_NUM_SHADERS (PIPE_SHADER_TESS_EVAL+1)
34 #define SI_MAX_ATTRIBS 16
35
36 struct si_screen;
37 struct si_shader;
38
39 struct si_state_blend {
40 struct si_pm4_state pm4;
41 uint32_t cb_target_mask;
42 bool alpha_to_coverage;
43 bool alpha_to_one;
44 bool dual_src_blend;
45 /* Set 0xf or 0x0 (4 bits) per render target if the following is
46 * true. ANDed with spi_shader_col_format.
47 */
48 unsigned blend_enable_4bit;
49 unsigned need_src_alpha_4bit;
50 };
51
52 struct si_state_rasterizer {
53 struct si_pm4_state pm4;
54 /* poly offset states for 16-bit, 24-bit, and 32-bit zbuffers */
55 struct si_pm4_state pm4_poly_offset[3];
56 bool flatshade;
57 bool two_side;
58 bool multisample_enable;
59 bool force_persample_interp;
60 bool line_stipple_enable;
61 unsigned sprite_coord_enable;
62 unsigned pa_sc_line_stipple;
63 unsigned pa_cl_clip_cntl;
64 unsigned clip_plane_enable;
65 bool poly_stipple_enable;
66 bool line_smooth;
67 bool poly_smooth;
68 bool uses_poly_offset;
69 bool clamp_fragment_color;
70 bool rasterizer_discard;
71 bool scissor_enable;
72 };
73
74 struct si_dsa_stencil_ref_part {
75 uint8_t valuemask[2];
76 uint8_t writemask[2];
77 };
78
79 struct si_state_dsa {
80 struct si_pm4_state pm4;
81 unsigned alpha_func;
82 struct si_dsa_stencil_ref_part stencil_ref;
83 };
84
85 struct si_stencil_ref {
86 struct r600_atom atom;
87 struct pipe_stencil_ref state;
88 struct si_dsa_stencil_ref_part dsa_part;
89 };
90
91 struct si_vertex_element
92 {
93 unsigned count;
94 uint32_t rsrc_word3[SI_MAX_ATTRIBS];
95 uint32_t format_size[SI_MAX_ATTRIBS];
96 struct pipe_vertex_element elements[SI_MAX_ATTRIBS];
97 };
98
99 union si_state {
100 struct {
101 struct si_state_blend *blend;
102 struct si_state_rasterizer *rasterizer;
103 struct si_state_dsa *dsa;
104 struct si_pm4_state *poly_offset;
105 struct si_pm4_state *ls;
106 struct si_pm4_state *hs;
107 struct si_pm4_state *es;
108 struct si_pm4_state *gs;
109 struct si_pm4_state *vgt_shader_config;
110 struct si_pm4_state *vs;
111 struct si_pm4_state *ps;
112 } named;
113 struct si_pm4_state *array[0];
114 };
115
116 union si_state_atoms {
117 struct {
118 /* The order matters. */
119 struct r600_atom *cache_flush;
120 struct r600_atom *render_cond;
121 struct r600_atom *streamout_begin;
122 struct r600_atom *streamout_enable; /* must be after streamout_begin */
123 struct r600_atom *framebuffer;
124 struct r600_atom *msaa_sample_locs;
125 struct r600_atom *db_render_state;
126 struct r600_atom *msaa_config;
127 struct r600_atom *sample_mask;
128 struct r600_atom *cb_render_state;
129 struct r600_atom *blend_color;
130 struct r600_atom *clip_regs;
131 struct r600_atom *clip_state;
132 struct r600_atom *shader_userdata;
133 struct r600_atom *scissors;
134 struct r600_atom *viewports;
135 struct r600_atom *stencil_ref;
136 struct r600_atom *spi_map;
137 } s;
138 struct r600_atom *array[0];
139 };
140
141 #define SI_NUM_ATOMS (sizeof(union si_state_atoms)/sizeof(struct r600_atom*))
142
143 struct si_shader_data {
144 struct r600_atom atom;
145 uint32_t sh_base[SI_NUM_SHADERS];
146 };
147
148 /* User sampler views: 0..31
149 * Polygon stipple tex: 32
150 */
151 #define SI_NUM_USER_SAMPLERS 32 /* AKA OpenGL textures units per shader */
152 #define SI_POLY_STIPPLE_SAMPLER SI_NUM_USER_SAMPLERS
153 #define SI_NUM_SAMPLERS (SI_POLY_STIPPLE_SAMPLER + 1)
154
155 /* User constant buffers: 0..15
156 * Driver state constants: 16
157 */
158 #define SI_NUM_USER_CONST_BUFFERS 16
159 #define SI_DRIVER_STATE_CONST_BUF SI_NUM_USER_CONST_BUFFERS
160 #define SI_NUM_CONST_BUFFERS (SI_DRIVER_STATE_CONST_BUF + 1)
161
162 #define SI_NUM_IMAGES 16
163
164 /* Read-write buffer slots.
165 *
166 * Ring buffers: 0..1
167 * Streamout buffers: 2..5
168 */
169 #define SI_RING_TESS_FACTOR 0 /* for HS (TCS) */
170 #define SI_RING_ESGS 0 /* for ES, GS */
171 #define SI_RING_GSVS 1 /* for GS, VS */
172 #define SI_RING_GSVS_1 2 /* 1, 2, 3 for GS */
173 #define SI_RING_GSVS_2 3
174 #define SI_RING_GSVS_3 4
175 #define SI_NUM_RING_BUFFERS 5
176 #define SI_SO_BUF_OFFSET SI_NUM_RING_BUFFERS
177 #define SI_NUM_RW_BUFFERS (SI_SO_BUF_OFFSET + 4)
178
179 #define SI_NUM_VERTEX_BUFFERS SI_MAX_ATTRIBS
180
181
182 /* This represents descriptors in memory, such as buffer resources,
183 * image resources, and sampler states.
184 */
185 struct si_descriptors {
186 /* The list of descriptors in malloc'd memory. */
187 uint32_t *list;
188 /* The size of one descriptor. */
189 unsigned element_dw_size;
190 /* The maximum number of descriptors. */
191 unsigned num_elements;
192 /* Whether the list has been changed and should be re-uploaded. */
193 bool list_dirty;
194
195 /* The buffer where the descriptors have been uploaded. */
196 struct r600_resource *buffer;
197 unsigned buffer_offset;
198
199 /* The i-th bit is set if that element is enabled (non-NULL resource). */
200 uint64_t enabled_mask;
201
202 /* The shader userdata offset within a shader where the 64-bit pointer to the descriptor
203 * array will be stored. */
204 unsigned shader_userdata_offset;
205 /* Whether the pointer should be re-emitted. */
206 bool pointer_dirty;
207 };
208
209 struct si_sampler_views {
210 struct si_descriptors desc;
211 struct pipe_sampler_view *views[SI_NUM_SAMPLERS];
212 void *sampler_states[SI_NUM_SAMPLERS];
213 };
214
215 struct si_buffer_resources {
216 struct si_descriptors desc;
217 enum radeon_bo_usage shader_usage; /* READ, WRITE, or READWRITE */
218 enum radeon_bo_priority priority;
219 struct pipe_resource **buffers; /* this has num_buffers elements */
220 };
221
222 #define si_pm4_block_idx(member) \
223 (offsetof(union si_state, named.member) / sizeof(struct si_pm4_state *))
224
225 #define si_pm4_state_changed(sctx, member) \
226 ((sctx)->queued.named.member != (sctx)->emitted.named.member)
227
228 #define si_pm4_bind_state(sctx, member, value) \
229 do { \
230 (sctx)->queued.named.member = (value); \
231 } while(0)
232
233 #define si_pm4_delete_state(sctx, member, value) \
234 do { \
235 if ((sctx)->queued.named.member == (value)) { \
236 (sctx)->queued.named.member = NULL; \
237 } \
238 si_pm4_free_state(sctx, (struct si_pm4_state *)(value), \
239 si_pm4_block_idx(member)); \
240 } while(0)
241
242 /* si_descriptors.c */
243 void si_set_ring_buffer(struct pipe_context *ctx, uint shader, uint slot,
244 struct pipe_resource *buffer,
245 unsigned stride, unsigned num_records,
246 bool add_tid, bool swizzle,
247 unsigned element_size, unsigned index_stride, uint64_t offset);
248 void si_init_all_descriptors(struct si_context *sctx);
249 bool si_upload_shader_descriptors(struct si_context *sctx);
250 void si_release_all_descriptors(struct si_context *sctx);
251 void si_all_descriptors_begin_new_cs(struct si_context *sctx);
252 void si_upload_const_buffer(struct si_context *sctx, struct r600_resource **rbuffer,
253 const uint8_t *ptr, unsigned size, uint32_t *const_offset);
254 void si_shader_change_notify(struct si_context *sctx);
255 void si_update_compressed_colortex_masks(struct si_context *sctx);
256 void si_emit_shader_userdata(struct si_context *sctx, struct r600_atom *atom);
257
258 /* si_state.c */
259 struct si_shader_selector;
260
261 void si_init_atom(struct si_context *sctx, struct r600_atom *atom,
262 struct r600_atom **list_elem,
263 void (*emit_func)(struct si_context *ctx, struct r600_atom *state));
264 boolean si_is_format_supported(struct pipe_screen *screen,
265 enum pipe_format format,
266 enum pipe_texture_target target,
267 unsigned sample_count,
268 unsigned usage);
269 void si_init_state_functions(struct si_context *sctx);
270 void si_init_screen_state_functions(struct si_screen *sscreen);
271 unsigned cik_bank_wh(unsigned bankwh);
272 unsigned cik_db_pipe_config(struct si_screen *sscreen, unsigned tile_mode);
273 unsigned cik_macro_tile_aspect(unsigned macro_tile_aspect);
274 unsigned cik_tile_split(unsigned tile_split);
275 unsigned si_array_mode(unsigned mode);
276 uint32_t si_num_banks(struct si_screen *sscreen, struct r600_texture *tex);
277 unsigned si_tile_mode_index(struct r600_texture *rtex, unsigned level, bool stencil);
278 void
279 si_make_buffer_descriptor(struct si_screen *screen, struct r600_resource *buf,
280 enum pipe_format format,
281 unsigned first_element, unsigned last_element,
282 uint32_t *state);
283 void
284 si_make_texture_descriptor(struct si_screen *screen,
285 struct r600_texture *tex,
286 bool sampler,
287 enum pipe_texture_target target,
288 enum pipe_format pipe_format,
289 const unsigned char state_swizzle[4],
290 unsigned base_level, unsigned first_level, unsigned last_level,
291 unsigned first_layer, unsigned last_layer,
292 unsigned width, unsigned height, unsigned depth,
293 uint32_t *state,
294 uint32_t *fmask_state);
295 struct pipe_sampler_view *
296 si_create_sampler_view_custom(struct pipe_context *ctx,
297 struct pipe_resource *texture,
298 const struct pipe_sampler_view *state,
299 unsigned width0, unsigned height0,
300 unsigned force_level);
301
302 /* si_state_shader.c */
303 bool si_update_shaders(struct si_context *sctx);
304 void si_init_shader_functions(struct si_context *sctx);
305 bool si_init_shader_cache(struct si_screen *sscreen);
306 void si_destroy_shader_cache(struct si_screen *sscreen);
307
308 /* si_state_draw.c */
309 void si_emit_cache_flush(struct si_context *sctx, struct r600_atom *atom);
310 void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *dinfo);
311 void si_trace_emit(struct si_context *sctx);
312
313 #endif