radeonsi: implement global resetting of texture descriptors
[mesa.git] / src / gallium / drivers / radeonsi / si_state.h
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Christian König <christian.koenig@amd.com>
25 */
26
27 #ifndef SI_STATE_H
28 #define SI_STATE_H
29
30 #include "si_pm4.h"
31 #include "radeon/r600_pipe_common.h"
32
33 #define SI_NUM_GRAPHICS_SHADERS (PIPE_SHADER_TESS_EVAL+1)
34 #define SI_NUM_SHADERS (PIPE_SHADER_COMPUTE+1)
35
36 #define SI_MAX_ATTRIBS 16
37 #define SI_NUM_VERTEX_BUFFERS SI_MAX_ATTRIBS
38 #define SI_NUM_SAMPLERS 32 /* OpenGL textures units per shader */
39 #define SI_NUM_CONST_BUFFERS 16
40 #define SI_NUM_IMAGES 16
41 #define SI_NUM_SHADER_BUFFERS 16
42
43 #define SI_TESS_OFFCHIP_BLOCK_SIZE (8192 * 4)
44
45 struct si_screen;
46 struct si_shader;
47
48 struct si_state_blend {
49 struct si_pm4_state pm4;
50 uint32_t cb_target_mask;
51 bool alpha_to_coverage;
52 bool alpha_to_one;
53 bool dual_src_blend;
54 /* Set 0xf or 0x0 (4 bits) per render target if the following is
55 * true. ANDed with spi_shader_col_format.
56 */
57 unsigned blend_enable_4bit;
58 unsigned need_src_alpha_4bit;
59 };
60
61 struct si_state_rasterizer {
62 struct si_pm4_state pm4;
63 /* poly offset states for 16-bit, 24-bit, and 32-bit zbuffers */
64 struct si_pm4_state pm4_poly_offset[3];
65 bool flatshade;
66 bool two_side;
67 bool multisample_enable;
68 bool force_persample_interp;
69 bool line_stipple_enable;
70 unsigned sprite_coord_enable;
71 unsigned pa_sc_line_stipple;
72 unsigned pa_cl_clip_cntl;
73 unsigned clip_plane_enable;
74 bool poly_stipple_enable;
75 bool line_smooth;
76 bool poly_smooth;
77 bool uses_poly_offset;
78 bool clamp_fragment_color;
79 bool rasterizer_discard;
80 bool scissor_enable;
81 };
82
83 struct si_dsa_stencil_ref_part {
84 uint8_t valuemask[2];
85 uint8_t writemask[2];
86 };
87
88 struct si_state_dsa {
89 struct si_pm4_state pm4;
90 unsigned alpha_func;
91 struct si_dsa_stencil_ref_part stencil_ref;
92 };
93
94 struct si_stencil_ref {
95 struct r600_atom atom;
96 struct pipe_stencil_ref state;
97 struct si_dsa_stencil_ref_part dsa_part;
98 };
99
100 struct si_vertex_element
101 {
102 unsigned count;
103 uint32_t rsrc_word3[SI_MAX_ATTRIBS];
104 uint32_t format_size[SI_MAX_ATTRIBS];
105 struct pipe_vertex_element elements[SI_MAX_ATTRIBS];
106 };
107
108 union si_state {
109 struct {
110 struct si_state_blend *blend;
111 struct si_state_rasterizer *rasterizer;
112 struct si_state_dsa *dsa;
113 struct si_pm4_state *poly_offset;
114 struct si_pm4_state *ls;
115 struct si_pm4_state *hs;
116 struct si_pm4_state *es;
117 struct si_pm4_state *gs;
118 struct si_pm4_state *vgt_shader_config;
119 struct si_pm4_state *vs;
120 struct si_pm4_state *ps;
121 } named;
122 struct si_pm4_state *array[0];
123 };
124
125 union si_state_atoms {
126 struct {
127 /* The order matters. */
128 struct r600_atom *cache_flush;
129 struct r600_atom *render_cond;
130 struct r600_atom *streamout_begin;
131 struct r600_atom *streamout_enable; /* must be after streamout_begin */
132 struct r600_atom *framebuffer;
133 struct r600_atom *msaa_sample_locs;
134 struct r600_atom *db_render_state;
135 struct r600_atom *msaa_config;
136 struct r600_atom *sample_mask;
137 struct r600_atom *cb_render_state;
138 struct r600_atom *blend_color;
139 struct r600_atom *clip_regs;
140 struct r600_atom *clip_state;
141 struct r600_atom *shader_userdata;
142 struct r600_atom *scissors;
143 struct r600_atom *viewports;
144 struct r600_atom *stencil_ref;
145 struct r600_atom *spi_map;
146 } s;
147 struct r600_atom *array[0];
148 };
149
150 #define SI_NUM_ATOMS (sizeof(union si_state_atoms)/sizeof(struct r600_atom*))
151
152 struct si_shader_data {
153 struct r600_atom atom;
154 uint32_t sh_base[SI_NUM_SHADERS];
155 };
156
157 /* Private read-write buffer slots. */
158 enum {
159 SI_HS_RING_TESS_FACTOR,
160 SI_HS_RING_TESS_OFFCHIP,
161
162 SI_ES_RING_ESGS,
163 SI_GS_RING_ESGS,
164
165 SI_GS_RING_GSVS0,
166 SI_GS_RING_GSVS1,
167 SI_GS_RING_GSVS2,
168 SI_GS_RING_GSVS3,
169 SI_VS_RING_GSVS,
170
171 SI_VS_STREAMOUT_BUF0,
172 SI_VS_STREAMOUT_BUF1,
173 SI_VS_STREAMOUT_BUF2,
174 SI_VS_STREAMOUT_BUF3,
175
176 SI_HS_CONST_DEFAULT_TESS_LEVELS,
177 SI_VS_CONST_CLIP_PLANES,
178 SI_PS_CONST_POLY_STIPPLE,
179 SI_PS_CONST_SAMPLE_POSITIONS,
180
181 SI_NUM_RW_BUFFERS,
182 };
183
184 /* This represents descriptors in memory, such as buffer resources,
185 * image resources, and sampler states.
186 */
187 struct si_descriptors {
188 /* The list of descriptors in malloc'd memory. */
189 uint32_t *list;
190 /* The size of one descriptor. */
191 unsigned element_dw_size;
192 /* The maximum number of descriptors. */
193 unsigned num_elements;
194
195 /* The buffer where the descriptors have been uploaded. */
196 struct r600_resource *buffer;
197 unsigned buffer_offset;
198
199 /* Offset in CE RAM */
200 unsigned ce_offset;
201
202 /* The i-th bit is set if that element is enabled (non-NULL resource). */
203 unsigned enabled_mask;
204
205 /* elements of the list that are changed and need to be uploaded */
206 unsigned dirty_mask;
207
208 /* Whether the CE ram is dirty and needs to be reinitialized entirely
209 * before we can do partial updates. */
210 bool ce_ram_dirty;
211
212 /* The shader userdata offset within a shader where the 64-bit pointer to the descriptor
213 * array will be stored. */
214 unsigned shader_userdata_offset;
215 /* Whether the pointer should be re-emitted. */
216 bool pointer_dirty;
217 };
218
219 struct si_sampler_views {
220 struct si_descriptors desc;
221 struct pipe_sampler_view *views[SI_NUM_SAMPLERS];
222 void *sampler_states[SI_NUM_SAMPLERS];
223 };
224
225 struct si_buffer_resources {
226 struct si_descriptors desc;
227 enum radeon_bo_usage shader_usage; /* READ, WRITE, or READWRITE */
228 enum radeon_bo_priority priority;
229 struct pipe_resource **buffers; /* this has num_buffers elements */
230 };
231
232 #define si_pm4_block_idx(member) \
233 (offsetof(union si_state, named.member) / sizeof(struct si_pm4_state *))
234
235 #define si_pm4_state_changed(sctx, member) \
236 ((sctx)->queued.named.member != (sctx)->emitted.named.member)
237
238 #define si_pm4_bind_state(sctx, member, value) \
239 do { \
240 (sctx)->queued.named.member = (value); \
241 } while(0)
242
243 #define si_pm4_delete_state(sctx, member, value) \
244 do { \
245 if ((sctx)->queued.named.member == (value)) { \
246 (sctx)->queued.named.member = NULL; \
247 } \
248 si_pm4_free_state(sctx, (struct si_pm4_state *)(value), \
249 si_pm4_block_idx(member)); \
250 } while(0)
251
252 /* si_descriptors.c */
253 void si_ce_enable_loads(struct radeon_winsys_cs *ib);
254 void si_set_mutable_tex_desc_fields(struct r600_texture *tex,
255 const struct radeon_surf_level *base_level_info,
256 unsigned base_level, unsigned block_width,
257 bool is_stencil, uint32_t *state);
258 void si_set_ring_buffer(struct pipe_context *ctx, uint slot,
259 struct pipe_resource *buffer,
260 unsigned stride, unsigned num_records,
261 bool add_tid, bool swizzle,
262 unsigned element_size, unsigned index_stride, uint64_t offset);
263 void si_init_all_descriptors(struct si_context *sctx);
264 bool si_upload_graphics_shader_descriptors(struct si_context *sctx);
265 bool si_upload_compute_shader_descriptors(struct si_context *sctx);
266 void si_release_all_descriptors(struct si_context *sctx);
267 void si_all_descriptors_begin_new_cs(struct si_context *sctx);
268 void si_upload_const_buffer(struct si_context *sctx, struct r600_resource **rbuffer,
269 const uint8_t *ptr, unsigned size, uint32_t *const_offset);
270 void si_update_all_texture_descriptors(struct si_context *sctx);
271 void si_shader_change_notify(struct si_context *sctx);
272 void si_update_compressed_colortex_masks(struct si_context *sctx);
273 void si_emit_graphics_shader_userdata(struct si_context *sctx,
274 struct r600_atom *atom);
275 void si_emit_compute_shader_userdata(struct si_context *sctx);
276 void si_set_constant_buffer(struct si_context *sctx,
277 struct si_buffer_resources *buffers,
278 uint slot, struct pipe_constant_buffer *input);
279
280 /* si_state.c */
281 struct si_shader_selector;
282
283 void si_init_atom(struct si_context *sctx, struct r600_atom *atom,
284 struct r600_atom **list_elem,
285 void (*emit_func)(struct si_context *ctx, struct r600_atom *state));
286 boolean si_is_format_supported(struct pipe_screen *screen,
287 enum pipe_format format,
288 enum pipe_texture_target target,
289 unsigned sample_count,
290 unsigned usage);
291 void si_init_state_functions(struct si_context *sctx);
292 void si_init_screen_state_functions(struct si_screen *sscreen);
293 void
294 si_make_buffer_descriptor(struct si_screen *screen, struct r600_resource *buf,
295 enum pipe_format format,
296 unsigned first_element, unsigned last_element,
297 uint32_t *state);
298 void
299 si_make_texture_descriptor(struct si_screen *screen,
300 struct r600_texture *tex,
301 bool sampler,
302 enum pipe_texture_target target,
303 enum pipe_format pipe_format,
304 const unsigned char state_swizzle[4],
305 unsigned first_level, unsigned last_level,
306 unsigned first_layer, unsigned last_layer,
307 unsigned width, unsigned height, unsigned depth,
308 uint32_t *state,
309 uint32_t *fmask_state);
310 struct pipe_sampler_view *
311 si_create_sampler_view_custom(struct pipe_context *ctx,
312 struct pipe_resource *texture,
313 const struct pipe_sampler_view *state,
314 unsigned width0, unsigned height0,
315 unsigned force_level);
316 void si_dec_framebuffer_counters(const struct pipe_framebuffer_state *state);
317
318 /* si_state_shader.c */
319 bool si_update_shaders(struct si_context *sctx);
320 void si_init_shader_functions(struct si_context *sctx);
321 bool si_init_shader_cache(struct si_screen *sscreen);
322 void si_destroy_shader_cache(struct si_screen *sscreen);
323
324 /* si_state_draw.c */
325 void si_emit_cache_flush(struct si_context *sctx, struct r600_atom *atom);
326 void si_ce_pre_draw_synchronization(struct si_context *sctx);
327 void si_ce_post_draw_synchronization(struct si_context *sctx);
328 void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *dinfo);
329 void si_trace_emit(struct si_context *sctx);
330
331
332 static inline unsigned
333 si_tile_mode_index(struct r600_texture *rtex, unsigned level, bool stencil)
334 {
335 if (stencil)
336 return rtex->surface.stencil_tiling_index[level];
337 else
338 return rtex->surface.tiling_index[level];
339 }
340
341 #endif