src/gallium/drivers/radeonsi/si_state.h

   1 /*
   2  * Copyright 2012 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Christian König <christian.koenig@amd.com>
  25  */
  26
  27 #ifndef SI_STATE_H
  28 #define SI_STATE_H
  29
  30 #include "si_pm4.h"
  31 #include "radeon/r600_pipe_common.h"
  32
  33 #include "pipebuffer/pb_slab.h"
  34
  35 #define SI_NUM_GRAPHICS_SHADERS (PIPE_SHADER_TESS_EVAL+1)
  36 #define SI_NUM_SHADERS (PIPE_SHADER_COMPUTE+1)
  37
  38 #define SI_MAX_ATTRIBS                  16
  39 #define SI_NUM_VERTEX_BUFFERS           SI_MAX_ATTRIBS
  40 #define SI_NUM_SAMPLERS                 32 /* OpenGL textures units per shader */
  41 #define SI_NUM_CONST_BUFFERS            16
  42 #define SI_NUM_IMAGES                   16
  43 #define SI_NUM_SHADER_BUFFERS           16
  44
  45 struct si_screen;
  46 struct si_shader;
  47 struct si_shader_selector;
  48
  49 struct si_state_blend {
  50         struct si_pm4_state     pm4;
  51         uint32_t                cb_target_mask;
  52         bool                    alpha_to_coverage;
  53         bool                    alpha_to_one;
  54         bool                    dual_src_blend;
  55         /* Set 0xf or 0x0 (4 bits) per render target if the following is
  56          * true. ANDed with spi_shader_col_format.
  57          */
  58         unsigned                blend_enable_4bit;
  59         unsigned                need_src_alpha_4bit;
  60 };
  61
  62 struct si_state_rasterizer {
  63         struct si_pm4_state     pm4;
  64         /* poly offset states for 16-bit, 24-bit, and 32-bit zbuffers */
  65         struct si_pm4_state     *pm4_poly_offset;
  66         unsigned                pa_sc_line_stipple;
  67         unsigned                pa_cl_clip_cntl;
  68         unsigned                sprite_coord_enable:8;
  69         unsigned                clip_plane_enable:8;
  70         unsigned                flatshade:1;
  71         unsigned                two_side:1;
  72         unsigned                multisample_enable:1;
  73         unsigned                force_persample_interp:1;
  74         unsigned                line_stipple_enable:1;
  75         unsigned                poly_stipple_enable:1;
  76         unsigned                line_smooth:1;
  77         unsigned                poly_smooth:1;
  78         unsigned                uses_poly_offset:1;
  79         unsigned                clamp_fragment_color:1;
  80         unsigned                clamp_vertex_color:1;
  81         unsigned                rasterizer_discard:1;
  82         unsigned                scissor_enable:1;
  83         unsigned                clip_halfz:1;
  84 };
  85
  86 struct si_dsa_stencil_ref_part {
  87         uint8_t                 valuemask[2];
  88         uint8_t                 writemask[2];
  89 };
  90
  91 struct si_state_dsa {
  92         struct si_pm4_state             pm4;
  93         unsigned                        alpha_func;
  94         struct si_dsa_stencil_ref_part  stencil_ref;
  95 };
  96
  97 struct si_stencil_ref {
  98         struct r600_atom                atom;
  99         struct pipe_stencil_ref         state;
 100         struct si_dsa_stencil_ref_part  dsa_part;
 101 };
 102
 103 struct si_vertex_elements
 104 {
 105         uint32_t                        instance_divisors[SI_MAX_ATTRIBS];
 106         uint32_t                        rsrc_word3[SI_MAX_ATTRIBS];
 107         uint16_t                        src_offset[SI_MAX_ATTRIBS];
 108         uint8_t                         fix_fetch[SI_MAX_ATTRIBS];
 109         uint8_t                         format_size[SI_MAX_ATTRIBS];
 110         uint8_t                         vertex_buffer_index[SI_MAX_ATTRIBS];
 111
 112         uint8_t                         count;
 113         bool                            uses_instance_divisors;
 114
 115         uint16_t                        first_vb_use_mask;
 116         /* Vertex buffer descriptor list size aligned for optimal prefetch. */
 117         uint16_t                        desc_list_byte_size;
 118 };
 119
 120 union si_state {
 121         struct {
 122                 struct si_state_blend           *blend;
 123                 struct si_state_rasterizer      *rasterizer;
 124                 struct si_state_dsa             *dsa;
 125                 struct si_pm4_state             *poly_offset;
 126                 struct si_pm4_state             *ls;
 127                 struct si_pm4_state             *hs;
 128                 struct si_pm4_state             *es;
 129                 struct si_pm4_state             *gs;
 130                 struct si_pm4_state             *vgt_shader_config;
 131                 struct si_pm4_state             *vs;
 132                 struct si_pm4_state             *ps;
 133         } named;
 134         struct si_pm4_state     *array[0];
 135 };
 136
 137 #define SI_NUM_STATES (sizeof(union si_state) / sizeof(struct si_pm4_state *))
 138
 139 union si_state_atoms {
 140         struct {
 141                 /* The order matters. */
 142                 struct r600_atom *prefetch_L2;
 143                 struct r600_atom *render_cond;
 144                 struct r600_atom *streamout_begin;
 145                 struct r600_atom *streamout_enable; /* must be after streamout_begin */
 146                 struct r600_atom *framebuffer;
 147                 struct r600_atom *msaa_sample_locs;
 148                 struct r600_atom *db_render_state;
 149                 struct r600_atom *msaa_config;
 150                 struct r600_atom *sample_mask;
 151                 struct r600_atom *cb_render_state;
 152                 struct r600_atom *blend_color;
 153                 struct r600_atom *clip_regs;
 154                 struct r600_atom *clip_state;
 155                 struct r600_atom *shader_userdata;
 156                 struct r600_atom *scissors;
 157                 struct r600_atom *viewports;
 158                 struct r600_atom *stencil_ref;
 159                 struct r600_atom *spi_map;
 160                 struct r600_atom *scratch_state;
 161         } s;
 162         struct r600_atom *array[0];
 163 };
 164
 165 #define SI_NUM_ATOMS (sizeof(union si_state_atoms)/sizeof(struct r600_atom*))
 166
 167 struct si_shader_data {
 168         struct r600_atom        atom;
 169         uint32_t                sh_base[SI_NUM_SHADERS];
 170 };
 171
 172 /* Private read-write buffer slots. */
 173 enum {
 174         SI_ES_RING_ESGS,
 175         SI_GS_RING_ESGS,
 176
 177         SI_RING_GSVS,
 178
 179         SI_VS_STREAMOUT_BUF0,
 180         SI_VS_STREAMOUT_BUF1,
 181         SI_VS_STREAMOUT_BUF2,
 182         SI_VS_STREAMOUT_BUF3,
 183
 184         SI_HS_CONST_DEFAULT_TESS_LEVELS,
 185         SI_VS_CONST_CLIP_PLANES,
 186         SI_PS_CONST_POLY_STIPPLE,
 187         SI_PS_CONST_SAMPLE_POSITIONS,
 188
 189         SI_NUM_RW_BUFFERS,
 190 };
 191
 192 /* Indices into sctx->descriptors, laid out so that gfx and compute pipelines
 193  * are contiguous:
 194  *
 195  *  0 - rw buffers
 196  *  1 - vertex const buffers
 197  *  2 - vertex shader buffers
 198  *   ...
 199  *  5 - fragment const buffers
 200  *   ...
 201  *  21 - compute const buffers
 202  *   ...
 203  */
 204 enum {
 205         SI_SHADER_DESCS_CONST_AND_SHADER_BUFFERS,
 206         SI_SHADER_DESCS_SAMPLERS_AND_IMAGES,
 207         SI_NUM_SHADER_DESCS,
 208 };
 209
 210 #define SI_DESCS_RW_BUFFERS            0
 211 #define SI_DESCS_FIRST_SHADER          1
 212 #define SI_DESCS_FIRST_COMPUTE         (SI_DESCS_FIRST_SHADER + \
 213                                         PIPE_SHADER_COMPUTE * SI_NUM_SHADER_DESCS)
 214 #define SI_NUM_DESCS                   (SI_DESCS_FIRST_SHADER + \
 215                                         SI_NUM_SHADERS * SI_NUM_SHADER_DESCS)
 216
 217 /* This represents descriptors in memory, such as buffer resources,
 218  * image resources, and sampler states.
 219  */
 220 struct si_descriptors {
 221         /* The list of descriptors in malloc'd memory. */
 222         uint32_t *list;
 223         /* The list in mapped GPU memory. */
 224         uint32_t *gpu_list;
 225         /* Slots that have been changed and need to be uploaded. */
 226         uint64_t dirty_mask;
 227
 228         /* The buffer where the descriptors have been uploaded. */
 229         struct r600_resource *buffer;
 230         int buffer_offset; /* can be negative if not using lower slots */
 231
 232         /* The size of one descriptor. */
 233         ubyte element_dw_size;
 234         /* The maximum number of descriptors. */
 235         ubyte num_elements;
 236
 237         /* Offset in CE RAM */
 238         uint16_t ce_offset;
 239
 240         /* Slots allocated in CE RAM. If we get active slots outside of this
 241          * range, direct uploads to memory will be used instead. This basically
 242          * governs switching between onchip (CE) and offchip (upload) modes.
 243          */
 244         ubyte first_ce_slot;
 245         ubyte num_ce_slots;
 246
 247         /* Slots that are used by currently-bound shaders.
 248          * With CE: It determines which slots are dumped to L2.
 249          *          It doesn't skip uploads to CE RAM.
 250          * Without CE: It determines which slots are uploaded.
 251          */
 252         ubyte first_active_slot;
 253         ubyte num_active_slots;
 254
 255         /* Whether CE is used to upload this descriptor array. */
 256         bool uses_ce;
 257
 258         /* The SGPR index where the 64-bit pointer to the descriptor array will
 259          * be stored. */
 260         ubyte shader_userdata_offset;
 261 };
 262
 263 struct si_sampler_views {
 264         struct pipe_sampler_view        *views[SI_NUM_SAMPLERS];
 265         struct si_sampler_state         *sampler_states[SI_NUM_SAMPLERS];
 266
 267         /* The i-th bit is set if that element is enabled (non-NULL resource). */
 268         unsigned                        enabled_mask;
 269 };
 270
 271 struct si_buffer_resources {
 272         struct pipe_resource            **buffers; /* this has num_buffers elements */
 273
 274         enum radeon_bo_usage            shader_usage:4; /* READ, WRITE, or READWRITE */
 275         enum radeon_bo_usage            shader_usage_constbuf:4;
 276         enum radeon_bo_priority         priority:6;
 277         enum radeon_bo_priority         priority_constbuf:6;
 278
 279         /* The i-th bit is set if that element is enabled (non-NULL resource). */
 280         unsigned                        enabled_mask;
 281 };
 282
 283 #define si_pm4_block_idx(member) \
 284         (offsetof(union si_state, named.member) / sizeof(struct si_pm4_state *))
 285
 286 #define si_pm4_state_changed(sctx, member) \
 287         ((sctx)->queued.named.member != (sctx)->emitted.named.member)
 288
 289 #define si_pm4_bind_state(sctx, member, value) \
 290         do { \
 291                 (sctx)->queued.named.member = (value); \
 292                 (sctx)->dirty_states |= 1 << si_pm4_block_idx(member); \
 293         } while(0)
 294
 295 #define si_pm4_delete_state(sctx, member, value) \
 296         do { \
 297                 if ((sctx)->queued.named.member == (value)) { \
 298                         (sctx)->queued.named.member = NULL; \
 299                 } \
 300                 si_pm4_free_state(sctx, (struct si_pm4_state *)(value), \
 301                                   si_pm4_block_idx(member)); \
 302         } while(0)
 303
 304 /* si_descriptors.c */
 305 void si_ce_save_all_descriptors_at_ib_end(struct si_context* sctx);
 306 void si_ce_restore_all_descriptors_at_ib_start(struct si_context *sctx);
 307 void si_ce_enable_loads(struct radeon_winsys_cs *ib);
 308 void si_set_mutable_tex_desc_fields(struct si_screen *sscreen,
 309                                     struct r600_texture *tex,
 310                                     const struct legacy_surf_level *base_level_info,
 311                                     unsigned base_level, unsigned first_level,
 312                                     unsigned block_width, bool is_stencil,
 313                                     uint32_t *state);
 314 void si_get_pipe_constant_buffer(struct si_context *sctx, uint shader,
 315                                  uint slot, struct pipe_constant_buffer *cbuf);
 316 void si_get_shader_buffers(struct si_context *sctx,
 317                            enum pipe_shader_type shader,
 318                            uint start_slot, uint count,
 319                            struct pipe_shader_buffer *sbuf);
 320 void si_set_ring_buffer(struct pipe_context *ctx, uint slot,
 321                         struct pipe_resource *buffer,
 322                         unsigned stride, unsigned num_records,
 323                         bool add_tid, bool swizzle,
 324                         unsigned element_size, unsigned index_stride, uint64_t offset);
 325 void si_init_all_descriptors(struct si_context *sctx);
 326 bool si_upload_vertex_buffer_descriptors(struct si_context *sctx);
 327 bool si_upload_graphics_shader_descriptors(struct si_context *sctx);
 328 bool si_upload_compute_shader_descriptors(struct si_context *sctx);
 329 void si_release_all_descriptors(struct si_context *sctx);
 330 void si_all_descriptors_begin_new_cs(struct si_context *sctx);
 331 void si_all_resident_buffers_begin_new_cs(struct si_context *sctx);
 332 void si_upload_const_buffer(struct si_context *sctx, struct r600_resource **rbuffer,
 333                             const uint8_t *ptr, unsigned size, uint32_t *const_offset);
 334 void si_update_all_texture_descriptors(struct si_context *sctx);
 335 void si_shader_change_notify(struct si_context *sctx);
 336 void si_update_needs_color_decompress_masks(struct si_context *sctx);
 337 void si_emit_graphics_shader_userdata(struct si_context *sctx,
 338                                       struct r600_atom *atom);
 339 void si_emit_compute_shader_userdata(struct si_context *sctx);
 340 void si_set_rw_buffer(struct si_context *sctx,
 341                       uint slot, const struct pipe_constant_buffer *input);
 342 void si_set_active_descriptors(struct si_context *sctx, unsigned desc_idx,
 343                                uint64_t new_active_mask);
 344 void si_set_active_descriptors_for_shader(struct si_context *sctx,
 345                                           struct si_shader_selector *sel);
 346 bool si_bindless_descriptor_can_reclaim_slab(void *priv,
 347                                              struct pb_slab_entry *entry);
 348 struct pb_slab *si_bindless_descriptor_slab_alloc(void *priv, unsigned heap,
 349                                                   unsigned entry_size,
 350                                                   unsigned group_index);
 351 void si_bindless_descriptor_slab_free(void *priv, struct pb_slab *pslab);
 352
 353 /* si_state.c */
 354 struct si_shader_selector;
 355
 356 void si_init_atom(struct si_context *sctx, struct r600_atom *atom,
 357                   struct r600_atom **list_elem,
 358                   void (*emit_func)(struct si_context *ctx, struct r600_atom *state));
 359 void si_init_state_functions(struct si_context *sctx);
 360 void si_init_screen_state_functions(struct si_screen *sscreen);
 361 void
 362 si_make_buffer_descriptor(struct si_screen *screen, struct r600_resource *buf,
 363                           enum pipe_format format,
 364                           unsigned offset, unsigned size,
 365                           uint32_t *state);
 366 void
 367 si_make_texture_descriptor(struct si_screen *screen,
 368                            struct r600_texture *tex,
 369                            bool sampler,
 370                            enum pipe_texture_target target,
 371                            enum pipe_format pipe_format,
 372                            const unsigned char state_swizzle[4],
 373                            unsigned first_level, unsigned last_level,
 374                            unsigned first_layer, unsigned last_layer,
 375                            unsigned width, unsigned height, unsigned depth,
 376                            uint32_t *state,
 377                            uint32_t *fmask_state);
 378 struct pipe_sampler_view *
 379 si_create_sampler_view_custom(struct pipe_context *ctx,
 380                               struct pipe_resource *texture,
 381                               const struct pipe_sampler_view *state,
 382                               unsigned width0, unsigned height0,
 383                               unsigned force_level);
 384
 385 /* si_state_shader.c */
 386 bool si_update_shaders(struct si_context *sctx);
 387 void si_init_shader_functions(struct si_context *sctx);
 388 bool si_init_shader_cache(struct si_screen *sscreen);
 389 void si_destroy_shader_cache(struct si_screen *sscreen);
 390 void si_init_shader_selector_async(void *job, int thread_index);
 391 void si_get_active_slot_masks(const struct tgsi_shader_info *info,
 392                               uint32_t *const_and_shader_buffers,
 393                               uint64_t *samplers_and_images);
 394
 395 /* si_state_draw.c */
 396 void si_init_ia_multi_vgt_param_table(struct si_context *sctx);
 397 void si_emit_cache_flush(struct si_context *sctx);
 398 void si_ce_pre_draw_synchronization(struct si_context *sctx);
 399 void si_ce_post_draw_synchronization(struct si_context *sctx);
 400 void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *dinfo);
 401 void si_trace_emit(struct si_context *sctx);
 402
 403
 404 static inline unsigned
 405 si_tile_mode_index(struct r600_texture *rtex, unsigned level, bool stencil)
 406 {
 407         if (stencil)
 408                 return rtex->surface.u.legacy.stencil_tiling_index[level];
 409         else
 410                 return rtex->surface.u.legacy.tiling_index[level];
 411 }
 412
 413 static inline unsigned si_get_constbuf_slot(unsigned slot)
 414 {
 415         /* Constant buffers are in slots [16..31], ascending */
 416         return SI_NUM_SHADER_BUFFERS + slot;
 417 }
 418
 419 static inline unsigned si_get_shaderbuf_slot(unsigned slot)
 420 {
 421         /* shader buffers are in slots [15..0], descending */
 422         return SI_NUM_SHADER_BUFFERS - 1 - slot;
 423 }
 424
 425 static inline unsigned si_get_sampler_slot(unsigned slot)
 426 {
 427         /* samplers are in slots [8..39], ascending */
 428         return SI_NUM_IMAGES / 2 + slot;
 429 }
 430
 431 static inline unsigned si_get_image_slot(unsigned slot)
 432 {
 433         /* images are in slots [15..0] (sampler slots [7..0]), descending */
 434         return SI_NUM_IMAGES - 1 - slot;
 435 }
 436
 437 #endif