src/gallium/drivers/radeonsi/si_state.h

   1 /*
   2  * Copyright 2012 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Christian König <christian.koenig@amd.com>
  25  */
  26
  27 #ifndef SI_STATE_H
  28 #define SI_STATE_H
  29
  30 #include "si_pm4.h"
  31 #include "radeon/r600_pipe_common.h"
  32
  33 #define SI_NUM_GRAPHICS_SHADERS (PIPE_SHADER_TESS_EVAL+1)
  34 #define SI_NUM_SHADERS (PIPE_SHADER_COMPUTE+1)
  35
  36 #define SI_MAX_ATTRIBS                  16
  37 #define SI_NUM_VERTEX_BUFFERS           SI_MAX_ATTRIBS
  38 #define SI_NUM_SAMPLERS                 32 /* OpenGL textures units per shader */
  39 #define SI_NUM_CONST_BUFFERS            16
  40 #define SI_NUM_IMAGES                   16
  41 #define SI_NUM_SHADER_BUFFERS           16
  42
  43 struct si_screen;
  44 struct si_shader;
  45
  46 struct si_state_blend {
  47         struct si_pm4_state     pm4;
  48         uint32_t                cb_target_mask;
  49         bool                    alpha_to_coverage;
  50         bool                    alpha_to_one;
  51         bool                    dual_src_blend;
  52         /* Set 0xf or 0x0 (4 bits) per render target if the following is
  53          * true. ANDed with spi_shader_col_format.
  54          */
  55         unsigned                blend_enable_4bit;
  56         unsigned                need_src_alpha_4bit;
  57 };
  58
  59 struct si_state_rasterizer {
  60         struct si_pm4_state     pm4;
  61         /* poly offset states for 16-bit, 24-bit, and 32-bit zbuffers */
  62         struct si_pm4_state     pm4_poly_offset[3];
  63         bool                    flatshade;
  64         bool                    two_side;
  65         bool                    multisample_enable;
  66         bool                    force_persample_interp;
  67         bool                    line_stipple_enable;
  68         unsigned                sprite_coord_enable;
  69         unsigned                pa_sc_line_stipple;
  70         unsigned                pa_cl_clip_cntl;
  71         unsigned                clip_plane_enable;
  72         bool                    poly_stipple_enable;
  73         bool                    line_smooth;
  74         bool                    poly_smooth;
  75         bool                    uses_poly_offset;
  76         bool                    clamp_fragment_color;
  77         bool                    clamp_vertex_color;
  78         bool                    rasterizer_discard;
  79         bool                    scissor_enable;
  80         bool                    clip_halfz;
  81 };
  82
  83 struct si_dsa_stencil_ref_part {
  84         uint8_t                 valuemask[2];
  85         uint8_t                 writemask[2];
  86 };
  87
  88 struct si_state_dsa {
  89         struct si_pm4_state             pm4;
  90         unsigned                        alpha_func;
  91         struct si_dsa_stencil_ref_part  stencil_ref;
  92 };
  93
  94 struct si_stencil_ref {
  95         struct r600_atom                atom;
  96         struct pipe_stencil_ref         state;
  97         struct si_dsa_stencil_ref_part  dsa_part;
  98 };
  99
 100 struct si_vertex_element
 101 {
 102         unsigned                        count;
 103         unsigned                        first_vb_use_mask;
 104         /* Vertex buffer descriptor list size aligned for optimal prefetch. */
 105         unsigned                        desc_list_byte_size;
 106
 107         uint8_t                         fix_fetch[SI_MAX_ATTRIBS];
 108         uint32_t                        rsrc_word3[SI_MAX_ATTRIBS];
 109         uint32_t                        format_size[SI_MAX_ATTRIBS];
 110         struct pipe_vertex_element      elements[SI_MAX_ATTRIBS];
 111 };
 112
 113 union si_state {
 114         struct {
 115                 struct si_state_blend           *blend;
 116                 struct si_state_rasterizer      *rasterizer;
 117                 struct si_state_dsa             *dsa;
 118                 struct si_pm4_state             *poly_offset;
 119                 struct si_pm4_state             *ls;
 120                 struct si_pm4_state             *hs;
 121                 struct si_pm4_state             *es;
 122                 struct si_pm4_state             *gs;
 123                 struct si_pm4_state             *vgt_shader_config;
 124                 struct si_pm4_state             *vs;
 125                 struct si_pm4_state             *ps;
 126         } named;
 127         struct si_pm4_state     *array[0];
 128 };
 129
 130 #define SI_NUM_STATES (sizeof(union si_state) / sizeof(struct si_pm4_state *))
 131
 132 union si_state_atoms {
 133         struct {
 134                 /* The order matters. */
 135                 struct r600_atom *prefetch_L2;
 136                 struct r600_atom *render_cond;
 137                 struct r600_atom *streamout_begin;
 138                 struct r600_atom *streamout_enable; /* must be after streamout_begin */
 139                 struct r600_atom *framebuffer;
 140                 struct r600_atom *msaa_sample_locs;
 141                 struct r600_atom *db_render_state;
 142                 struct r600_atom *msaa_config;
 143                 struct r600_atom *sample_mask;
 144                 struct r600_atom *cb_render_state;
 145                 struct r600_atom *blend_color;
 146                 struct r600_atom *clip_regs;
 147                 struct r600_atom *clip_state;
 148                 struct r600_atom *shader_userdata;
 149                 struct r600_atom *scissors;
 150                 struct r600_atom *viewports;
 151                 struct r600_atom *stencil_ref;
 152                 struct r600_atom *spi_map;
 153                 struct r600_atom *scratch_state;
 154         } s;
 155         struct r600_atom *array[0];
 156 };
 157
 158 #define SI_NUM_ATOMS (sizeof(union si_state_atoms)/sizeof(struct r600_atom*))
 159
 160 struct si_shader_data {
 161         struct r600_atom        atom;
 162         uint32_t                sh_base[SI_NUM_SHADERS];
 163 };
 164
 165 /* Private read-write buffer slots. */
 166 enum {
 167         SI_ES_RING_ESGS,
 168         SI_GS_RING_ESGS,
 169
 170         SI_RING_GSVS,
 171
 172         SI_VS_STREAMOUT_BUF0,
 173         SI_VS_STREAMOUT_BUF1,
 174         SI_VS_STREAMOUT_BUF2,
 175         SI_VS_STREAMOUT_BUF3,
 176
 177         SI_HS_CONST_DEFAULT_TESS_LEVELS,
 178         SI_VS_CONST_CLIP_PLANES,
 179         SI_PS_CONST_POLY_STIPPLE,
 180         SI_PS_CONST_SAMPLE_POSITIONS,
 181
 182         SI_NUM_RW_BUFFERS,
 183 };
 184
 185 /* Indices into sctx->descriptors, laid out so that gfx and compute pipelines
 186  * are contiguous:
 187  *
 188  *  0 - rw buffers
 189  *  1 - vertex const buffers
 190  *  2 - vertex shader buffers
 191  *   ...
 192  *  5 - fragment const buffers
 193  *   ...
 194  *  21 - compute const buffers
 195  *   ...
 196  */
 197 enum {
 198         SI_SHADER_DESCS_CONST_AND_SHADER_BUFFERS,
 199         SI_SHADER_DESCS_SAMPLERS_AND_IMAGES,
 200         SI_NUM_SHADER_DESCS,
 201 };
 202
 203 #define SI_DESCS_RW_BUFFERS            0
 204 #define SI_DESCS_FIRST_SHADER          1
 205 #define SI_DESCS_FIRST_COMPUTE         (SI_DESCS_FIRST_SHADER + \
 206                                         PIPE_SHADER_COMPUTE * SI_NUM_SHADER_DESCS)
 207 #define SI_NUM_DESCS                   (SI_DESCS_FIRST_SHADER + \
 208                                         SI_NUM_SHADERS * SI_NUM_SHADER_DESCS)
 209
 210 /* This represents descriptors in memory, such as buffer resources,
 211  * image resources, and sampler states.
 212  */
 213 struct si_descriptors {
 214         /* The list of descriptors in malloc'd memory. */
 215         uint32_t *list;
 216         /* The list in mapped GPU memory. */
 217         uint32_t *gpu_list;
 218         /* The size of one descriptor. */
 219         unsigned element_dw_size;
 220         /* The maximum number of descriptors. */
 221         unsigned num_elements;
 222
 223         /* The buffer where the descriptors have been uploaded. */
 224         struct r600_resource *buffer;
 225         unsigned buffer_offset;
 226
 227         /* Offset in CE RAM */
 228         unsigned ce_offset;
 229
 230         /* elements of the list that are changed and need to be uploaded */
 231         uint64_t dirty_mask;
 232
 233         /* Whether CE is used to upload this descriptor array. */
 234         bool uses_ce;
 235
 236         /* The shader userdata offset within a shader where the 64-bit pointer to the descriptor
 237          * array will be stored. */
 238         unsigned shader_userdata_offset;
 239 };
 240
 241 struct si_sampler_views {
 242         struct pipe_sampler_view        *views[SI_NUM_SAMPLERS];
 243         struct si_sampler_state         *sampler_states[SI_NUM_SAMPLERS];
 244
 245         /* The i-th bit is set if that element is enabled (non-NULL resource). */
 246         unsigned                        enabled_mask;
 247 };
 248
 249 struct si_buffer_resources {
 250         enum radeon_bo_usage            shader_usage; /* READ, WRITE, or READWRITE */
 251         enum radeon_bo_usage            shader_usage_constbuf;
 252         enum radeon_bo_priority         priority;
 253         enum radeon_bo_priority         priority_constbuf;
 254         struct pipe_resource            **buffers; /* this has num_buffers elements */
 255
 256         /* The i-th bit is set if that element is enabled (non-NULL resource). */
 257         unsigned                        enabled_mask;
 258 };
 259
 260 #define si_pm4_block_idx(member) \
 261         (offsetof(union si_state, named.member) / sizeof(struct si_pm4_state *))
 262
 263 #define si_pm4_state_changed(sctx, member) \
 264         ((sctx)->queued.named.member != (sctx)->emitted.named.member)
 265
 266 #define si_pm4_bind_state(sctx, member, value) \
 267         do { \
 268                 (sctx)->queued.named.member = (value); \
 269                 (sctx)->dirty_states |= 1 << si_pm4_block_idx(member); \
 270         } while(0)
 271
 272 #define si_pm4_delete_state(sctx, member, value) \
 273         do { \
 274                 if ((sctx)->queued.named.member == (value)) { \
 275                         (sctx)->queued.named.member = NULL; \
 276                 } \
 277                 si_pm4_free_state(sctx, (struct si_pm4_state *)(value), \
 278                                   si_pm4_block_idx(member)); \
 279         } while(0)
 280
 281 /* si_descriptors.c */
 282 void si_ce_save_all_descriptors_at_ib_end(struct si_context* sctx);
 283 void si_ce_restore_all_descriptors_at_ib_start(struct si_context *sctx);
 284 void si_ce_enable_loads(struct radeon_winsys_cs *ib);
 285 void si_set_mutable_tex_desc_fields(struct si_screen *sscreen,
 286                                     struct r600_texture *tex,
 287                                     const struct legacy_surf_level *base_level_info,
 288                                     unsigned base_level, unsigned first_level,
 289                                     unsigned block_width, bool is_stencil,
 290                                     uint32_t *state);
 291 void si_get_pipe_constant_buffer(struct si_context *sctx, uint shader,
 292                                  uint slot, struct pipe_constant_buffer *cbuf);
 293 void si_get_shader_buffers(struct si_context *sctx,
 294                            enum pipe_shader_type shader,
 295                            uint start_slot, uint count,
 296                            struct pipe_shader_buffer *sbuf);
 297 void si_set_ring_buffer(struct pipe_context *ctx, uint slot,
 298                         struct pipe_resource *buffer,
 299                         unsigned stride, unsigned num_records,
 300                         bool add_tid, bool swizzle,
 301                         unsigned element_size, unsigned index_stride, uint64_t offset);
 302 void si_init_all_descriptors(struct si_context *sctx);
 303 bool si_upload_vertex_buffer_descriptors(struct si_context *sctx);
 304 bool si_upload_graphics_shader_descriptors(struct si_context *sctx);
 305 bool si_upload_compute_shader_descriptors(struct si_context *sctx);
 306 void si_release_all_descriptors(struct si_context *sctx);
 307 void si_all_descriptors_begin_new_cs(struct si_context *sctx);
 308 void si_upload_const_buffer(struct si_context *sctx, struct r600_resource **rbuffer,
 309                             const uint8_t *ptr, unsigned size, uint32_t *const_offset);
 310 void si_update_all_texture_descriptors(struct si_context *sctx);
 311 void si_shader_change_notify(struct si_context *sctx);
 312 void si_update_compressed_colortex_masks(struct si_context *sctx);
 313 void si_emit_graphics_shader_userdata(struct si_context *sctx,
 314                                       struct r600_atom *atom);
 315 void si_emit_compute_shader_userdata(struct si_context *sctx);
 316 void si_set_rw_buffer(struct si_context *sctx,
 317                       uint slot, const struct pipe_constant_buffer *input);
 318 /* si_state.c */
 319 struct si_shader_selector;
 320
 321 void si_init_atom(struct si_context *sctx, struct r600_atom *atom,
 322                   struct r600_atom **list_elem,
 323                   void (*emit_func)(struct si_context *ctx, struct r600_atom *state));
 324 void si_init_state_functions(struct si_context *sctx);
 325 void si_init_screen_state_functions(struct si_screen *sscreen);
 326 void
 327 si_make_buffer_descriptor(struct si_screen *screen, struct r600_resource *buf,
 328                           enum pipe_format format,
 329                           unsigned offset, unsigned size,
 330                           uint32_t *state);
 331 void
 332 si_make_texture_descriptor(struct si_screen *screen,
 333                            struct r600_texture *tex,
 334                            bool sampler,
 335                            enum pipe_texture_target target,
 336                            enum pipe_format pipe_format,
 337                            const unsigned char state_swizzle[4],
 338                            unsigned first_level, unsigned last_level,
 339                            unsigned first_layer, unsigned last_layer,
 340                            unsigned width, unsigned height, unsigned depth,
 341                            uint32_t *state,
 342                            uint32_t *fmask_state);
 343 struct pipe_sampler_view *
 344 si_create_sampler_view_custom(struct pipe_context *ctx,
 345                               struct pipe_resource *texture,
 346                               const struct pipe_sampler_view *state,
 347                               unsigned width0, unsigned height0,
 348                               unsigned force_level);
 349
 350 /* si_state_shader.c */
 351 bool si_update_shaders(struct si_context *sctx);
 352 void si_init_shader_functions(struct si_context *sctx);
 353 bool si_init_shader_cache(struct si_screen *sscreen);
 354 void si_destroy_shader_cache(struct si_screen *sscreen);
 355 void si_init_shader_selector_async(void *job, int thread_index);
 356 void si_get_active_slot_masks(const struct tgsi_shader_info *info,
 357                               uint32_t *const_and_shader_buffers,
 358                               uint64_t *samplers_and_images);
 359
 360 /* si_state_draw.c */
 361 void si_init_ia_multi_vgt_param_table(struct si_context *sctx);
 362 void si_emit_cache_flush(struct si_context *sctx);
 363 void si_ce_pre_draw_synchronization(struct si_context *sctx);
 364 void si_ce_post_draw_synchronization(struct si_context *sctx);
 365 void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *dinfo);
 366 void si_trace_emit(struct si_context *sctx);
 367
 368
 369 static inline unsigned
 370 si_tile_mode_index(struct r600_texture *rtex, unsigned level, bool stencil)
 371 {
 372         if (stencil)
 373                 return rtex->surface.u.legacy.stencil_tiling_index[level];
 374         else
 375                 return rtex->surface.u.legacy.tiling_index[level];
 376 }
 377
 378 static inline unsigned si_get_constbuf_slot(unsigned slot)
 379 {
 380         /* Constant buffers are in slots [16..31], ascending */
 381         return SI_NUM_SHADER_BUFFERS + slot;
 382 }
 383
 384 static inline unsigned si_get_shaderbuf_slot(unsigned slot)
 385 {
 386         /* shader buffers are in slots [15..0], descending */
 387         return SI_NUM_SHADER_BUFFERS - 1 - slot;
 388 }
 389
 390 static inline unsigned si_get_sampler_slot(unsigned slot)
 391 {
 392         /* samplers are in slots [8..39], ascending */
 393         return SI_NUM_IMAGES / 2 + slot;
 394 }
 395
 396 static inline unsigned si_get_image_slot(unsigned slot)
 397 {
 398         /* images are in slots [15..0] (sampler slots [7..0]), descending */
 399         return SI_NUM_IMAGES - 1 - slot;
 400 }
 401
 402 #endif