src/gallium/drivers/radeonsi/si_state.h

   1 /*
   2  * Copyright 2012 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Christian König <christian.koenig@amd.com>
  25  */
  26
  27 #ifndef SI_STATE_H
  28 #define SI_STATE_H
  29
  30 #include "si_pm4.h"
  31 #include "radeon/r600_pipe_common.h"
  32
  33 #define SI_NUM_GRAPHICS_SHADERS (PIPE_SHADER_TESS_EVAL+1)
  34 #define SI_NUM_SHADERS (PIPE_SHADER_COMPUTE+1)
  35
  36 #define SI_MAX_ATTRIBS                  16
  37 #define SI_NUM_VERTEX_BUFFERS           SI_MAX_ATTRIBS
  38 #define SI_NUM_SAMPLERS                 32 /* OpenGL textures units per shader */
  39 #define SI_NUM_CONST_BUFFERS            16
  40 #define SI_NUM_IMAGES                   16
  41 #define SI_NUM_SHADER_BUFFERS           16
  42
  43 struct si_screen;
  44 struct si_shader;
  45
  46 struct si_state_blend {
  47         struct si_pm4_state     pm4;
  48         uint32_t                cb_target_mask;
  49         bool                    alpha_to_coverage;
  50         bool                    alpha_to_one;
  51         bool                    dual_src_blend;
  52         /* Set 0xf or 0x0 (4 bits) per render target if the following is
  53          * true. ANDed with spi_shader_col_format.
  54          */
  55         unsigned                blend_enable_4bit;
  56         unsigned                need_src_alpha_4bit;
  57 };
  58
  59 struct si_state_rasterizer {
  60         struct si_pm4_state     pm4;
  61         /* poly offset states for 16-bit, 24-bit, and 32-bit zbuffers */
  62         struct si_pm4_state     pm4_poly_offset[3];
  63         bool                    flatshade;
  64         bool                    two_side;
  65         bool                    multisample_enable;
  66         bool                    force_persample_interp;
  67         bool                    line_stipple_enable;
  68         unsigned                sprite_coord_enable;
  69         unsigned                pa_sc_line_stipple;
  70         unsigned                pa_cl_clip_cntl;
  71         unsigned                clip_plane_enable;
  72         bool                    poly_stipple_enable;
  73         bool                    line_smooth;
  74         bool                    poly_smooth;
  75         bool                    uses_poly_offset;
  76         bool                    clamp_fragment_color;
  77         bool                    rasterizer_discard;
  78         bool                    scissor_enable;
  79         bool                    clip_halfz;
  80 };
  81
  82 struct si_dsa_stencil_ref_part {
  83         uint8_t                 valuemask[2];
  84         uint8_t                 writemask[2];
  85 };
  86
  87 struct si_state_dsa {
  88         struct si_pm4_state             pm4;
  89         unsigned                        alpha_func;
  90         struct si_dsa_stencil_ref_part  stencil_ref;
  91 };
  92
  93 struct si_stencil_ref {
  94         struct r600_atom                atom;
  95         struct pipe_stencil_ref         state;
  96         struct si_dsa_stencil_ref_part  dsa_part;
  97 };
  98
  99 struct si_vertex_element
 100 {
 101         unsigned                        count;
 102         uint32_t                        rsrc_word3[SI_MAX_ATTRIBS];
 103         uint32_t                        format_size[SI_MAX_ATTRIBS];
 104         struct pipe_vertex_element      elements[SI_MAX_ATTRIBS];
 105 };
 106
 107 union si_state {
 108         struct {
 109                 struct si_state_blend           *blend;
 110                 struct si_state_rasterizer      *rasterizer;
 111                 struct si_state_dsa             *dsa;
 112                 struct si_pm4_state             *poly_offset;
 113                 struct si_pm4_state             *ls;
 114                 struct si_pm4_state             *hs;
 115                 struct si_pm4_state             *es;
 116                 struct si_pm4_state             *gs;
 117                 struct si_pm4_state             *vgt_shader_config;
 118                 struct si_pm4_state             *vs;
 119                 struct si_pm4_state             *ps;
 120         } named;
 121         struct si_pm4_state     *array[0];
 122 };
 123
 124 union si_state_atoms {
 125         struct {
 126                 /* The order matters. */
 127                 struct r600_atom *cache_flush;
 128                 struct r600_atom *render_cond;
 129                 struct r600_atom *streamout_begin;
 130                 struct r600_atom *streamout_enable; /* must be after streamout_begin */
 131                 struct r600_atom *framebuffer;
 132                 struct r600_atom *msaa_sample_locs;
 133                 struct r600_atom *db_render_state;
 134                 struct r600_atom *msaa_config;
 135                 struct r600_atom *sample_mask;
 136                 struct r600_atom *cb_render_state;
 137                 struct r600_atom *blend_color;
 138                 struct r600_atom *clip_regs;
 139                 struct r600_atom *clip_state;
 140                 struct r600_atom *shader_userdata;
 141                 struct r600_atom *scissors;
 142                 struct r600_atom *viewports;
 143                 struct r600_atom *stencil_ref;
 144                 struct r600_atom *spi_map;
 145         } s;
 146         struct r600_atom *array[0];
 147 };
 148
 149 #define SI_NUM_ATOMS (sizeof(union si_state_atoms)/sizeof(struct r600_atom*))
 150
 151 struct si_shader_data {
 152         struct r600_atom        atom;
 153         uint32_t                sh_base[SI_NUM_SHADERS];
 154 };
 155
 156 /* Private read-write buffer slots. */
 157 enum {
 158         SI_HS_RING_TESS_FACTOR,
 159         SI_HS_RING_TESS_OFFCHIP,
 160
 161         SI_ES_RING_ESGS,
 162         SI_GS_RING_ESGS,
 163
 164         SI_GS_RING_GSVS0,
 165         SI_GS_RING_GSVS1,
 166         SI_GS_RING_GSVS2,
 167         SI_GS_RING_GSVS3,
 168         SI_VS_RING_GSVS,
 169
 170         SI_VS_STREAMOUT_BUF0,
 171         SI_VS_STREAMOUT_BUF1,
 172         SI_VS_STREAMOUT_BUF2,
 173         SI_VS_STREAMOUT_BUF3,
 174
 175         SI_HS_CONST_DEFAULT_TESS_LEVELS,
 176         SI_VS_CONST_CLIP_PLANES,
 177         SI_PS_CONST_POLY_STIPPLE,
 178         SI_PS_CONST_SAMPLE_POSITIONS,
 179
 180         SI_NUM_RW_BUFFERS,
 181 };
 182
 183 /* Indices into sctx->descriptors, laid out so that gfx and compute pipelines
 184  * are contiguous:
 185  *
 186  *  0 - rw buffers
 187  *  1 - vertex const buffers
 188  *  2 - vertex shader buffers
 189  *   ...
 190  *  5 - fragment const buffers
 191  *   ...
 192  *  21 - compute const buffers
 193  *   ...
 194  */
 195 #define SI_SHADER_DESCS_CONST_BUFFERS  0
 196 #define SI_SHADER_DESCS_SHADER_BUFFERS 1
 197 #define SI_SHADER_DESCS_SAMPLERS       2
 198 #define SI_SHADER_DESCS_IMAGES         3
 199 #define SI_NUM_SHADER_DESCS            4
 200
 201 #define SI_DESCS_RW_BUFFERS            0
 202 #define SI_DESCS_FIRST_SHADER          1
 203 #define SI_DESCS_FIRST_COMPUTE         (SI_DESCS_FIRST_SHADER + \
 204                                         PIPE_SHADER_COMPUTE * SI_NUM_SHADER_DESCS)
 205 #define SI_NUM_DESCS                   (SI_DESCS_FIRST_SHADER + \
 206                                         SI_NUM_SHADERS * SI_NUM_SHADER_DESCS)
 207
 208 /* This represents descriptors in memory, such as buffer resources,
 209  * image resources, and sampler states.
 210  */
 211 struct si_descriptors {
 212         /* The list of descriptors in malloc'd memory. */
 213         uint32_t *list;
 214         /* The size of one descriptor. */
 215         unsigned element_dw_size;
 216         /* The maximum number of descriptors. */
 217         unsigned num_elements;
 218
 219         /* The buffer where the descriptors have been uploaded. */
 220         struct r600_resource *buffer;
 221         unsigned buffer_offset;
 222
 223         /* Offset in CE RAM */
 224         unsigned ce_offset;
 225
 226         /* elements of the list that are changed and need to be uploaded */
 227         unsigned dirty_mask;
 228
 229         /* Whether the CE ram is dirty and needs to be reinitialized entirely
 230          * before we can do partial updates. */
 231         bool ce_ram_dirty;
 232
 233         /* The shader userdata offset within a shader where the 64-bit pointer to the descriptor
 234          * array will be stored. */
 235         unsigned shader_userdata_offset;
 236         /* Whether the pointer should be re-emitted. */
 237         bool pointer_dirty;
 238 };
 239
 240 struct si_sampler_views {
 241         struct pipe_sampler_view        *views[SI_NUM_SAMPLERS];
 242         void                            *sampler_states[SI_NUM_SAMPLERS];
 243
 244         /* The i-th bit is set if that element is enabled (non-NULL resource). */
 245         unsigned                        enabled_mask;
 246 };
 247
 248 struct si_buffer_resources {
 249         enum radeon_bo_usage            shader_usage; /* READ, WRITE, or READWRITE */
 250         enum radeon_bo_priority         priority;
 251         struct pipe_resource            **buffers; /* this has num_buffers elements */
 252
 253         /* The i-th bit is set if that element is enabled (non-NULL resource). */
 254         unsigned                        enabled_mask;
 255 };
 256
 257 #define si_pm4_block_idx(member) \
 258         (offsetof(union si_state, named.member) / sizeof(struct si_pm4_state *))
 259
 260 #define si_pm4_state_changed(sctx, member) \
 261         ((sctx)->queued.named.member != (sctx)->emitted.named.member)
 262
 263 #define si_pm4_bind_state(sctx, member, value) \
 264         do { \
 265                 (sctx)->queued.named.member = (value); \
 266         } while(0)
 267
 268 #define si_pm4_delete_state(sctx, member, value) \
 269         do { \
 270                 if ((sctx)->queued.named.member == (value)) { \
 271                         (sctx)->queued.named.member = NULL; \
 272                 } \
 273                 si_pm4_free_state(sctx, (struct si_pm4_state *)(value), \
 274                                   si_pm4_block_idx(member)); \
 275         } while(0)
 276
 277 /* si_descriptors.c */
 278 void si_ce_reinitialize_all_descriptors(struct si_context *sctx);
 279 void si_ce_enable_loads(struct radeon_winsys_cs *ib);
 280 void si_set_mutable_tex_desc_fields(struct r600_texture *tex,
 281                                     const struct radeon_surf_level *base_level_info,
 282                                     unsigned base_level, unsigned first_level,
 283                                     unsigned block_width, bool is_stencil,
 284                                     uint32_t *state);
 285 void si_set_ring_buffer(struct pipe_context *ctx, uint slot,
 286                         struct pipe_resource *buffer,
 287                         unsigned stride, unsigned num_records,
 288                         bool add_tid, bool swizzle,
 289                         unsigned element_size, unsigned index_stride, uint64_t offset);
 290 void si_init_all_descriptors(struct si_context *sctx);
 291 bool si_upload_vertex_buffer_descriptors(struct si_context *sctx);
 292 bool si_upload_graphics_shader_descriptors(struct si_context *sctx);
 293 bool si_upload_compute_shader_descriptors(struct si_context *sctx);
 294 void si_release_all_descriptors(struct si_context *sctx);
 295 void si_all_descriptors_begin_new_cs(struct si_context *sctx);
 296 void si_upload_const_buffer(struct si_context *sctx, struct r600_resource **rbuffer,
 297                             const uint8_t *ptr, unsigned size, uint32_t *const_offset);
 298 void si_update_all_texture_descriptors(struct si_context *sctx);
 299 void si_shader_change_notify(struct si_context *sctx);
 300 void si_update_compressed_colortex_masks(struct si_context *sctx);
 301 void si_emit_graphics_shader_userdata(struct si_context *sctx,
 302                                       struct r600_atom *atom);
 303 void si_emit_compute_shader_userdata(struct si_context *sctx);
 304 void si_set_rw_buffer(struct si_context *sctx,
 305                       uint slot, const struct pipe_constant_buffer *input);
 306 /* si_state.c */
 307 struct si_shader_selector;
 308
 309 void si_init_atom(struct si_context *sctx, struct r600_atom *atom,
 310                   struct r600_atom **list_elem,
 311                   void (*emit_func)(struct si_context *ctx, struct r600_atom *state));
 312 void si_init_state_functions(struct si_context *sctx);
 313 void si_init_screen_state_functions(struct si_screen *sscreen);
 314 void
 315 si_make_buffer_descriptor(struct si_screen *screen, struct r600_resource *buf,
 316                           enum pipe_format format,
 317                           unsigned offset, unsigned size,
 318                           uint32_t *state);
 319 void
 320 si_make_texture_descriptor(struct si_screen *screen,
 321                            struct r600_texture *tex,
 322                            bool sampler,
 323                            enum pipe_texture_target target,
 324                            enum pipe_format pipe_format,
 325                            const unsigned char state_swizzle[4],
 326                            unsigned first_level, unsigned last_level,
 327                            unsigned first_layer, unsigned last_layer,
 328                            unsigned width, unsigned height, unsigned depth,
 329                            uint32_t *state,
 330                            uint32_t *fmask_state);
 331 struct pipe_sampler_view *
 332 si_create_sampler_view_custom(struct pipe_context *ctx,
 333                               struct pipe_resource *texture,
 334                               const struct pipe_sampler_view *state,
 335                               unsigned width0, unsigned height0,
 336                               unsigned force_level);
 337
 338 /* si_state_shader.c */
 339 bool si_update_shaders(struct si_context *sctx);
 340 void si_init_shader_functions(struct si_context *sctx);
 341 bool si_init_shader_cache(struct si_screen *sscreen);
 342 void si_destroy_shader_cache(struct si_screen *sscreen);
 343 void si_init_shader_selector_async(void *job, int thread_index);
 344
 345 /* si_state_draw.c */
 346 void si_emit_cache_flush(struct si_context *sctx, struct r600_atom *atom);
 347 void si_ce_pre_draw_synchronization(struct si_context *sctx);
 348 void si_ce_post_draw_synchronization(struct si_context *sctx);
 349 void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *dinfo);
 350 void si_trace_emit(struct si_context *sctx);
 351
 352
 353 static inline unsigned
 354 si_tile_mode_index(struct r600_texture *rtex, unsigned level, bool stencil)
 355 {
 356         if (stencil)
 357                 return rtex->surface.stencil_tiling_index[level];
 358         else
 359                 return rtex->surface.tiling_index[level];
 360 }
 361
 362 #endif