2 * Copyright 2012 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 * Christian König <christian.koenig@amd.com>
31 #include "radeon/r600_pipe_common.h"
33 #define SI_NUM_GRAPHICS_SHADERS (PIPE_SHADER_TESS_EVAL+1)
34 #define SI_NUM_SHADERS (PIPE_SHADER_COMPUTE+1)
36 #define SI_MAX_ATTRIBS 16
37 #define SI_NUM_VERTEX_BUFFERS SI_MAX_ATTRIBS
38 #define SI_NUM_SAMPLERS 32 /* OpenGL textures units per shader */
39 #define SI_NUM_CONST_BUFFERS 16
40 #define SI_NUM_IMAGES 16
41 #define SI_NUM_SHADER_BUFFERS 16
46 struct si_state_blend
{
47 struct si_pm4_state pm4
;
48 uint32_t cb_target_mask
;
49 bool alpha_to_coverage
;
52 /* Set 0xf or 0x0 (4 bits) per render target if the following is
53 * true. ANDed with spi_shader_col_format.
55 unsigned blend_enable_4bit
;
56 unsigned need_src_alpha_4bit
;
59 struct si_state_rasterizer
{
60 struct si_pm4_state pm4
;
61 /* poly offset states for 16-bit, 24-bit, and 32-bit zbuffers */
62 struct si_pm4_state pm4_poly_offset
[3];
65 bool multisample_enable
;
66 bool force_persample_interp
;
67 bool line_stipple_enable
;
68 unsigned sprite_coord_enable
;
69 unsigned pa_sc_line_stipple
;
70 unsigned pa_cl_clip_cntl
;
71 unsigned clip_plane_enable
;
72 bool poly_stipple_enable
;
75 bool uses_poly_offset
;
76 bool clamp_fragment_color
;
77 bool rasterizer_discard
;
82 struct si_dsa_stencil_ref_part
{
88 struct si_pm4_state pm4
;
90 struct si_dsa_stencil_ref_part stencil_ref
;
93 struct si_stencil_ref
{
94 struct r600_atom atom
;
95 struct pipe_stencil_ref state
;
96 struct si_dsa_stencil_ref_part dsa_part
;
99 struct si_vertex_element
102 unsigned first_vb_use_mask
;
103 /* Vertex buffer descriptor list size aligned for optimal prefetch. */
104 unsigned desc_list_byte_size
;
106 uint8_t fix_fetch
[SI_MAX_ATTRIBS
];
107 uint32_t rsrc_word3
[SI_MAX_ATTRIBS
];
108 uint32_t format_size
[SI_MAX_ATTRIBS
];
109 struct pipe_vertex_element elements
[SI_MAX_ATTRIBS
];
114 struct si_state_blend
*blend
;
115 struct si_state_rasterizer
*rasterizer
;
116 struct si_state_dsa
*dsa
;
117 struct si_pm4_state
*poly_offset
;
118 struct si_pm4_state
*ls
;
119 struct si_pm4_state
*hs
;
120 struct si_pm4_state
*es
;
121 struct si_pm4_state
*gs
;
122 struct si_pm4_state
*vgt_shader_config
;
123 struct si_pm4_state
*vs
;
124 struct si_pm4_state
*ps
;
126 struct si_pm4_state
*array
[0];
129 #define SI_NUM_STATES (sizeof(union si_state) / sizeof(struct si_pm4_state *))
131 union si_state_atoms
{
133 /* The order matters. */
134 struct r600_atom
*prefetch_L2
;
135 struct r600_atom
*render_cond
;
136 struct r600_atom
*streamout_begin
;
137 struct r600_atom
*streamout_enable
; /* must be after streamout_begin */
138 struct r600_atom
*framebuffer
;
139 struct r600_atom
*msaa_sample_locs
;
140 struct r600_atom
*db_render_state
;
141 struct r600_atom
*msaa_config
;
142 struct r600_atom
*sample_mask
;
143 struct r600_atom
*cb_render_state
;
144 struct r600_atom
*blend_color
;
145 struct r600_atom
*clip_regs
;
146 struct r600_atom
*clip_state
;
147 struct r600_atom
*shader_userdata
;
148 struct r600_atom
*scissors
;
149 struct r600_atom
*viewports
;
150 struct r600_atom
*stencil_ref
;
151 struct r600_atom
*spi_map
;
152 struct r600_atom
*scratch_state
;
154 struct r600_atom
*array
[0];
157 #define SI_NUM_ATOMS (sizeof(union si_state_atoms)/sizeof(struct r600_atom*))
159 struct si_shader_data
{
160 struct r600_atom atom
;
161 uint32_t sh_base
[SI_NUM_SHADERS
];
164 /* Private read-write buffer slots. */
166 SI_HS_RING_TESS_FACTOR
,
167 SI_HS_RING_TESS_OFFCHIP
,
174 SI_VS_STREAMOUT_BUF0
,
175 SI_VS_STREAMOUT_BUF1
,
176 SI_VS_STREAMOUT_BUF2
,
177 SI_VS_STREAMOUT_BUF3
,
179 SI_HS_CONST_DEFAULT_TESS_LEVELS
,
180 SI_VS_CONST_CLIP_PLANES
,
181 SI_PS_CONST_POLY_STIPPLE
,
182 SI_PS_CONST_SAMPLE_POSITIONS
,
187 /* Indices into sctx->descriptors, laid out so that gfx and compute pipelines
191 * 1 - vertex const buffers
192 * 2 - vertex shader buffers
194 * 5 - fragment const buffers
196 * 21 - compute const buffers
199 #define SI_SHADER_DESCS_CONST_BUFFERS 0
200 #define SI_SHADER_DESCS_SHADER_BUFFERS 1
201 #define SI_SHADER_DESCS_SAMPLERS 2
202 #define SI_SHADER_DESCS_IMAGES 3
203 #define SI_NUM_SHADER_DESCS 4
205 #define SI_DESCS_RW_BUFFERS 0
206 #define SI_DESCS_FIRST_SHADER 1
207 #define SI_DESCS_FIRST_COMPUTE (SI_DESCS_FIRST_SHADER + \
208 PIPE_SHADER_COMPUTE * SI_NUM_SHADER_DESCS)
209 #define SI_NUM_DESCS (SI_DESCS_FIRST_SHADER + \
210 SI_NUM_SHADERS * SI_NUM_SHADER_DESCS)
212 /* This represents descriptors in memory, such as buffer resources,
213 * image resources, and sampler states.
215 struct si_descriptors
{
216 /* The list of descriptors in malloc'd memory. */
218 /* The list in mapped GPU memory. */
220 /* The size of one descriptor. */
221 unsigned element_dw_size
;
222 /* The maximum number of descriptors. */
223 unsigned num_elements
;
225 /* The buffer where the descriptors have been uploaded. */
226 struct r600_resource
*buffer
;
227 unsigned buffer_offset
;
229 /* Offset in CE RAM */
232 /* elements of the list that are changed and need to be uploaded */
235 /* Whether CE is used to upload this descriptor array. */
237 /* Whether the CE ram is dirty and needs to be reinitialized entirely
238 * before we can do partial updates. */
241 /* The shader userdata offset within a shader where the 64-bit pointer to the descriptor
242 * array will be stored. */
243 unsigned shader_userdata_offset
;
246 struct si_sampler_views
{
247 struct pipe_sampler_view
*views
[SI_NUM_SAMPLERS
];
248 struct si_sampler_state
*sampler_states
[SI_NUM_SAMPLERS
];
250 /* The i-th bit is set if that element is enabled (non-NULL resource). */
251 unsigned enabled_mask
;
254 struct si_buffer_resources
{
255 enum radeon_bo_usage shader_usage
; /* READ, WRITE, or READWRITE */
256 enum radeon_bo_priority priority
;
257 struct pipe_resource
**buffers
; /* this has num_buffers elements */
259 /* The i-th bit is set if that element is enabled (non-NULL resource). */
260 unsigned enabled_mask
;
263 #define si_pm4_block_idx(member) \
264 (offsetof(union si_state, named.member) / sizeof(struct si_pm4_state *))
266 #define si_pm4_state_changed(sctx, member) \
267 ((sctx)->queued.named.member != (sctx)->emitted.named.member)
269 #define si_pm4_bind_state(sctx, member, value) \
271 (sctx)->queued.named.member = (value); \
272 (sctx)->dirty_states |= 1 << si_pm4_block_idx(member); \
275 #define si_pm4_delete_state(sctx, member, value) \
277 if ((sctx)->queued.named.member == (value)) { \
278 (sctx)->queued.named.member = NULL; \
280 si_pm4_free_state(sctx, (struct si_pm4_state *)(value), \
281 si_pm4_block_idx(member)); \
284 /* si_descriptors.c */
285 void si_ce_reinitialize_all_descriptors(struct si_context
*sctx
);
286 void si_ce_enable_loads(struct radeon_winsys_cs
*ib
);
287 void si_set_mutable_tex_desc_fields(struct si_screen
*sscreen
,
288 struct r600_texture
*tex
,
289 const struct legacy_surf_level
*base_level_info
,
290 unsigned base_level
, unsigned first_level
,
291 unsigned block_width
, bool is_stencil
,
293 void si_get_pipe_constant_buffer(struct si_context
*sctx
, uint shader
,
294 uint slot
, struct pipe_constant_buffer
*cbuf
);
295 void si_get_shader_buffers(struct si_context
*sctx
,
296 enum pipe_shader_type shader
,
297 uint start_slot
, uint count
,
298 struct pipe_shader_buffer
*sbuf
);
299 void si_set_ring_buffer(struct pipe_context
*ctx
, uint slot
,
300 struct pipe_resource
*buffer
,
301 unsigned stride
, unsigned num_records
,
302 bool add_tid
, bool swizzle
,
303 unsigned element_size
, unsigned index_stride
, uint64_t offset
);
304 void si_init_all_descriptors(struct si_context
*sctx
);
305 bool si_upload_vertex_buffer_descriptors(struct si_context
*sctx
);
306 bool si_upload_graphics_shader_descriptors(struct si_context
*sctx
);
307 bool si_upload_compute_shader_descriptors(struct si_context
*sctx
);
308 void si_release_all_descriptors(struct si_context
*sctx
);
309 void si_all_descriptors_begin_new_cs(struct si_context
*sctx
);
310 void si_upload_const_buffer(struct si_context
*sctx
, struct r600_resource
**rbuffer
,
311 const uint8_t *ptr
, unsigned size
, uint32_t *const_offset
);
312 void si_update_all_texture_descriptors(struct si_context
*sctx
);
313 void si_shader_change_notify(struct si_context
*sctx
);
314 void si_update_compressed_colortex_masks(struct si_context
*sctx
);
315 void si_emit_graphics_shader_userdata(struct si_context
*sctx
,
316 struct r600_atom
*atom
);
317 void si_emit_compute_shader_userdata(struct si_context
*sctx
);
318 void si_set_rw_buffer(struct si_context
*sctx
,
319 uint slot
, const struct pipe_constant_buffer
*input
);
321 struct si_shader_selector
;
323 void si_init_atom(struct si_context
*sctx
, struct r600_atom
*atom
,
324 struct r600_atom
**list_elem
,
325 void (*emit_func
)(struct si_context
*ctx
, struct r600_atom
*state
));
326 void si_init_state_functions(struct si_context
*sctx
);
327 void si_init_screen_state_functions(struct si_screen
*sscreen
);
329 si_make_buffer_descriptor(struct si_screen
*screen
, struct r600_resource
*buf
,
330 enum pipe_format format
,
331 unsigned offset
, unsigned size
,
334 si_make_texture_descriptor(struct si_screen
*screen
,
335 struct r600_texture
*tex
,
337 enum pipe_texture_target target
,
338 enum pipe_format pipe_format
,
339 const unsigned char state_swizzle
[4],
340 unsigned first_level
, unsigned last_level
,
341 unsigned first_layer
, unsigned last_layer
,
342 unsigned width
, unsigned height
, unsigned depth
,
344 uint32_t *fmask_state
);
345 struct pipe_sampler_view
*
346 si_create_sampler_view_custom(struct pipe_context
*ctx
,
347 struct pipe_resource
*texture
,
348 const struct pipe_sampler_view
*state
,
349 unsigned width0
, unsigned height0
,
350 unsigned force_level
);
352 /* si_state_shader.c */
353 bool si_update_shaders(struct si_context
*sctx
);
354 void si_init_shader_functions(struct si_context
*sctx
);
355 bool si_init_shader_cache(struct si_screen
*sscreen
);
356 void si_destroy_shader_cache(struct si_screen
*sscreen
);
357 void si_init_shader_selector_async(void *job
, int thread_index
);
359 /* si_state_draw.c */
360 void si_init_ia_multi_vgt_param_table(struct si_context
*sctx
);
361 void si_emit_cache_flush(struct si_context
*sctx
);
362 void si_ce_pre_draw_synchronization(struct si_context
*sctx
);
363 void si_ce_post_draw_synchronization(struct si_context
*sctx
);
364 void si_draw_vbo(struct pipe_context
*ctx
, const struct pipe_draw_info
*dinfo
);
365 void si_trace_emit(struct si_context
*sctx
);
368 static inline unsigned
369 si_tile_mode_index(struct r600_texture
*rtex
, unsigned level
, bool stencil
)
372 return rtex
->surface
.u
.legacy
.stencil_tiling_index
[level
];
374 return rtex
->surface
.u
.legacy
.tiling_index
[level
];