src/gallium/drivers/radeonsi/si_state.h

   1 /*
   2  * Copyright 2012 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Christian König <christian.koenig@amd.com>
  25  */
  26
  27 #ifndef SI_STATE_H
  28 #define SI_STATE_H
  29
  30 #include "si_pm4.h"
  31 #include "radeon/r600_pipe_common.h"
  32
  33 #define SI_NUM_GRAPHICS_SHADERS (PIPE_SHADER_TESS_EVAL+1)
  34 #define SI_NUM_SHADERS (PIPE_SHADER_COMPUTE+1)
  35 #define SI_MAX_ATTRIBS 16
  36
  37 struct si_screen;
  38 struct si_shader;
  39
  40 struct si_state_blend {
  41         struct si_pm4_state     pm4;
  42         uint32_t                cb_target_mask;
  43         bool                    alpha_to_coverage;
  44         bool                    alpha_to_one;
  45         bool                    dual_src_blend;
  46         /* Set 0xf or 0x0 (4 bits) per render target if the following is
  47          * true. ANDed with spi_shader_col_format.
  48          */
  49         unsigned                blend_enable_4bit;
  50         unsigned                need_src_alpha_4bit;
  51 };
  52
  53 struct si_state_rasterizer {
  54         struct si_pm4_state     pm4;
  55         /* poly offset states for 16-bit, 24-bit, and 32-bit zbuffers */
  56         struct si_pm4_state     pm4_poly_offset[3];
  57         bool                    flatshade;
  58         bool                    two_side;
  59         bool                    multisample_enable;
  60         bool                    force_persample_interp;
  61         bool                    line_stipple_enable;
  62         unsigned                sprite_coord_enable;
  63         unsigned                pa_sc_line_stipple;
  64         unsigned                pa_cl_clip_cntl;
  65         unsigned                clip_plane_enable;
  66         bool                    poly_stipple_enable;
  67         bool                    line_smooth;
  68         bool                    poly_smooth;
  69         bool                    uses_poly_offset;
  70         bool                    clamp_fragment_color;
  71         bool                    rasterizer_discard;
  72         bool                    scissor_enable;
  73 };
  74
  75 struct si_dsa_stencil_ref_part {
  76         uint8_t                 valuemask[2];
  77         uint8_t                 writemask[2];
  78 };
  79
  80 struct si_state_dsa {
  81         struct si_pm4_state             pm4;
  82         unsigned                        alpha_func;
  83         struct si_dsa_stencil_ref_part  stencil_ref;
  84 };
  85
  86 struct si_stencil_ref {
  87         struct r600_atom                atom;
  88         struct pipe_stencil_ref         state;
  89         struct si_dsa_stencil_ref_part  dsa_part;
  90 };
  91
  92 struct si_vertex_element
  93 {
  94         unsigned                        count;
  95         uint32_t                        rsrc_word3[SI_MAX_ATTRIBS];
  96         uint32_t                        format_size[SI_MAX_ATTRIBS];
  97         struct pipe_vertex_element      elements[SI_MAX_ATTRIBS];
  98 };
  99
 100 union si_state {
 101         struct {
 102                 struct si_state_blend           *blend;
 103                 struct si_state_rasterizer      *rasterizer;
 104                 struct si_state_dsa             *dsa;
 105                 struct si_pm4_state             *poly_offset;
 106                 struct si_pm4_state             *ls;
 107                 struct si_pm4_state             *hs;
 108                 struct si_pm4_state             *es;
 109                 struct si_pm4_state             *gs;
 110                 struct si_pm4_state             *vgt_shader_config;
 111                 struct si_pm4_state             *vs;
 112                 struct si_pm4_state             *ps;
 113         } named;
 114         struct si_pm4_state     *array[0];
 115 };
 116
 117 union si_state_atoms {
 118         struct {
 119                 /* The order matters. */
 120                 struct r600_atom *cache_flush;
 121                 struct r600_atom *render_cond;
 122                 struct r600_atom *streamout_begin;
 123                 struct r600_atom *streamout_enable; /* must be after streamout_begin */
 124                 struct r600_atom *framebuffer;
 125                 struct r600_atom *msaa_sample_locs;
 126                 struct r600_atom *db_render_state;
 127                 struct r600_atom *msaa_config;
 128                 struct r600_atom *sample_mask;
 129                 struct r600_atom *cb_render_state;
 130                 struct r600_atom *blend_color;
 131                 struct r600_atom *clip_regs;
 132                 struct r600_atom *clip_state;
 133                 struct r600_atom *shader_userdata;
 134                 struct r600_atom *scissors;
 135                 struct r600_atom *viewports;
 136                 struct r600_atom *stencil_ref;
 137                 struct r600_atom *spi_map;
 138         } s;
 139         struct r600_atom *array[0];
 140 };
 141
 142 #define SI_NUM_ATOMS (sizeof(union si_state_atoms)/sizeof(struct r600_atom*))
 143
 144 struct si_shader_data {
 145         struct r600_atom        atom;
 146         uint32_t                sh_base[SI_NUM_SHADERS];
 147 };
 148
 149 #define SI_NUM_USER_SAMPLERS            32 /* AKA OpenGL textures units per shader */
 150 #define SI_NUM_SAMPLERS                 SI_NUM_USER_SAMPLERS
 151
 152 /* User constant buffers:   0..15
 153  * Driver state constants:  16
 154  */
 155 #define SI_NUM_USER_CONST_BUFFERS       16
 156 #define SI_DRIVER_STATE_CONST_BUF       SI_NUM_USER_CONST_BUFFERS
 157 #define SI_NUM_CONST_BUFFERS            (SI_DRIVER_STATE_CONST_BUF + 1)
 158
 159 #define SI_NUM_IMAGES                   16
 160
 161 #define SI_NUM_SHADER_BUFFERS           16
 162
 163 /* Private read-write buffer slots. */
 164 enum {
 165         SI_HS_RING_TESS_FACTOR,
 166
 167         SI_ES_RING_ESGS,
 168         SI_GS_RING_ESGS,
 169
 170         SI_GS_RING_GSVS0,
 171         SI_GS_RING_GSVS1,
 172         SI_GS_RING_GSVS2,
 173         SI_GS_RING_GSVS3,
 174         SI_VS_RING_GSVS,
 175
 176         SI_VS_STREAMOUT_BUF0,
 177         SI_VS_STREAMOUT_BUF1,
 178         SI_VS_STREAMOUT_BUF2,
 179         SI_VS_STREAMOUT_BUF3,
 180
 181         SI_VS_CONST_CLIP_PLANES,
 182         SI_PS_CONST_POLY_STIPPLE,
 183
 184         SI_NUM_RW_BUFFERS,
 185 };
 186
 187 #define SI_NUM_VERTEX_BUFFERS   SI_MAX_ATTRIBS
 188
 189
 190 /* This represents descriptors in memory, such as buffer resources,
 191  * image resources, and sampler states.
 192  */
 193 struct si_descriptors {
 194         /* The list of descriptors in malloc'd memory. */
 195         uint32_t *list;
 196         /* The size of one descriptor. */
 197         unsigned element_dw_size;
 198         /* The maximum number of descriptors. */
 199         unsigned num_elements;
 200
 201         /* The buffer where the descriptors have been uploaded. */
 202         struct r600_resource *buffer;
 203         unsigned buffer_offset;
 204
 205         /* Offset in CE RAM */
 206         unsigned ce_offset;
 207
 208         /* The i-th bit is set if that element is enabled (non-NULL resource). */
 209         uint64_t enabled_mask;
 210
 211         /* elements of the list that are changed and need to be uploaded */
 212         uint64_t dirty_mask;
 213
 214         /* Whether the CE ram is dirty and needs to be reinitialized entirely
 215          * before we can do partial updates. */
 216         bool ce_ram_dirty;
 217
 218         /* The shader userdata offset within a shader where the 64-bit pointer to the descriptor
 219          * array will be stored. */
 220         unsigned shader_userdata_offset;
 221         /* Whether the pointer should be re-emitted. */
 222         bool pointer_dirty;
 223 };
 224
 225 struct si_sampler_views {
 226         struct si_descriptors           desc;
 227         struct pipe_sampler_view        *views[SI_NUM_SAMPLERS];
 228         void                            *sampler_states[SI_NUM_SAMPLERS];
 229 };
 230
 231 struct si_buffer_resources {
 232         struct si_descriptors           desc;
 233         enum radeon_bo_usage            shader_usage; /* READ, WRITE, or READWRITE */
 234         enum radeon_bo_priority         priority;
 235         struct pipe_resource            **buffers; /* this has num_buffers elements */
 236 };
 237
 238 #define si_pm4_block_idx(member) \
 239         (offsetof(union si_state, named.member) / sizeof(struct si_pm4_state *))
 240
 241 #define si_pm4_state_changed(sctx, member) \
 242         ((sctx)->queued.named.member != (sctx)->emitted.named.member)
 243
 244 #define si_pm4_bind_state(sctx, member, value) \
 245         do { \
 246                 (sctx)->queued.named.member = (value); \
 247         } while(0)
 248
 249 #define si_pm4_delete_state(sctx, member, value) \
 250         do { \
 251                 if ((sctx)->queued.named.member == (value)) { \
 252                         (sctx)->queued.named.member = NULL; \
 253                 } \
 254                 si_pm4_free_state(sctx, (struct si_pm4_state *)(value), \
 255                                   si_pm4_block_idx(member)); \
 256         } while(0)
 257
 258 /* si_descriptors.c */
 259 void si_ce_enable_loads(struct radeon_winsys_cs *ib);
 260 void si_set_ring_buffer(struct pipe_context *ctx, uint shader, uint slot,
 261                         struct pipe_resource *buffer,
 262                         unsigned stride, unsigned num_records,
 263                         bool add_tid, bool swizzle,
 264                         unsigned element_size, unsigned index_stride, uint64_t offset);
 265 void si_init_all_descriptors(struct si_context *sctx);
 266 bool si_upload_graphics_shader_descriptors(struct si_context *sctx);
 267 bool si_upload_compute_shader_descriptors(struct si_context *sctx);
 268 void si_release_all_descriptors(struct si_context *sctx);
 269 void si_all_descriptors_begin_new_cs(struct si_context *sctx);
 270 void si_upload_const_buffer(struct si_context *sctx, struct r600_resource **rbuffer,
 271                             const uint8_t *ptr, unsigned size, uint32_t *const_offset);
 272 void si_shader_change_notify(struct si_context *sctx);
 273 void si_update_compressed_colortex_masks(struct si_context *sctx);
 274 void si_emit_graphics_shader_userdata(struct si_context *sctx,
 275                                       struct r600_atom *atom);
 276 void si_emit_compute_shader_userdata(struct si_context *sctx);
 277 void si_set_constant_buffer(struct si_context *sctx,
 278                             struct si_buffer_resources *buffers,
 279                             uint slot, struct pipe_constant_buffer *input);
 280
 281 /* si_state.c */
 282 struct si_shader_selector;
 283
 284 void si_init_atom(struct si_context *sctx, struct r600_atom *atom,
 285                   struct r600_atom **list_elem,
 286                   void (*emit_func)(struct si_context *ctx, struct r600_atom *state));
 287 boolean si_is_format_supported(struct pipe_screen *screen,
 288                                enum pipe_format format,
 289                                enum pipe_texture_target target,
 290                                unsigned sample_count,
 291                                unsigned usage);
 292 void si_init_state_functions(struct si_context *sctx);
 293 void si_init_screen_state_functions(struct si_screen *sscreen);
 294 unsigned cik_bank_wh(unsigned bankwh);
 295 unsigned cik_db_pipe_config(struct si_screen *sscreen, unsigned tile_mode);
 296 unsigned cik_macro_tile_aspect(unsigned macro_tile_aspect);
 297 unsigned cik_tile_split(unsigned tile_split);
 298 unsigned si_array_mode(unsigned mode);
 299 uint32_t si_num_banks(struct si_screen *sscreen, struct r600_texture *tex);
 300 unsigned si_tile_mode_index(struct r600_texture *rtex, unsigned level, bool stencil);
 301 void
 302 si_make_buffer_descriptor(struct si_screen *screen, struct r600_resource *buf,
 303                           enum pipe_format format,
 304                           unsigned first_element, unsigned last_element,
 305                           uint32_t *state);
 306 void
 307 si_make_texture_descriptor(struct si_screen *screen,
 308                            struct r600_texture *tex,
 309                            bool sampler,
 310                            enum pipe_texture_target target,
 311                            enum pipe_format pipe_format,
 312                            const unsigned char state_swizzle[4],
 313                            unsigned base_level, unsigned first_level, unsigned last_level,
 314                            unsigned first_layer, unsigned last_layer,
 315                            unsigned width, unsigned height, unsigned depth,
 316                            uint32_t *state,
 317                            uint32_t *fmask_state);
 318 struct pipe_sampler_view *
 319 si_create_sampler_view_custom(struct pipe_context *ctx,
 320                               struct pipe_resource *texture,
 321                               const struct pipe_sampler_view *state,
 322                               unsigned width0, unsigned height0,
 323                               unsigned force_level);
 324
 325 /* si_state_shader.c */
 326 bool si_update_shaders(struct si_context *sctx);
 327 void si_init_shader_functions(struct si_context *sctx);
 328 bool si_init_shader_cache(struct si_screen *sscreen);
 329 void si_destroy_shader_cache(struct si_screen *sscreen);
 330
 331 /* si_state_draw.c */
 332 void si_emit_cache_flush(struct si_context *sctx, struct r600_atom *atom);
 333 void si_ce_pre_draw_synchronization(struct si_context *sctx);
 334 void si_ce_post_draw_synchronization(struct si_context *sctx);
 335 void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *dinfo);
 336 void si_trace_emit(struct si_context *sctx);
 337
 338 #endif