src/gallium/drivers/radeonsi/si_state.h

   1 /*
   2  * Copyright 2012 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Christian König <christian.koenig@amd.com>
  25  */
  26
  27 #ifndef SI_STATE_H
  28 #define SI_STATE_H
  29
  30 #include "si_pm4.h"
  31 #include "radeon/r600_pipe_common.h"
  32
  33 #define SI_NUM_SHADERS (PIPE_SHADER_TESS_EVAL+1)
  34
  35 struct si_screen;
  36 struct si_shader;
  37
  38 struct si_state_blend {
  39         struct si_pm4_state     pm4;
  40         uint32_t                cb_target_mask;
  41         bool                    alpha_to_one;
  42 };
  43
  44 struct si_state_sample_mask {
  45         struct si_pm4_state     pm4;
  46         uint16_t                sample_mask;
  47 };
  48
  49 struct si_state_scissor {
  50         struct si_pm4_state             pm4;
  51         struct pipe_scissor_state       scissor;
  52 };
  53
  54 struct si_state_viewport {
  55         struct si_pm4_state             pm4;
  56         struct pipe_viewport_state      viewport;
  57 };
  58
  59 struct si_state_rasterizer {
  60         struct si_pm4_state     pm4;
  61         bool                    flatshade;
  62         bool                    two_side;
  63         bool                    multisample_enable;
  64         bool                    line_stipple_enable;
  65         unsigned                sprite_coord_enable;
  66         unsigned                pa_sc_line_stipple;
  67         unsigned                pa_cl_clip_cntl;
  68         unsigned                clip_plane_enable;
  69         float                   offset_units;
  70         float                   offset_scale;
  71         bool                    poly_stipple_enable;
  72         bool                    line_smooth;
  73         bool                    poly_smooth;
  74 };
  75
  76 struct si_state_dsa {
  77         struct si_pm4_state     pm4;
  78         unsigned                alpha_func;
  79         uint8_t                 valuemask[2];
  80         uint8_t                 writemask[2];
  81 };
  82
  83 struct si_vertex_element
  84 {
  85         unsigned                        count;
  86         uint32_t                        rsrc_word3[PIPE_MAX_ATTRIBS];
  87         uint32_t                        format_size[PIPE_MAX_ATTRIBS];
  88         struct pipe_vertex_element      elements[PIPE_MAX_ATTRIBS];
  89 };
  90
  91 union si_state {
  92         struct {
  93                 struct si_state_blend           *blend;
  94                 struct si_pm4_state             *blend_color;
  95                 struct si_pm4_state             *clip;
  96                 struct si_state_sample_mask     *sample_mask;
  97                 struct si_state_scissor         *scissor[16];
  98                 struct si_state_viewport        *viewport[16];
  99                 struct si_state_rasterizer      *rasterizer;
 100                 struct si_state_dsa             *dsa;
 101                 struct si_pm4_state             *fb_rs;
 102                 struct si_pm4_state             *fb_blend;
 103                 struct si_pm4_state             *dsa_stencil_ref;
 104                 struct si_pm4_state             *ta_bordercolor_base;
 105                 struct si_pm4_state             *ls;
 106                 struct si_pm4_state             *hs;
 107                 struct si_pm4_state             *es;
 108                 struct si_pm4_state             *gs;
 109                 struct si_pm4_state             *gs_rings;
 110                 struct si_pm4_state             *tf_ring;
 111                 struct si_pm4_state             *vgt_shader_config;
 112                 struct si_pm4_state             *vs;
 113                 struct si_pm4_state             *ps;
 114                 struct si_pm4_state             *spi;
 115         } named;
 116         struct si_pm4_state     *array[0];
 117 };
 118
 119 struct si_shader_data {
 120         struct r600_atom        atom;
 121         uint32_t                sh_base[SI_NUM_SHADERS];
 122 };
 123
 124 #define SI_NUM_USER_SAMPLERS            16 /* AKA OpenGL textures units per shader */
 125 #define SI_POLY_STIPPLE_SAMPLER         SI_NUM_USER_SAMPLERS
 126 #define SI_NUM_SAMPLERS                 (SI_POLY_STIPPLE_SAMPLER + 1)
 127
 128 /* User sampler views:   0..15
 129  * Polygon stipple tex:  16
 130  * FMASK sampler views:  17..33 (no sampler states)
 131  */
 132 #define SI_FMASK_TEX_OFFSET             SI_NUM_SAMPLERS
 133 #define SI_NUM_SAMPLER_VIEWS            (SI_FMASK_TEX_OFFSET + SI_NUM_SAMPLERS)
 134 #define SI_NUM_SAMPLER_STATES           SI_NUM_SAMPLERS
 135
 136 /* User constant buffers:   0..15
 137  * Driver state constants:  16
 138  */
 139 #define SI_NUM_USER_CONST_BUFFERS       16
 140 #define SI_DRIVER_STATE_CONST_BUF       SI_NUM_USER_CONST_BUFFERS
 141 #define SI_NUM_CONST_BUFFERS            (SI_DRIVER_STATE_CONST_BUF + 1)
 142
 143 /* Read-write buffer slots.
 144  *
 145  * Ring buffers:        0..1
 146  * Streamout buffers:   2..5
 147  */
 148 #define SI_RING_TESS_FACTOR     0 /* for HS (TCS)  */
 149 #define SI_RING_ESGS            0 /* for ES, GS */
 150 #define SI_RING_GSVS            1 /* for GS, VS */
 151 #define SI_NUM_RING_BUFFERS     2
 152 #define SI_SO_BUF_OFFSET        SI_NUM_RING_BUFFERS
 153 #define SI_NUM_RW_BUFFERS       (SI_SO_BUF_OFFSET + 4)
 154
 155 #define SI_NUM_VERTEX_BUFFERS   16
 156
 157
 158 /* This represents resource descriptors in memory, such as buffer resources,
 159  * image resources, and sampler states.
 160  */
 161 struct si_descriptors {
 162         struct r600_atom atom;
 163
 164         /* The size of one resource descriptor. */
 165         unsigned element_dw_size;
 166         /* The maximum number of resource descriptors. */
 167         unsigned num_elements;
 168
 169         /* The buffer where resource descriptors are stored. */
 170         struct r600_resource *buffer;
 171         unsigned buffer_offset;
 172
 173         /* The i-th bit is set if that element is dirty (changed but not emitted). */
 174         uint64_t dirty_mask;
 175         /* The i-th bit is set if that element is enabled (non-NULL resource). */
 176         uint64_t enabled_mask;
 177
 178         /* We can't update descriptors directly because the GPU might be
 179          * reading them at the same time, so we have to update them
 180          * in a copy-on-write manner. Each such copy is called a context,
 181          * which is just another array descriptors in the same buffer. */
 182         unsigned current_context_id;
 183         /* The size of a context, should be equal to 4*element_dw_size*num_elements. */
 184         unsigned context_size;
 185
 186         /* The shader userdata offset within a shader where the 64-bit pointer to the descriptor
 187          * array will be stored. */
 188         unsigned shader_userdata_offset;
 189         bool pointer_dirty;
 190 };
 191
 192 struct si_sampler_views {
 193         struct si_descriptors           desc;
 194         struct pipe_sampler_view        *views[SI_NUM_SAMPLER_VIEWS];
 195         uint32_t                        *desc_data[SI_NUM_SAMPLER_VIEWS];
 196 };
 197
 198 struct si_sampler_states {
 199         struct si_descriptors           desc;
 200         uint32_t                        *desc_data[SI_NUM_SAMPLER_STATES];
 201         void                            *saved_states[2]; /* saved for u_blitter */
 202 };
 203
 204 struct si_buffer_resources {
 205         struct si_descriptors           desc;
 206         unsigned                        num_buffers;
 207         enum radeon_bo_usage            shader_usage; /* READ, WRITE, or READWRITE */
 208         enum radeon_bo_priority         priority;
 209         struct pipe_resource            **buffers; /* this has num_buffers elements */
 210         uint32_t                        *desc_storage; /* this has num_buffers*4 elements */
 211         uint32_t                        **desc_data; /* an array of pointers pointing to desc_storage */
 212 };
 213
 214 #define si_pm4_block_idx(member) \
 215         (offsetof(union si_state, named.member) / sizeof(struct si_pm4_state *))
 216
 217 #define si_pm4_state_changed(sctx, member) \
 218         ((sctx)->queued.named.member != (sctx)->emitted.named.member)
 219
 220 #define si_pm4_bind_state(sctx, member, value) \
 221         do { \
 222                 (sctx)->queued.named.member = (value); \
 223         } while(0)
 224
 225 #define si_pm4_delete_state(sctx, member, value) \
 226         do { \
 227                 if ((sctx)->queued.named.member == (value)) { \
 228                         (sctx)->queued.named.member = NULL; \
 229                 } \
 230                 si_pm4_free_state(sctx, (struct si_pm4_state *)(value), \
 231                                   si_pm4_block_idx(member)); \
 232         } while(0)
 233
 234 #define si_pm4_set_state(sctx, member, value) \
 235         do { \
 236                 if ((sctx)->queued.named.member != (value)) { \
 237                         si_pm4_free_state(sctx, \
 238                                 (struct si_pm4_state *)(sctx)->queued.named.member, \
 239                                 si_pm4_block_idx(member)); \
 240                         (sctx)->queued.named.member = (value); \
 241                 } \
 242         } while(0)
 243
 244 /* si_descriptors.c */
 245 void si_set_sampler_descriptors(struct si_context *sctx, unsigned shader,
 246                                 unsigned start, unsigned count, void **states);
 247 void si_update_vertex_buffers(struct si_context *sctx);
 248 void si_set_ring_buffer(struct pipe_context *ctx, uint shader, uint slot,
 249                         struct pipe_resource *buffer,
 250                         unsigned stride, unsigned num_records,
 251                         bool add_tid, bool swizzle,
 252                         unsigned element_size, unsigned index_stride);
 253 void si_init_all_descriptors(struct si_context *sctx);
 254 void si_release_all_descriptors(struct si_context *sctx);
 255 void si_all_descriptors_begin_new_cs(struct si_context *sctx);
 256 void si_copy_buffer(struct si_context *sctx,
 257                     struct pipe_resource *dst, struct pipe_resource *src,
 258                     uint64_t dst_offset, uint64_t src_offset, unsigned size, bool is_framebuffer);
 259 void si_upload_const_buffer(struct si_context *sctx, struct r600_resource **rbuffer,
 260                             const uint8_t *ptr, unsigned size, uint32_t *const_offset);
 261 void si_shader_change_notify(struct si_context *sctx);
 262
 263 /* si_state.c */
 264 struct si_shader_selector;
 265
 266 boolean si_is_format_supported(struct pipe_screen *screen,
 267                                enum pipe_format format,
 268                                enum pipe_texture_target target,
 269                                unsigned sample_count,
 270                                unsigned usage);
 271 void si_init_state_functions(struct si_context *sctx);
 272 unsigned cik_bank_wh(unsigned bankwh);
 273 unsigned cik_db_pipe_config(struct si_screen *sscreen, unsigned tile_mode);
 274 unsigned cik_macro_tile_aspect(unsigned macro_tile_aspect);
 275 unsigned cik_tile_split(unsigned tile_split);
 276 unsigned si_array_mode(unsigned mode);
 277 uint32_t si_num_banks(struct si_screen *sscreen, struct r600_texture *tex);
 278 unsigned si_tile_mode_index(struct r600_texture *rtex, unsigned level, bool stencil);
 279 struct pipe_sampler_view *
 280 si_create_sampler_view_custom(struct pipe_context *ctx,
 281                               struct pipe_resource *texture,
 282                               const struct pipe_sampler_view *state,
 283                               unsigned width0, unsigned height0,
 284                               unsigned force_level);
 285
 286 /* si_state_shader.c */
 287 void si_update_shaders(struct si_context *sctx);
 288 void si_init_shader_functions(struct si_context *sctx);
 289
 290 /* si_state_draw.c */
 291 extern const struct r600_atom si_atom_cache_flush;
 292 extern const struct r600_atom si_atom_msaa_sample_locs;
 293 extern const struct r600_atom si_atom_msaa_config;
 294 void si_emit_cache_flush(struct r600_common_context *sctx, struct r600_atom *atom);
 295 void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *dinfo);
 296
 297 /* si_commands.c */
 298 void si_cmd_context_control(struct si_pm4_state *pm4);
 299
 300 #endif