src/gallium/drivers/radeonsi/si_state.h

   1 /*
   2  * Copyright 2012 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Christian König <christian.koenig@amd.com>
  25  */
  26
  27 #ifndef SI_STATE_H
  28 #define SI_STATE_H
  29
  30 #include "si_pm4.h"
  31 #include "radeon/r600_pipe_common.h"
  32
  33 struct si_screen;
  34
  35 struct si_state_blend {
  36         struct si_pm4_state     pm4;
  37         uint32_t                cb_target_mask;
  38         bool                    alpha_to_one;
  39 };
  40
  41 struct si_state_sample_mask {
  42         struct si_pm4_state     pm4;
  43         uint16_t                sample_mask;
  44 };
  45
  46 struct si_state_scissor {
  47         struct si_pm4_state             pm4;
  48         struct pipe_scissor_state       scissor;
  49 };
  50
  51 struct si_state_viewport {
  52         struct si_pm4_state             pm4;
  53         struct pipe_viewport_state      viewport;
  54 };
  55
  56 struct si_state_rasterizer {
  57         struct si_pm4_state     pm4;
  58         bool                    flatshade;
  59         bool                    two_side;
  60         bool                    multisample_enable;
  61         bool                    line_stipple_enable;
  62         unsigned                sprite_coord_enable;
  63         unsigned                pa_sc_line_stipple;
  64         unsigned                pa_su_sc_mode_cntl;
  65         unsigned                pa_cl_clip_cntl;
  66         unsigned                pa_cl_vs_out_cntl;
  67         unsigned                clip_plane_enable;
  68         float                   offset_units;
  69         float                   offset_scale;
  70 };
  71
  72 struct si_state_dsa {
  73         struct si_pm4_state     pm4;
  74         float                   alpha_ref;
  75         unsigned                alpha_func;
  76         unsigned                db_render_control;
  77         uint8_t                 valuemask[2];
  78         uint8_t                 writemask[2];
  79 };
  80
  81 struct si_vertex_element
  82 {
  83         unsigned                        count;
  84         uint32_t                        rsrc_word3[PIPE_MAX_ATTRIBS];
  85         uint32_t                        format_size[PIPE_MAX_ATTRIBS];
  86         struct pipe_vertex_element      elements[PIPE_MAX_ATTRIBS];
  87 };
  88
  89 union si_state {
  90         struct {
  91                 struct si_pm4_state             *init;
  92                 struct si_state_blend           *blend;
  93                 struct si_pm4_state             *blend_color;
  94                 struct si_pm4_state             *clip;
  95                 struct si_state_sample_mask     *sample_mask;
  96                 struct si_state_scissor         *scissor;
  97                 struct si_state_viewport        *viewport;
  98                 struct si_state_rasterizer      *rasterizer;
  99                 struct si_state_dsa             *dsa;
 100                 struct si_pm4_state             *fb_rs;
 101                 struct si_pm4_state             *fb_blend;
 102                 struct si_pm4_state             *dsa_stencil_ref;
 103                 struct si_pm4_state             *ta_bordercolor_base;
 104                 struct si_pm4_state             *es;
 105                 struct si_pm4_state             *gs;
 106                 struct si_pm4_state             *gs_rings;
 107                 struct si_pm4_state             *gs_onoff;
 108                 struct si_pm4_state             *vs;
 109                 struct si_pm4_state             *ps;
 110                 struct si_pm4_state             *spi;
 111                 struct si_pm4_state             *draw_info;
 112                 struct si_pm4_state             *draw;
 113         } named;
 114         struct si_pm4_state     *array[0];
 115 };
 116
 117 #define SI_NUM_USER_SAMPLERS 16 /* AKA OpenGL textures units per shader */
 118
 119 /* User sampler views:   0..15
 120  * FMASK sampler views: 16..31 (no sampler states)
 121  */
 122 #define SI_FMASK_TEX_OFFSET             SI_NUM_USER_SAMPLERS
 123 #define SI_NUM_SAMPLER_VIEWS            (SI_FMASK_TEX_OFFSET + SI_NUM_USER_SAMPLERS)
 124 #define SI_NUM_SAMPLER_STATES           SI_NUM_USER_SAMPLERS
 125
 126 /* User constant buffers:   0..15
 127  * Driver state constants:  16
 128  */
 129 #define SI_NUM_USER_CONST_BUFFERS       16
 130 #define SI_DRIVER_STATE_CONST_BUF       SI_NUM_USER_CONST_BUFFERS
 131 #define SI_NUM_CONST_BUFFERS            (SI_DRIVER_STATE_CONST_BUF + 1)
 132
 133 /* Read-write buffer slots.
 134  *
 135  * Ring buffers:        0..1
 136  * Streamout buffers:   2..5
 137  */
 138 #define SI_RING_ESGS            0
 139 #define SI_RING_GSVS            1
 140 #define SI_NUM_RING_BUFFERS     2
 141 #define SI_SO_BUF_OFFSET        SI_NUM_RING_BUFFERS
 142 #define SI_NUM_RW_BUFFERS       (SI_SO_BUF_OFFSET + 4)
 143
 144 #define SI_NUM_VERTEX_BUFFERS   16
 145
 146
 147 /* This represents resource descriptors in memory, such as buffer resources,
 148  * image resources, and sampler states.
 149  */
 150 struct si_descriptors {
 151         struct r600_atom atom;
 152
 153         /* The size of one resource descriptor. */
 154         unsigned element_dw_size;
 155         /* The maximum number of resource descriptors. */
 156         unsigned num_elements;
 157
 158         /* The buffer where resource descriptors are stored. */
 159         struct r600_resource *buffer;
 160         unsigned buffer_offset;
 161
 162         /* The i-th bit is set if that element is dirty (changed but not emitted). */
 163         unsigned dirty_mask;
 164         /* The i-th bit is set if that element is enabled (non-NULL resource). */
 165         unsigned enabled_mask;
 166
 167         /* We can't update descriptors directly because the GPU might be
 168          * reading them at the same time, so we have to update them
 169          * in a copy-on-write manner. Each such copy is called a context,
 170          * which is just another array descriptors in the same buffer. */
 171         unsigned current_context_id;
 172         /* The size of a context, should be equal to 4*element_dw_size*num_elements. */
 173         unsigned context_size;
 174
 175         /* The shader userdata register where the 64-bit pointer to the descriptor
 176          * array will be stored. */
 177         unsigned shader_userdata_reg;
 178 };
 179
 180 struct si_sampler_views {
 181         struct si_descriptors           desc;
 182         struct pipe_sampler_view        *views[SI_NUM_SAMPLER_VIEWS];
 183         uint32_t                        *desc_data[SI_NUM_SAMPLER_VIEWS];
 184 };
 185
 186 struct si_sampler_states {
 187         struct si_descriptors           desc;
 188         uint32_t                        *desc_data[SI_NUM_SAMPLER_STATES];
 189         void                            *saved_states[2]; /* saved for u_blitter */
 190 };
 191
 192 struct si_buffer_resources {
 193         struct si_descriptors           desc;
 194         unsigned                        num_buffers;
 195         enum radeon_bo_usage            shader_usage; /* READ, WRITE, or READWRITE */
 196         enum radeon_bo_priority         priority;
 197         struct pipe_resource            **buffers; /* this has num_buffers elements */
 198         uint32_t                        *desc_storage; /* this has num_buffers*4 elements */
 199         uint32_t                        **desc_data; /* an array of pointers pointing to desc_storage */
 200 };
 201
 202 #define si_pm4_block_idx(member) \
 203         (offsetof(union si_state, named.member) / sizeof(struct si_pm4_state *))
 204
 205 #define si_pm4_state_changed(sctx, member) \
 206         ((sctx)->queued.named.member != (sctx)->emitted.named.member)
 207
 208 #define si_pm4_bind_state(sctx, member, value) \
 209         do { \
 210                 (sctx)->queued.named.member = (value); \
 211         } while(0)
 212
 213 #define si_pm4_delete_state(sctx, member, value) \
 214         do { \
 215                 if ((sctx)->queued.named.member == (value)) { \
 216                         (sctx)->queued.named.member = NULL; \
 217                 } \
 218                 si_pm4_free_state(sctx, (struct si_pm4_state *)(value), \
 219                                   si_pm4_block_idx(member)); \
 220         } while(0)
 221
 222 #define si_pm4_set_state(sctx, member, value) \
 223         do { \
 224                 if ((sctx)->queued.named.member != (value)) { \
 225                         si_pm4_free_state(sctx, \
 226                                 (struct si_pm4_state *)(sctx)->queued.named.member, \
 227                                 si_pm4_block_idx(member)); \
 228                         (sctx)->queued.named.member = (value); \
 229                 } \
 230         } while(0)
 231
 232 /* si_descriptors.c */
 233 void si_set_sampler_descriptors(struct si_context *sctx, unsigned shader,
 234                                 unsigned start, unsigned count, void **states);
 235 void si_update_vertex_buffers(struct si_context *sctx);
 236 void si_set_ring_buffer(struct pipe_context *ctx, uint shader, uint slot,
 237                         struct pipe_resource *buffer,
 238                         unsigned stride, unsigned num_records,
 239                         bool add_tid, bool swizzle,
 240                         unsigned element_size, unsigned index_stride);
 241 void si_init_all_descriptors(struct si_context *sctx);
 242 void si_release_all_descriptors(struct si_context *sctx);
 243 void si_all_descriptors_begin_new_cs(struct si_context *sctx);
 244 void si_copy_buffer(struct si_context *sctx,
 245                     struct pipe_resource *dst, struct pipe_resource *src,
 246                     uint64_t dst_offset, uint64_t src_offset, unsigned size);
 247 void si_upload_const_buffer(struct si_context *sctx, struct r600_resource **rbuffer,
 248                             const uint8_t *ptr, unsigned size, uint32_t *const_offset);
 249
 250 /* si_state.c */
 251 struct si_shader_selector;
 252
 253 boolean si_is_format_supported(struct pipe_screen *screen,
 254                                enum pipe_format format,
 255                                enum pipe_texture_target target,
 256                                unsigned sample_count,
 257                                unsigned usage);
 258 int si_shader_select(struct pipe_context *ctx,
 259                      struct si_shader_selector *sel);
 260 void si_make_dummy_ps(struct si_context *sctx);
 261 void si_init_state_functions(struct si_context *sctx);
 262 void si_init_config(struct si_context *sctx);
 263 unsigned cik_bank_wh(unsigned bankwh);
 264 unsigned cik_db_pipe_config(struct si_screen *sscreen, unsigned tile_mode);
 265 unsigned cik_macro_tile_aspect(unsigned macro_tile_aspect);
 266 unsigned cik_tile_split(unsigned tile_split);
 267 uint32_t si_num_banks(struct si_screen *sscreen, struct r600_texture *tex);
 268 unsigned si_tile_mode_index(struct r600_texture *rtex, unsigned level, bool stencil);
 269
 270 /* si_state_draw.c */
 271 extern const struct r600_atom si_atom_cache_flush;
 272 extern const struct r600_atom si_atom_msaa_config;
 273 void si_emit_cache_flush(struct r600_common_context *sctx, struct r600_atom *atom);
 274 void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *dinfo);
 275
 276 /* si_commands.c */
 277 void si_cmd_context_control(struct si_pm4_state *pm4);
 278 void si_cmd_draw_index_2(struct si_pm4_state *pm4, uint32_t max_size,
 279                          uint64_t index_base, uint32_t index_count,
 280                          uint32_t initiator, bool predicate);
 281 void si_cmd_draw_index_auto(struct si_pm4_state *pm4, uint32_t count,
 282                             uint32_t initiator, bool predicate);
 283 void si_cmd_draw_indirect(struct si_pm4_state *pm4, uint64_t indirect_va,
 284                           uint32_t indirect_offset, uint32_t base_vtx_loc,
 285                           uint32_t start_inst_loc, bool predicate);
 286 void si_cmd_draw_index_indirect(struct si_pm4_state *pm4, uint64_t indirect_va,
 287                                 uint64_t index_va, uint32_t index_max_size,
 288                                 uint32_t indirect_offset, uint32_t base_vtx_loc,
 289                                 uint32_t start_inst_loc, bool predicate);
 290
 291 #endif