src/gallium/drivers/radeonsi/si_state.h

   1 /*
   2  * Copyright 2012 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Christian König <christian.koenig@amd.com>
  25  */
  26
  27 #ifndef SI_STATE_H
  28 #define SI_STATE_H
  29
  30 #include "radeonsi_pm4.h"
  31
  32 /* This encapsulates a state or an operation which can emitted into the GPU
  33  * command stream. */
  34 struct si_atom {
  35         void (*emit)(struct r600_context *ctx, struct si_atom *state);
  36         unsigned                num_dw;
  37         bool                    dirty;
  38 };
  39
  40 struct si_state_blend {
  41         struct si_pm4_state     pm4;
  42         uint32_t                cb_target_mask;
  43         uint32_t                cb_color_control;
  44 };
  45
  46 struct si_state_viewport {
  47         struct si_pm4_state             pm4;
  48         struct pipe_viewport_state      viewport;
  49 };
  50
  51 struct si_state_rasterizer {
  52         struct si_pm4_state     pm4;
  53         bool                    flatshade;
  54         bool                    two_side;
  55         unsigned                sprite_coord_enable;
  56         unsigned                pa_sc_line_stipple;
  57         unsigned                pa_su_sc_mode_cntl;
  58         unsigned                pa_cl_clip_cntl;
  59         unsigned                pa_cl_vs_out_cntl;
  60         unsigned                clip_plane_enable;
  61         float                   offset_units;
  62         float                   offset_scale;
  63 };
  64
  65 struct si_state_dsa {
  66         struct si_pm4_state     pm4;
  67         float                   alpha_ref;
  68         unsigned                alpha_func;
  69         unsigned                db_render_override;
  70         unsigned                db_render_control;
  71         uint8_t                 valuemask[2];
  72         uint8_t                 writemask[2];
  73 };
  74
  75 struct si_vertex_element
  76 {
  77         unsigned                        count;
  78         uint32_t                        rsrc_word3[PIPE_MAX_ATTRIBS];
  79         struct pipe_vertex_element      elements[PIPE_MAX_ATTRIBS];
  80 };
  81
  82 union si_state {
  83         struct {
  84                 struct si_pm4_state             *sync;
  85                 struct si_pm4_state             *init;
  86                 struct si_state_blend           *blend;
  87                 struct si_pm4_state             *blend_color;
  88                 struct si_pm4_state             *clip;
  89                 struct si_pm4_state             *scissor;
  90                 struct si_state_viewport        *viewport;
  91                 struct si_pm4_state             *framebuffer;
  92                 struct si_state_rasterizer      *rasterizer;
  93                 struct si_state_dsa             *dsa;
  94                 struct si_pm4_state             *fb_rs;
  95                 struct si_pm4_state             *fb_blend;
  96                 struct si_pm4_state             *dsa_stencil_ref;
  97                 struct si_pm4_state             *vs;
  98                 struct si_pm4_state             *vs_sampler_views;
  99                 struct si_pm4_state             *vs_sampler;
 100                 struct si_pm4_state             *vs_const;
 101                 struct si_pm4_state             *ps;
 102                 struct si_pm4_state             *ps_sampler_views;
 103                 struct si_pm4_state             *ps_sampler;
 104                 struct si_pm4_state             *ps_const;
 105                 struct si_pm4_state             *spi;
 106                 struct si_pm4_state             *vertex_buffers;
 107                 struct si_pm4_state             *texture_barrier;
 108                 struct si_pm4_state             *draw_info;
 109                 struct si_pm4_state             *draw;
 110         } named;
 111         struct si_pm4_state     *array[0];
 112 };
 113
 114 #define NUM_TEX_UNITS 16
 115
 116 /* This represents resource descriptors in memory, such as buffer resources,
 117  * image resources, and sampler states.
 118  */
 119 struct si_descriptors {
 120         struct si_atom atom;
 121
 122         /* The size of one resource descriptor. */
 123         unsigned element_dw_size;
 124         /* The maximum number of resource descriptors. */
 125         unsigned num_elements;
 126
 127         /* The buffer where resource descriptors are stored. */
 128         struct si_resource *buffer;
 129
 130         /* The i-th bit is set if that element is dirty (changed but not emitted). */
 131         unsigned dirty_mask;
 132         /* The i-th bit is set if that element is enabled (non-NULL resource). */
 133         unsigned enabled_mask;
 134
 135         /* We can't update descriptors directly because the GPU might be
 136          * reading them at the same time, so we have to update them
 137          * in a copy-on-write manner. Each such copy is called a context,
 138          * which is just another array descriptors in the same buffer. */
 139         unsigned current_context_id;
 140         /* The size of a context, should be equal to 4*element_dw_size*num_elements. */
 141         unsigned context_size;
 142
 143         /* The shader userdata register where the 64-bit pointer to the descriptor
 144          * array will be stored. */
 145         unsigned shader_userdata_reg;
 146 };
 147
 148 struct si_sampler_views {
 149         struct si_descriptors           desc;
 150         struct pipe_sampler_view        *views[NUM_TEX_UNITS];
 151         const uint32_t                  *desc_data[NUM_TEX_UNITS];
 152 };
 153
 154 #define si_pm4_block_idx(member) \
 155         (offsetof(union si_state, named.member) / sizeof(struct si_pm4_state *))
 156
 157 #define si_pm4_state_changed(rctx, member) \
 158         ((rctx)->queued.named.member != (rctx)->emitted.named.member)
 159
 160 #define si_pm4_bind_state(rctx, member, value) \
 161         do { \
 162                 (rctx)->queued.named.member = (value); \
 163         } while(0)
 164
 165 #define si_pm4_delete_state(rctx, member, value) \
 166         do { \
 167                 if ((rctx)->queued.named.member == (value)) { \
 168                         (rctx)->queued.named.member = NULL; \
 169                 } \
 170                 si_pm4_free_state(rctx, (struct si_pm4_state *)(value), \
 171                                   si_pm4_block_idx(member)); \
 172         } while(0)
 173
 174 #define si_pm4_set_state(rctx, member, value) \
 175         do { \
 176                 if ((rctx)->queued.named.member != (value)) { \
 177                         si_pm4_free_state(rctx, \
 178                                 (struct si_pm4_state *)(rctx)->queued.named.member, \
 179                                 si_pm4_block_idx(member)); \
 180                         (rctx)->queued.named.member = (value); \
 181                 } \
 182         } while(0)
 183
 184 /* si_descriptors.c */
 185 void si_set_sampler_view(struct r600_context *rctx, unsigned shader,
 186                          unsigned slot, struct pipe_sampler_view *view,
 187                          unsigned *view_desc);
 188 void si_init_all_descriptors(struct r600_context *rctx);
 189 void si_release_all_descriptors(struct r600_context *rctx);
 190 void si_all_descriptors_begin_new_cs(struct r600_context *rctx);
 191
 192 /* si_state.c */
 193 struct si_pipe_shader_selector;
 194
 195 boolean si_is_format_supported(struct pipe_screen *screen,
 196                                enum pipe_format format,
 197                                enum pipe_texture_target target,
 198                                unsigned sample_count,
 199                                unsigned usage);
 200 int si_shader_select(struct pipe_context *ctx,
 201                      struct si_pipe_shader_selector *sel,
 202                      unsigned *dirty);
 203 void si_init_state_functions(struct r600_context *rctx);
 204 void si_init_config(struct r600_context *rctx);
 205
 206 /* si_state_streamout.c */
 207 struct pipe_stream_output_target *
 208 si_create_so_target(struct pipe_context *ctx,
 209                     struct pipe_resource *buffer,
 210                     unsigned buffer_offset,
 211                     unsigned buffer_size);
 212 void si_so_target_destroy(struct pipe_context *ctx,
 213                           struct pipe_stream_output_target *target);
 214 void si_set_so_targets(struct pipe_context *ctx,
 215                        unsigned num_targets,
 216                        struct pipe_stream_output_target **targets,
 217                        unsigned append_bitmask);
 218
 219 /* si_state_draw.c */
 220 void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *dinfo);
 221
 222 /* si_commands.c */
 223 void si_cmd_context_control(struct si_pm4_state *pm4);
 224 void si_cmd_draw_index_2(struct si_pm4_state *pm4, uint32_t max_size,
 225                          uint64_t index_base, uint32_t index_count,
 226                          uint32_t initiator, bool predicate);
 227 void si_cmd_draw_index_auto(struct si_pm4_state *pm4, uint32_t count,
 228                             uint32_t initiator, bool predicate);
 229 void si_cmd_surface_sync(struct si_pm4_state *pm4, uint32_t cp_coher_cntl);
 230
 231 #endif