src/gallium/drivers/radeonsi/si_state.h

   1 /*
   2  * Copyright 2012 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Christian König <christian.koenig@amd.com>
  25  */
  26
  27 #ifndef SI_STATE_H
  28 #define SI_STATE_H
  29
  30 #include "si_pm4.h"
  31 #include "radeon/r600_pipe_common.h"
  32
  33 #define SI_NUM_GRAPHICS_SHADERS (PIPE_SHADER_TESS_EVAL+1)
  34 #define SI_NUM_SHADERS (PIPE_SHADER_COMPUTE+1)
  35
  36 #define SI_MAX_ATTRIBS                  16
  37 #define SI_NUM_VERTEX_BUFFERS           SI_MAX_ATTRIBS
  38 #define SI_NUM_SAMPLERS                 32 /* OpenGL textures units per shader */
  39 #define SI_NUM_CONST_BUFFERS            16
  40 #define SI_NUM_IMAGES                   16
  41 #define SI_NUM_SHADER_BUFFERS           16
  42
  43 struct si_screen;
  44 struct si_shader;
  45 struct si_shader_selector;
  46
  47 struct si_state_blend {
  48         struct si_pm4_state     pm4;
  49         uint32_t                cb_target_mask;
  50         bool                    alpha_to_coverage;
  51         bool                    alpha_to_one;
  52         bool                    dual_src_blend;
  53         /* Set 0xf or 0x0 (4 bits) per render target if the following is
  54          * true. ANDed with spi_shader_col_format.
  55          */
  56         unsigned                blend_enable_4bit;
  57         unsigned                need_src_alpha_4bit;
  58 };
  59
  60 struct si_state_rasterizer {
  61         struct si_pm4_state     pm4;
  62         /* poly offset states for 16-bit, 24-bit, and 32-bit zbuffers */
  63         struct si_pm4_state     *pm4_poly_offset;
  64         unsigned                pa_sc_line_stipple;
  65         unsigned                pa_cl_clip_cntl;
  66         unsigned                sprite_coord_enable:8;
  67         unsigned                clip_plane_enable:8;
  68         unsigned                flatshade:1;
  69         unsigned                two_side:1;
  70         unsigned                multisample_enable:1;
  71         unsigned                force_persample_interp:1;
  72         unsigned                line_stipple_enable:1;
  73         unsigned                poly_stipple_enable:1;
  74         unsigned                line_smooth:1;
  75         unsigned                poly_smooth:1;
  76         unsigned                uses_poly_offset:1;
  77         unsigned                clamp_fragment_color:1;
  78         unsigned                clamp_vertex_color:1;
  79         unsigned                rasterizer_discard:1;
  80         unsigned                scissor_enable:1;
  81         unsigned                clip_halfz:1;
  82 };
  83
  84 struct si_dsa_stencil_ref_part {
  85         uint8_t                 valuemask[2];
  86         uint8_t                 writemask[2];
  87 };
  88
  89 struct si_state_dsa {
  90         struct si_pm4_state             pm4;
  91         unsigned                        alpha_func;
  92         struct si_dsa_stencil_ref_part  stencil_ref;
  93 };
  94
  95 struct si_stencil_ref {
  96         struct r600_atom                atom;
  97         struct pipe_stencil_ref         state;
  98         struct si_dsa_stencil_ref_part  dsa_part;
  99 };
 100
 101 struct si_vertex_elements
 102 {
 103         uint32_t                        instance_divisors[SI_MAX_ATTRIBS];
 104         uint32_t                        rsrc_word3[SI_MAX_ATTRIBS];
 105         uint16_t                        src_offset[SI_MAX_ATTRIBS];
 106         uint8_t                         fix_fetch[SI_MAX_ATTRIBS];
 107         uint8_t                         format_size[SI_MAX_ATTRIBS];
 108         uint8_t                         vertex_buffer_index[SI_MAX_ATTRIBS];
 109
 110         uint8_t                         count;
 111         bool                            uses_instance_divisors;
 112
 113         uint16_t                        first_vb_use_mask;
 114         /* Vertex buffer descriptor list size aligned for optimal prefetch. */
 115         uint16_t                        desc_list_byte_size;
 116 };
 117
 118 union si_state {
 119         struct {
 120                 struct si_state_blend           *blend;
 121                 struct si_state_rasterizer      *rasterizer;
 122                 struct si_state_dsa             *dsa;
 123                 struct si_pm4_state             *poly_offset;
 124                 struct si_pm4_state             *ls;
 125                 struct si_pm4_state             *hs;
 126                 struct si_pm4_state             *es;
 127                 struct si_pm4_state             *gs;
 128                 struct si_pm4_state             *vgt_shader_config;
 129                 struct si_pm4_state             *vs;
 130                 struct si_pm4_state             *ps;
 131         } named;
 132         struct si_pm4_state     *array[0];
 133 };
 134
 135 #define SI_NUM_STATES (sizeof(union si_state) / sizeof(struct si_pm4_state *))
 136
 137 union si_state_atoms {
 138         struct {
 139                 /* The order matters. */
 140                 struct r600_atom *prefetch_L2;
 141                 struct r600_atom *render_cond;
 142                 struct r600_atom *streamout_begin;
 143                 struct r600_atom *streamout_enable; /* must be after streamout_begin */
 144                 struct r600_atom *framebuffer;
 145                 struct r600_atom *msaa_sample_locs;
 146                 struct r600_atom *db_render_state;
 147                 struct r600_atom *msaa_config;
 148                 struct r600_atom *sample_mask;
 149                 struct r600_atom *cb_render_state;
 150                 struct r600_atom *blend_color;
 151                 struct r600_atom *clip_regs;
 152                 struct r600_atom *clip_state;
 153                 struct r600_atom *shader_userdata;
 154                 struct r600_atom *scissors;
 155                 struct r600_atom *viewports;
 156                 struct r600_atom *stencil_ref;
 157                 struct r600_atom *spi_map;
 158                 struct r600_atom *scratch_state;
 159         } s;
 160         struct r600_atom *array[0];
 161 };
 162
 163 #define SI_NUM_ATOMS (sizeof(union si_state_atoms)/sizeof(struct r600_atom*))
 164
 165 struct si_shader_data {
 166         struct r600_atom        atom;
 167         uint32_t                sh_base[SI_NUM_SHADERS];
 168 };
 169
 170 /* Private read-write buffer slots. */
 171 enum {
 172         SI_ES_RING_ESGS,
 173         SI_GS_RING_ESGS,
 174
 175         SI_RING_GSVS,
 176
 177         SI_VS_STREAMOUT_BUF0,
 178         SI_VS_STREAMOUT_BUF1,
 179         SI_VS_STREAMOUT_BUF2,
 180         SI_VS_STREAMOUT_BUF3,
 181
 182         SI_HS_CONST_DEFAULT_TESS_LEVELS,
 183         SI_VS_CONST_CLIP_PLANES,
 184         SI_PS_CONST_POLY_STIPPLE,
 185         SI_PS_CONST_SAMPLE_POSITIONS,
 186
 187         SI_NUM_RW_BUFFERS,
 188 };
 189
 190 /* Indices into sctx->descriptors, laid out so that gfx and compute pipelines
 191  * are contiguous:
 192  *
 193  *  0 - rw buffers
 194  *  1 - vertex const buffers
 195  *  2 - vertex shader buffers
 196  *   ...
 197  *  5 - fragment const buffers
 198  *   ...
 199  *  21 - compute const buffers
 200  *   ...
 201  */
 202 enum {
 203         SI_SHADER_DESCS_CONST_AND_SHADER_BUFFERS,
 204         SI_SHADER_DESCS_SAMPLERS_AND_IMAGES,
 205         SI_NUM_SHADER_DESCS,
 206 };
 207
 208 #define SI_DESCS_RW_BUFFERS            0
 209 #define SI_DESCS_FIRST_SHADER          1
 210 #define SI_DESCS_FIRST_COMPUTE         (SI_DESCS_FIRST_SHADER + \
 211                                         PIPE_SHADER_COMPUTE * SI_NUM_SHADER_DESCS)
 212 #define SI_NUM_DESCS                   (SI_DESCS_FIRST_SHADER + \
 213                                         SI_NUM_SHADERS * SI_NUM_SHADER_DESCS)
 214
 215 /* This represents descriptors in memory, such as buffer resources,
 216  * image resources, and sampler states.
 217  */
 218 struct si_descriptors {
 219         /* The list of descriptors in malloc'd memory. */
 220         uint32_t *list;
 221         /* The list in mapped GPU memory. */
 222         uint32_t *gpu_list;
 223         /* Slots that have been changed and need to be uploaded. */
 224         uint64_t dirty_mask;
 225
 226         /* The buffer where the descriptors have been uploaded. */
 227         struct r600_resource *buffer;
 228         int buffer_offset; /* can be negative if not using lower slots */
 229
 230         /* The size of one descriptor. */
 231         ubyte element_dw_size;
 232         /* The maximum number of descriptors. */
 233         ubyte num_elements;
 234
 235         /* Offset in CE RAM */
 236         uint16_t ce_offset;
 237
 238         /* Slots allocated in CE RAM. If we get active slots outside of this
 239          * range, direct uploads to memory will be used instead. This basically
 240          * governs switching between onchip (CE) and offchip (upload) modes.
 241          */
 242         ubyte first_ce_slot;
 243         ubyte num_ce_slots;
 244
 245         /* Slots that are used by currently-bound shaders.
 246          * With CE: It determines which slots are dumped to L2.
 247          *          It doesn't skip uploads to CE RAM.
 248          * Without CE: It determines which slots are uploaded.
 249          */
 250         ubyte first_active_slot;
 251         ubyte num_active_slots;
 252
 253         /* Whether CE is used to upload this descriptor array. */
 254         bool uses_ce;
 255
 256         /* The SGPR index where the 64-bit pointer to the descriptor array will
 257          * be stored. */
 258         ubyte shader_userdata_offset;
 259 };
 260
 261 struct si_sampler_views {
 262         struct pipe_sampler_view        *views[SI_NUM_SAMPLERS];
 263         struct si_sampler_state         *sampler_states[SI_NUM_SAMPLERS];
 264
 265         /* The i-th bit is set if that element is enabled (non-NULL resource). */
 266         unsigned                        enabled_mask;
 267 };
 268
 269 struct si_buffer_resources {
 270         enum radeon_bo_usage            shader_usage; /* READ, WRITE, or READWRITE */
 271         enum radeon_bo_usage            shader_usage_constbuf;
 272         enum radeon_bo_priority         priority;
 273         enum radeon_bo_priority         priority_constbuf;
 274         struct pipe_resource            **buffers; /* this has num_buffers elements */
 275
 276         /* The i-th bit is set if that element is enabled (non-NULL resource). */
 277         unsigned                        enabled_mask;
 278 };
 279
 280 #define si_pm4_block_idx(member) \
 281         (offsetof(union si_state, named.member) / sizeof(struct si_pm4_state *))
 282
 283 #define si_pm4_state_changed(sctx, member) \
 284         ((sctx)->queued.named.member != (sctx)->emitted.named.member)
 285
 286 #define si_pm4_bind_state(sctx, member, value) \
 287         do { \
 288                 (sctx)->queued.named.member = (value); \
 289                 (sctx)->dirty_states |= 1 << si_pm4_block_idx(member); \
 290         } while(0)
 291
 292 #define si_pm4_delete_state(sctx, member, value) \
 293         do { \
 294                 if ((sctx)->queued.named.member == (value)) { \
 295                         (sctx)->queued.named.member = NULL; \
 296                 } \
 297                 si_pm4_free_state(sctx, (struct si_pm4_state *)(value), \
 298                                   si_pm4_block_idx(member)); \
 299         } while(0)
 300
 301 /* si_descriptors.c */
 302 void si_ce_save_all_descriptors_at_ib_end(struct si_context* sctx);
 303 void si_ce_restore_all_descriptors_at_ib_start(struct si_context *sctx);
 304 void si_ce_enable_loads(struct radeon_winsys_cs *ib);
 305 void si_set_mutable_tex_desc_fields(struct si_screen *sscreen,
 306                                     struct r600_texture *tex,
 307                                     const struct legacy_surf_level *base_level_info,
 308                                     unsigned base_level, unsigned first_level,
 309                                     unsigned block_width, bool is_stencil,
 310                                     uint32_t *state);
 311 void si_get_pipe_constant_buffer(struct si_context *sctx, uint shader,
 312                                  uint slot, struct pipe_constant_buffer *cbuf);
 313 void si_get_shader_buffers(struct si_context *sctx,
 314                            enum pipe_shader_type shader,
 315                            uint start_slot, uint count,
 316                            struct pipe_shader_buffer *sbuf);
 317 void si_set_ring_buffer(struct pipe_context *ctx, uint slot,
 318                         struct pipe_resource *buffer,
 319                         unsigned stride, unsigned num_records,
 320                         bool add_tid, bool swizzle,
 321                         unsigned element_size, unsigned index_stride, uint64_t offset);
 322 void si_init_all_descriptors(struct si_context *sctx);
 323 bool si_upload_vertex_buffer_descriptors(struct si_context *sctx);
 324 bool si_upload_graphics_shader_descriptors(struct si_context *sctx);
 325 bool si_upload_compute_shader_descriptors(struct si_context *sctx);
 326 void si_release_all_descriptors(struct si_context *sctx);
 327 void si_all_descriptors_begin_new_cs(struct si_context *sctx);
 328 void si_upload_const_buffer(struct si_context *sctx, struct r600_resource **rbuffer,
 329                             const uint8_t *ptr, unsigned size, uint32_t *const_offset);
 330 void si_update_all_texture_descriptors(struct si_context *sctx);
 331 void si_shader_change_notify(struct si_context *sctx);
 332 void si_update_needs_color_decompress_masks(struct si_context *sctx);
 333 void si_emit_graphics_shader_userdata(struct si_context *sctx,
 334                                       struct r600_atom *atom);
 335 void si_emit_compute_shader_userdata(struct si_context *sctx);
 336 void si_set_rw_buffer(struct si_context *sctx,
 337                       uint slot, const struct pipe_constant_buffer *input);
 338 void si_set_active_descriptors(struct si_context *sctx, unsigned desc_idx,
 339                                uint64_t new_active_mask);
 340 void si_set_active_descriptors_for_shader(struct si_context *sctx,
 341                                           struct si_shader_selector *sel);
 342
 343 /* si_state.c */
 344 struct si_shader_selector;
 345
 346 void si_init_atom(struct si_context *sctx, struct r600_atom *atom,
 347                   struct r600_atom **list_elem,
 348                   void (*emit_func)(struct si_context *ctx, struct r600_atom *state));
 349 void si_init_state_functions(struct si_context *sctx);
 350 void si_init_screen_state_functions(struct si_screen *sscreen);
 351 void
 352 si_make_buffer_descriptor(struct si_screen *screen, struct r600_resource *buf,
 353                           enum pipe_format format,
 354                           unsigned offset, unsigned size,
 355                           uint32_t *state);
 356 void
 357 si_make_texture_descriptor(struct si_screen *screen,
 358                            struct r600_texture *tex,
 359                            bool sampler,
 360                            enum pipe_texture_target target,
 361                            enum pipe_format pipe_format,
 362                            const unsigned char state_swizzle[4],
 363                            unsigned first_level, unsigned last_level,
 364                            unsigned first_layer, unsigned last_layer,
 365                            unsigned width, unsigned height, unsigned depth,
 366                            uint32_t *state,
 367                            uint32_t *fmask_state);
 368 struct pipe_sampler_view *
 369 si_create_sampler_view_custom(struct pipe_context *ctx,
 370                               struct pipe_resource *texture,
 371                               const struct pipe_sampler_view *state,
 372                               unsigned width0, unsigned height0,
 373                               unsigned force_level);
 374
 375 /* si_state_shader.c */
 376 bool si_update_shaders(struct si_context *sctx);
 377 void si_init_shader_functions(struct si_context *sctx);
 378 bool si_init_shader_cache(struct si_screen *sscreen);
 379 void si_destroy_shader_cache(struct si_screen *sscreen);
 380 void si_init_shader_selector_async(void *job, int thread_index);
 381 void si_get_active_slot_masks(const struct tgsi_shader_info *info,
 382                               uint32_t *const_and_shader_buffers,
 383                               uint64_t *samplers_and_images);
 384
 385 /* si_state_draw.c */
 386 void si_init_ia_multi_vgt_param_table(struct si_context *sctx);
 387 void si_emit_cache_flush(struct si_context *sctx);
 388 void si_ce_pre_draw_synchronization(struct si_context *sctx);
 389 void si_ce_post_draw_synchronization(struct si_context *sctx);
 390 void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *dinfo);
 391 void si_trace_emit(struct si_context *sctx);
 392
 393
 394 static inline unsigned
 395 si_tile_mode_index(struct r600_texture *rtex, unsigned level, bool stencil)
 396 {
 397         if (stencil)
 398                 return rtex->surface.u.legacy.stencil_tiling_index[level];
 399         else
 400                 return rtex->surface.u.legacy.tiling_index[level];
 401 }
 402
 403 static inline unsigned si_get_constbuf_slot(unsigned slot)
 404 {
 405         /* Constant buffers are in slots [16..31], ascending */
 406         return SI_NUM_SHADER_BUFFERS + slot;
 407 }
 408
 409 static inline unsigned si_get_shaderbuf_slot(unsigned slot)
 410 {
 411         /* shader buffers are in slots [15..0], descending */
 412         return SI_NUM_SHADER_BUFFERS - 1 - slot;
 413 }
 414
 415 static inline unsigned si_get_sampler_slot(unsigned slot)
 416 {
 417         /* samplers are in slots [8..39], ascending */
 418         return SI_NUM_IMAGES / 2 + slot;
 419 }
 420
 421 static inline unsigned si_get_image_slot(unsigned slot)
 422 {
 423         /* images are in slots [15..0] (sampler slots [7..0]), descending */
 424         return SI_NUM_IMAGES - 1 - slot;
 425 }
 426
 427 #endif