src/gallium/drivers/radeonsi/si_state.h

   1 /*
   2  * Copyright 2012 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Christian König <christian.koenig@amd.com>
  25  */
  26
  27 #ifndef SI_STATE_H
  28 #define SI_STATE_H
  29
  30 #include "si_pm4.h"
  31 #include "radeon/r600_pipe_common.h"
  32
  33 #define SI_NUM_GRAPHICS_SHADERS (PIPE_SHADER_TESS_EVAL+1)
  34 #define SI_NUM_SHADERS (PIPE_SHADER_COMPUTE+1)
  35
  36 #define SI_MAX_ATTRIBS                  16
  37 #define SI_NUM_VERTEX_BUFFERS           SI_MAX_ATTRIBS
  38 #define SI_NUM_SAMPLERS                 32 /* OpenGL textures units per shader */
  39 #define SI_NUM_CONST_BUFFERS            16
  40 #define SI_NUM_IMAGES                   16
  41 #define SI_NUM_SHADER_BUFFERS           16
  42
  43 #define SI_TESS_OFFCHIP_BLOCK_SIZE      (8192 * 4)
  44
  45 struct si_screen;
  46 struct si_shader;
  47
  48 struct si_state_blend {
  49         struct si_pm4_state     pm4;
  50         uint32_t                cb_target_mask;
  51         bool                    alpha_to_coverage;
  52         bool                    alpha_to_one;
  53         bool                    dual_src_blend;
  54         /* Set 0xf or 0x0 (4 bits) per render target if the following is
  55          * true. ANDed with spi_shader_col_format.
  56          */
  57         unsigned                blend_enable_4bit;
  58         unsigned                need_src_alpha_4bit;
  59 };
  60
  61 struct si_state_rasterizer {
  62         struct si_pm4_state     pm4;
  63         /* poly offset states for 16-bit, 24-bit, and 32-bit zbuffers */
  64         struct si_pm4_state     pm4_poly_offset[3];
  65         bool                    flatshade;
  66         bool                    two_side;
  67         bool                    multisample_enable;
  68         bool                    force_persample_interp;
  69         bool                    line_stipple_enable;
  70         unsigned                sprite_coord_enable;
  71         unsigned                pa_sc_line_stipple;
  72         unsigned                pa_cl_clip_cntl;
  73         unsigned                clip_plane_enable;
  74         bool                    poly_stipple_enable;
  75         bool                    line_smooth;
  76         bool                    poly_smooth;
  77         bool                    uses_poly_offset;
  78         bool                    clamp_fragment_color;
  79         bool                    rasterizer_discard;
  80         bool                    scissor_enable;
  81 };
  82
  83 struct si_dsa_stencil_ref_part {
  84         uint8_t                 valuemask[2];
  85         uint8_t                 writemask[2];
  86 };
  87
  88 struct si_state_dsa {
  89         struct si_pm4_state             pm4;
  90         unsigned                        alpha_func;
  91         struct si_dsa_stencil_ref_part  stencil_ref;
  92 };
  93
  94 struct si_stencil_ref {
  95         struct r600_atom                atom;
  96         struct pipe_stencil_ref         state;
  97         struct si_dsa_stencil_ref_part  dsa_part;
  98 };
  99
 100 struct si_vertex_element
 101 {
 102         unsigned                        count;
 103         uint32_t                        rsrc_word3[SI_MAX_ATTRIBS];
 104         uint32_t                        format_size[SI_MAX_ATTRIBS];
 105         struct pipe_vertex_element      elements[SI_MAX_ATTRIBS];
 106 };
 107
 108 union si_state {
 109         struct {
 110                 struct si_state_blend           *blend;
 111                 struct si_state_rasterizer      *rasterizer;
 112                 struct si_state_dsa             *dsa;
 113                 struct si_pm4_state             *poly_offset;
 114                 struct si_pm4_state             *ls;
 115                 struct si_pm4_state             *hs;
 116                 struct si_pm4_state             *es;
 117                 struct si_pm4_state             *gs;
 118                 struct si_pm4_state             *vgt_shader_config;
 119                 struct si_pm4_state             *vs;
 120                 struct si_pm4_state             *ps;
 121         } named;
 122         struct si_pm4_state     *array[0];
 123 };
 124
 125 union si_state_atoms {
 126         struct {
 127                 /* The order matters. */
 128                 struct r600_atom *cache_flush;
 129                 struct r600_atom *render_cond;
 130                 struct r600_atom *streamout_begin;
 131                 struct r600_atom *streamout_enable; /* must be after streamout_begin */
 132                 struct r600_atom *framebuffer;
 133                 struct r600_atom *msaa_sample_locs;
 134                 struct r600_atom *db_render_state;
 135                 struct r600_atom *msaa_config;
 136                 struct r600_atom *sample_mask;
 137                 struct r600_atom *cb_render_state;
 138                 struct r600_atom *blend_color;
 139                 struct r600_atom *clip_regs;
 140                 struct r600_atom *clip_state;
 141                 struct r600_atom *shader_userdata;
 142                 struct r600_atom *scissors;
 143                 struct r600_atom *viewports;
 144                 struct r600_atom *stencil_ref;
 145                 struct r600_atom *spi_map;
 146         } s;
 147         struct r600_atom *array[0];
 148 };
 149
 150 #define SI_NUM_ATOMS (sizeof(union si_state_atoms)/sizeof(struct r600_atom*))
 151
 152 struct si_shader_data {
 153         struct r600_atom        atom;
 154         uint32_t                sh_base[SI_NUM_SHADERS];
 155 };
 156
 157 /* Private read-write buffer slots. */
 158 enum {
 159         SI_HS_RING_TESS_FACTOR,
 160         SI_HS_RING_TESS_OFFCHIP,
 161
 162         SI_ES_RING_ESGS,
 163         SI_GS_RING_ESGS,
 164
 165         SI_GS_RING_GSVS0,
 166         SI_GS_RING_GSVS1,
 167         SI_GS_RING_GSVS2,
 168         SI_GS_RING_GSVS3,
 169         SI_VS_RING_GSVS,
 170
 171         SI_VS_STREAMOUT_BUF0,
 172         SI_VS_STREAMOUT_BUF1,
 173         SI_VS_STREAMOUT_BUF2,
 174         SI_VS_STREAMOUT_BUF3,
 175
 176         SI_HS_CONST_DEFAULT_TESS_LEVELS,
 177         SI_VS_CONST_CLIP_PLANES,
 178         SI_PS_CONST_POLY_STIPPLE,
 179         SI_PS_CONST_SAMPLE_POSITIONS,
 180
 181         SI_NUM_RW_BUFFERS,
 182 };
 183
 184 /* Indices into sctx->descriptors, laid out so that gfx and compute pipelines
 185  * are contiguous:
 186  *
 187  *  0 - rw buffers
 188  *  1 - vertex const buffers
 189  *  2 - vertex shader buffers
 190  *   ...
 191  *  5 - fragment const buffers
 192  *   ...
 193  *  21 - compute const buffers
 194  *   ...
 195  */
 196 #define SI_SHADER_DESCS_CONST_BUFFERS  0
 197 #define SI_SHADER_DESCS_SHADER_BUFFERS 1
 198 #define SI_SHADER_DESCS_SAMPLERS       2
 199 #define SI_SHADER_DESCS_IMAGES         3
 200 #define SI_NUM_SHADER_DESCS            4
 201
 202 #define SI_DESCS_RW_BUFFERS            0
 203 #define SI_DESCS_FIRST_SHADER          1
 204 #define SI_DESCS_FIRST_COMPUTE         (SI_DESCS_FIRST_SHADER + \
 205                                         PIPE_SHADER_COMPUTE * SI_NUM_SHADER_DESCS)
 206 #define SI_NUM_DESCS                   (SI_DESCS_FIRST_SHADER + \
 207                                         SI_NUM_SHADERS * SI_NUM_SHADER_DESCS)
 208
 209 /* This represents descriptors in memory, such as buffer resources,
 210  * image resources, and sampler states.
 211  */
 212 struct si_descriptors {
 213         /* The list of descriptors in malloc'd memory. */
 214         uint32_t *list;
 215         /* The size of one descriptor. */
 216         unsigned element_dw_size;
 217         /* The maximum number of descriptors. */
 218         unsigned num_elements;
 219
 220         /* The buffer where the descriptors have been uploaded. */
 221         struct r600_resource *buffer;
 222         unsigned buffer_offset;
 223
 224         /* Offset in CE RAM */
 225         unsigned ce_offset;
 226
 227         /* elements of the list that are changed and need to be uploaded */
 228         unsigned dirty_mask;
 229
 230         /* Whether the CE ram is dirty and needs to be reinitialized entirely
 231          * before we can do partial updates. */
 232         bool ce_ram_dirty;
 233
 234         /* The shader userdata offset within a shader where the 64-bit pointer to the descriptor
 235          * array will be stored. */
 236         unsigned shader_userdata_offset;
 237         /* Whether the pointer should be re-emitted. */
 238         bool pointer_dirty;
 239 };
 240
 241 struct si_sampler_views {
 242         struct pipe_sampler_view        *views[SI_NUM_SAMPLERS];
 243         void                            *sampler_states[SI_NUM_SAMPLERS];
 244
 245         /* The i-th bit is set if that element is enabled (non-NULL resource). */
 246         unsigned                        enabled_mask;
 247 };
 248
 249 struct si_buffer_resources {
 250         enum radeon_bo_usage            shader_usage; /* READ, WRITE, or READWRITE */
 251         enum radeon_bo_priority         priority;
 252         struct pipe_resource            **buffers; /* this has num_buffers elements */
 253
 254         /* The i-th bit is set if that element is enabled (non-NULL resource). */
 255         unsigned                        enabled_mask;
 256 };
 257
 258 #define si_pm4_block_idx(member) \
 259         (offsetof(union si_state, named.member) / sizeof(struct si_pm4_state *))
 260
 261 #define si_pm4_state_changed(sctx, member) \
 262         ((sctx)->queued.named.member != (sctx)->emitted.named.member)
 263
 264 #define si_pm4_bind_state(sctx, member, value) \
 265         do { \
 266                 (sctx)->queued.named.member = (value); \
 267         } while(0)
 268
 269 #define si_pm4_delete_state(sctx, member, value) \
 270         do { \
 271                 if ((sctx)->queued.named.member == (value)) { \
 272                         (sctx)->queued.named.member = NULL; \
 273                 } \
 274                 si_pm4_free_state(sctx, (struct si_pm4_state *)(value), \
 275                                   si_pm4_block_idx(member)); \
 276         } while(0)
 277
 278 /* si_descriptors.c */
 279 void si_ce_reinitialize_all_descriptors(struct si_context *sctx);
 280 void si_ce_enable_loads(struct radeon_winsys_cs *ib);
 281 void si_set_mutable_tex_desc_fields(struct r600_texture *tex,
 282                                     const struct radeon_surf_level *base_level_info,
 283                                     unsigned base_level, unsigned first_level,
 284                                     unsigned block_width, bool is_stencil,
 285                                     uint32_t *state);
 286 void si_set_ring_buffer(struct pipe_context *ctx, uint slot,
 287                         struct pipe_resource *buffer,
 288                         unsigned stride, unsigned num_records,
 289                         bool add_tid, bool swizzle,
 290                         unsigned element_size, unsigned index_stride, uint64_t offset);
 291 void si_init_all_descriptors(struct si_context *sctx);
 292 bool si_upload_graphics_shader_descriptors(struct si_context *sctx);
 293 bool si_upload_compute_shader_descriptors(struct si_context *sctx);
 294 void si_release_all_descriptors(struct si_context *sctx);
 295 void si_all_descriptors_begin_new_cs(struct si_context *sctx);
 296 void si_upload_const_buffer(struct si_context *sctx, struct r600_resource **rbuffer,
 297                             const uint8_t *ptr, unsigned size, uint32_t *const_offset);
 298 void si_update_all_texture_descriptors(struct si_context *sctx);
 299 void si_shader_change_notify(struct si_context *sctx);
 300 void si_update_compressed_colortex_masks(struct si_context *sctx);
 301 void si_emit_graphics_shader_userdata(struct si_context *sctx,
 302                                       struct r600_atom *atom);
 303 void si_emit_compute_shader_userdata(struct si_context *sctx);
 304 void si_set_rw_buffer(struct si_context *sctx,
 305                       uint slot, const struct pipe_constant_buffer *input);
 306 /* si_state.c */
 307 struct si_shader_selector;
 308
 309 void si_init_atom(struct si_context *sctx, struct r600_atom *atom,
 310                   struct r600_atom **list_elem,
 311                   void (*emit_func)(struct si_context *ctx, struct r600_atom *state));
 312 void si_init_state_functions(struct si_context *sctx);
 313 void si_init_screen_state_functions(struct si_screen *sscreen);
 314 void
 315 si_make_buffer_descriptor(struct si_screen *screen, struct r600_resource *buf,
 316                           enum pipe_format format,
 317                           unsigned first_element, unsigned last_element,
 318                           uint32_t *state);
 319 void
 320 si_make_texture_descriptor(struct si_screen *screen,
 321                            struct r600_texture *tex,
 322                            bool sampler,
 323                            enum pipe_texture_target target,
 324                            enum pipe_format pipe_format,
 325                            const unsigned char state_swizzle[4],
 326                            unsigned first_level, unsigned last_level,
 327                            unsigned first_layer, unsigned last_layer,
 328                            unsigned width, unsigned height, unsigned depth,
 329                            uint32_t *state,
 330                            uint32_t *fmask_state);
 331 struct pipe_sampler_view *
 332 si_create_sampler_view_custom(struct pipe_context *ctx,
 333                               struct pipe_resource *texture,
 334                               const struct pipe_sampler_view *state,
 335                               unsigned width0, unsigned height0,
 336                               unsigned force_level);
 337 void si_dec_framebuffer_counters(const struct pipe_framebuffer_state *state);
 338
 339 /* si_state_shader.c */
 340 bool si_update_shaders(struct si_context *sctx);
 341 void si_init_shader_functions(struct si_context *sctx);
 342 bool si_init_shader_cache(struct si_screen *sscreen);
 343 void si_destroy_shader_cache(struct si_screen *sscreen);
 344
 345 /* si_state_draw.c */
 346 void si_emit_cache_flush(struct si_context *sctx, struct r600_atom *atom);
 347 void si_ce_pre_draw_synchronization(struct si_context *sctx);
 348 void si_ce_post_draw_synchronization(struct si_context *sctx);
 349 void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *dinfo);
 350 void si_trace_emit(struct si_context *sctx);
 351
 352
 353 static inline unsigned
 354 si_tile_mode_index(struct r600_texture *rtex, unsigned level, bool stencil)
 355 {
 356         if (stencil)
 357                 return rtex->surface.stencil_tiling_index[level];
 358         else
 359                 return rtex->surface.tiling_index[level];
 360 }
 361
 362 #endif