src/gallium/drivers/radeonsi/si_state.h

   1 /*
   2  * Copyright 2012 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Christian König <christian.koenig@amd.com>
  25  */
  26
  27 #ifndef SI_STATE_H
  28 #define SI_STATE_H
  29
  30 #include "si_pm4.h"
  31 #include "radeon/r600_pipe_common.h"
  32
  33 #include "pipebuffer/pb_slab.h"
  34
  35 #define SI_NUM_GRAPHICS_SHADERS (PIPE_SHADER_TESS_EVAL+1)
  36 #define SI_NUM_SHADERS (PIPE_SHADER_COMPUTE+1)
  37
  38 #define SI_MAX_ATTRIBS                  16
  39 #define SI_NUM_VERTEX_BUFFERS           SI_MAX_ATTRIBS
  40 #define SI_NUM_SAMPLERS                 32 /* OpenGL textures units per shader */
  41 #define SI_NUM_CONST_BUFFERS            16
  42 #define SI_NUM_IMAGES                   16
  43 #define SI_NUM_SHADER_BUFFERS           16
  44
  45 struct si_screen;
  46 struct si_shader;
  47 struct si_shader_selector;
  48
  49 struct si_state_blend {
  50         struct si_pm4_state     pm4;
  51         uint32_t                cb_target_mask;
  52         bool                    alpha_to_coverage;
  53         bool                    alpha_to_one;
  54         bool                    dual_src_blend;
  55         /* Set 0xf or 0x0 (4 bits) per render target if the following is
  56          * true. ANDed with spi_shader_col_format.
  57          */
  58         unsigned                blend_enable_4bit;
  59         unsigned                need_src_alpha_4bit;
  60 };
  61
  62 struct si_state_rasterizer {
  63         struct si_pm4_state     pm4;
  64         /* poly offset states for 16-bit, 24-bit, and 32-bit zbuffers */
  65         struct si_pm4_state     *pm4_poly_offset;
  66         unsigned                pa_sc_line_stipple;
  67         unsigned                pa_cl_clip_cntl;
  68         unsigned                sprite_coord_enable:8;
  69         unsigned                clip_plane_enable:8;
  70         unsigned                flatshade:1;
  71         unsigned                two_side:1;
  72         unsigned                multisample_enable:1;
  73         unsigned                force_persample_interp:1;
  74         unsigned                line_stipple_enable:1;
  75         unsigned                poly_stipple_enable:1;
  76         unsigned                line_smooth:1;
  77         unsigned                poly_smooth:1;
  78         unsigned                uses_poly_offset:1;
  79         unsigned                clamp_fragment_color:1;
  80         unsigned                clamp_vertex_color:1;
  81         unsigned                rasterizer_discard:1;
  82         unsigned                scissor_enable:1;
  83         unsigned                clip_halfz:1;
  84 };
  85
  86 struct si_dsa_stencil_ref_part {
  87         uint8_t                 valuemask[2];
  88         uint8_t                 writemask[2];
  89 };
  90
  91 struct si_state_dsa {
  92         struct si_pm4_state             pm4;
  93         unsigned                        alpha_func;
  94         struct si_dsa_stencil_ref_part  stencil_ref;
  95 };
  96
  97 struct si_stencil_ref {
  98         struct r600_atom                atom;
  99         struct pipe_stencil_ref         state;
 100         struct si_dsa_stencil_ref_part  dsa_part;
 101 };
 102
 103 struct si_vertex_elements
 104 {
 105         uint32_t                        instance_divisors[SI_MAX_ATTRIBS];
 106         uint32_t                        rsrc_word3[SI_MAX_ATTRIBS];
 107         uint16_t                        src_offset[SI_MAX_ATTRIBS];
 108         uint8_t                         fix_fetch[SI_MAX_ATTRIBS];
 109         uint8_t                         format_size[SI_MAX_ATTRIBS];
 110         uint8_t                         vertex_buffer_index[SI_MAX_ATTRIBS];
 111
 112         uint8_t                         count;
 113         bool                            uses_instance_divisors;
 114
 115         uint16_t                        first_vb_use_mask;
 116         /* Vertex buffer descriptor list size aligned for optimal prefetch. */
 117         uint16_t                        desc_list_byte_size;
 118         uint16_t                        instance_divisor_is_one; /* bitmask of inputs */
 119         uint16_t                        instance_divisor_is_fetched;  /* bitmask of inputs */
 120 };
 121
 122 union si_state {
 123         struct {
 124                 struct si_state_blend           *blend;
 125                 struct si_state_rasterizer      *rasterizer;
 126                 struct si_state_dsa             *dsa;
 127                 struct si_pm4_state             *poly_offset;
 128                 struct si_pm4_state             *ls;
 129                 struct si_pm4_state             *hs;
 130                 struct si_pm4_state             *es;
 131                 struct si_pm4_state             *gs;
 132                 struct si_pm4_state             *vgt_shader_config;
 133                 struct si_pm4_state             *vs;
 134                 struct si_pm4_state             *ps;
 135         } named;
 136         struct si_pm4_state     *array[0];
 137 };
 138
 139 #define SI_NUM_STATES (sizeof(union si_state) / sizeof(struct si_pm4_state *))
 140
 141 union si_state_atoms {
 142         struct {
 143                 /* The order matters. */
 144                 struct r600_atom *prefetch_L2;
 145                 struct r600_atom *render_cond;
 146                 struct r600_atom *streamout_begin;
 147                 struct r600_atom *streamout_enable; /* must be after streamout_begin */
 148                 struct r600_atom *framebuffer;
 149                 struct r600_atom *msaa_sample_locs;
 150                 struct r600_atom *db_render_state;
 151                 struct r600_atom *msaa_config;
 152                 struct r600_atom *sample_mask;
 153                 struct r600_atom *cb_render_state;
 154                 struct r600_atom *blend_color;
 155                 struct r600_atom *clip_regs;
 156                 struct r600_atom *clip_state;
 157                 struct r600_atom *shader_userdata;
 158                 struct r600_atom *scissors;
 159                 struct r600_atom *viewports;
 160                 struct r600_atom *stencil_ref;
 161                 struct r600_atom *spi_map;
 162                 struct r600_atom *scratch_state;
 163         } s;
 164         struct r600_atom *array[0];
 165 };
 166
 167 #define SI_NUM_ATOMS (sizeof(union si_state_atoms)/sizeof(struct r600_atom*))
 168
 169 struct si_shader_data {
 170         struct r600_atom        atom;
 171         uint32_t                sh_base[SI_NUM_SHADERS];
 172 };
 173
 174 /* Private read-write buffer slots. */
 175 enum {
 176         SI_ES_RING_ESGS,
 177         SI_GS_RING_ESGS,
 178
 179         SI_RING_GSVS,
 180
 181         SI_VS_STREAMOUT_BUF0,
 182         SI_VS_STREAMOUT_BUF1,
 183         SI_VS_STREAMOUT_BUF2,
 184         SI_VS_STREAMOUT_BUF3,
 185
 186         SI_HS_CONST_DEFAULT_TESS_LEVELS,
 187         SI_VS_CONST_INSTANCE_DIVISORS,
 188         SI_VS_CONST_CLIP_PLANES,
 189         SI_PS_CONST_POLY_STIPPLE,
 190         SI_PS_CONST_SAMPLE_POSITIONS,
 191
 192         SI_NUM_RW_BUFFERS,
 193 };
 194
 195 /* Indices into sctx->descriptors, laid out so that gfx and compute pipelines
 196  * are contiguous:
 197  *
 198  *  0 - rw buffers
 199  *  1 - vertex const buffers
 200  *  2 - vertex shader buffers
 201  *   ...
 202  *  5 - fragment const buffers
 203  *   ...
 204  *  21 - compute const buffers
 205  *   ...
 206  */
 207 enum {
 208         SI_SHADER_DESCS_CONST_AND_SHADER_BUFFERS,
 209         SI_SHADER_DESCS_SAMPLERS_AND_IMAGES,
 210         SI_NUM_SHADER_DESCS,
 211 };
 212
 213 #define SI_DESCS_RW_BUFFERS            0
 214 #define SI_DESCS_FIRST_SHADER          1
 215 #define SI_DESCS_FIRST_COMPUTE         (SI_DESCS_FIRST_SHADER + \
 216                                         PIPE_SHADER_COMPUTE * SI_NUM_SHADER_DESCS)
 217 #define SI_NUM_DESCS                   (SI_DESCS_FIRST_SHADER + \
 218                                         SI_NUM_SHADERS * SI_NUM_SHADER_DESCS)
 219
 220 /* This represents descriptors in memory, such as buffer resources,
 221  * image resources, and sampler states.
 222  */
 223 struct si_descriptors {
 224         /* The list of descriptors in malloc'd memory. */
 225         uint32_t *list;
 226         /* The list in mapped GPU memory. */
 227         uint32_t *gpu_list;
 228         /* Slots that have been changed and need to be uploaded. */
 229         uint64_t dirty_mask;
 230
 231         /* The buffer where the descriptors have been uploaded. */
 232         struct r600_resource *buffer;
 233         int buffer_offset; /* can be negative if not using lower slots */
 234
 235         /* The size of one descriptor. */
 236         ubyte element_dw_size;
 237         /* The maximum number of descriptors. */
 238         ubyte num_elements;
 239
 240         /* Offset in CE RAM */
 241         uint16_t ce_offset;
 242
 243         /* Slots allocated in CE RAM. If we get active slots outside of this
 244          * range, direct uploads to memory will be used instead. This basically
 245          * governs switching between onchip (CE) and offchip (upload) modes.
 246          */
 247         ubyte first_ce_slot;
 248         ubyte num_ce_slots;
 249
 250         /* Slots that are used by currently-bound shaders.
 251          * With CE: It determines which slots are dumped to L2.
 252          *          It doesn't skip uploads to CE RAM.
 253          * Without CE: It determines which slots are uploaded.
 254          */
 255         ubyte first_active_slot;
 256         ubyte num_active_slots;
 257
 258         /* Whether CE is used to upload this descriptor array. */
 259         bool uses_ce;
 260
 261         /* The SGPR index where the 64-bit pointer to the descriptor array will
 262          * be stored. */
 263         ubyte shader_userdata_offset;
 264 };
 265
 266 struct si_sampler_views {
 267         struct pipe_sampler_view        *views[SI_NUM_SAMPLERS];
 268         struct si_sampler_state         *sampler_states[SI_NUM_SAMPLERS];
 269
 270         /* The i-th bit is set if that element is enabled (non-NULL resource). */
 271         unsigned                        enabled_mask;
 272 };
 273
 274 struct si_buffer_resources {
 275         struct pipe_resource            **buffers; /* this has num_buffers elements */
 276
 277         enum radeon_bo_usage            shader_usage:4; /* READ, WRITE, or READWRITE */
 278         enum radeon_bo_usage            shader_usage_constbuf:4;
 279         enum radeon_bo_priority         priority:6;
 280         enum radeon_bo_priority         priority_constbuf:6;
 281
 282         /* The i-th bit is set if that element is enabled (non-NULL resource). */
 283         unsigned                        enabled_mask;
 284 };
 285
 286 #define si_pm4_block_idx(member) \
 287         (offsetof(union si_state, named.member) / sizeof(struct si_pm4_state *))
 288
 289 #define si_pm4_state_changed(sctx, member) \
 290         ((sctx)->queued.named.member != (sctx)->emitted.named.member)
 291
 292 #define si_pm4_bind_state(sctx, member, value) \
 293         do { \
 294                 (sctx)->queued.named.member = (value); \
 295                 (sctx)->dirty_states |= 1 << si_pm4_block_idx(member); \
 296         } while(0)
 297
 298 #define si_pm4_delete_state(sctx, member, value) \
 299         do { \
 300                 if ((sctx)->queued.named.member == (value)) { \
 301                         (sctx)->queued.named.member = NULL; \
 302                 } \
 303                 si_pm4_free_state(sctx, (struct si_pm4_state *)(value), \
 304                                   si_pm4_block_idx(member)); \
 305         } while(0)
 306
 307 /* si_descriptors.c */
 308 void si_ce_save_all_descriptors_at_ib_end(struct si_context* sctx);
 309 void si_ce_restore_all_descriptors_at_ib_start(struct si_context *sctx);
 310 void si_ce_enable_loads(struct radeon_winsys_cs *ib);
 311 void si_set_mutable_tex_desc_fields(struct si_screen *sscreen,
 312                                     struct r600_texture *tex,
 313                                     const struct legacy_surf_level *base_level_info,
 314                                     unsigned base_level, unsigned first_level,
 315                                     unsigned block_width, bool is_stencil,
 316                                     uint32_t *state);
 317 void si_get_pipe_constant_buffer(struct si_context *sctx, uint shader,
 318                                  uint slot, struct pipe_constant_buffer *cbuf);
 319 void si_get_shader_buffers(struct si_context *sctx,
 320                            enum pipe_shader_type shader,
 321                            uint start_slot, uint count,
 322                            struct pipe_shader_buffer *sbuf);
 323 void si_set_ring_buffer(struct pipe_context *ctx, uint slot,
 324                         struct pipe_resource *buffer,
 325                         unsigned stride, unsigned num_records,
 326                         bool add_tid, bool swizzle,
 327                         unsigned element_size, unsigned index_stride, uint64_t offset);
 328 void si_init_all_descriptors(struct si_context *sctx);
 329 bool si_upload_vertex_buffer_descriptors(struct si_context *sctx);
 330 bool si_upload_graphics_shader_descriptors(struct si_context *sctx);
 331 bool si_upload_compute_shader_descriptors(struct si_context *sctx);
 332 void si_release_all_descriptors(struct si_context *sctx);
 333 void si_all_descriptors_begin_new_cs(struct si_context *sctx);
 334 void si_all_resident_buffers_begin_new_cs(struct si_context *sctx);
 335 void si_upload_const_buffer(struct si_context *sctx, struct r600_resource **rbuffer,
 336                             const uint8_t *ptr, unsigned size, uint32_t *const_offset);
 337 void si_update_all_texture_descriptors(struct si_context *sctx);
 338 void si_shader_change_notify(struct si_context *sctx);
 339 void si_update_needs_color_decompress_masks(struct si_context *sctx);
 340 void si_emit_graphics_shader_userdata(struct si_context *sctx,
 341                                       struct r600_atom *atom);
 342 void si_emit_compute_shader_userdata(struct si_context *sctx);
 343 void si_set_rw_buffer(struct si_context *sctx,
 344                       uint slot, const struct pipe_constant_buffer *input);
 345 void si_set_active_descriptors(struct si_context *sctx, unsigned desc_idx,
 346                                uint64_t new_active_mask);
 347 void si_set_active_descriptors_for_shader(struct si_context *sctx,
 348                                           struct si_shader_selector *sel);
 349 bool si_bindless_descriptor_can_reclaim_slab(void *priv,
 350                                              struct pb_slab_entry *entry);
 351 struct pb_slab *si_bindless_descriptor_slab_alloc(void *priv, unsigned heap,
 352                                                   unsigned entry_size,
 353                                                   unsigned group_index);
 354 void si_bindless_descriptor_slab_free(void *priv, struct pb_slab *pslab);
 355
 356 /* si_state.c */
 357 struct si_shader_selector;
 358
 359 void si_init_atom(struct si_context *sctx, struct r600_atom *atom,
 360                   struct r600_atom **list_elem,
 361                   void (*emit_func)(struct si_context *ctx, struct r600_atom *state));
 362 void si_init_state_functions(struct si_context *sctx);
 363 void si_init_screen_state_functions(struct si_screen *sscreen);
 364 void
 365 si_make_buffer_descriptor(struct si_screen *screen, struct r600_resource *buf,
 366                           enum pipe_format format,
 367                           unsigned offset, unsigned size,
 368                           uint32_t *state);
 369 void
 370 si_make_texture_descriptor(struct si_screen *screen,
 371                            struct r600_texture *tex,
 372                            bool sampler,
 373                            enum pipe_texture_target target,
 374                            enum pipe_format pipe_format,
 375                            const unsigned char state_swizzle[4],
 376                            unsigned first_level, unsigned last_level,
 377                            unsigned first_layer, unsigned last_layer,
 378                            unsigned width, unsigned height, unsigned depth,
 379                            uint32_t *state,
 380                            uint32_t *fmask_state);
 381 struct pipe_sampler_view *
 382 si_create_sampler_view_custom(struct pipe_context *ctx,
 383                               struct pipe_resource *texture,
 384                               const struct pipe_sampler_view *state,
 385                               unsigned width0, unsigned height0,
 386                               unsigned force_level);
 387 void si_update_fb_dirtiness_after_rendering(struct si_context *sctx);
 388
 389 /* si_state_shader.c */
 390 bool si_update_shaders(struct si_context *sctx);
 391 void si_init_shader_functions(struct si_context *sctx);
 392 bool si_init_shader_cache(struct si_screen *sscreen);
 393 void si_destroy_shader_cache(struct si_screen *sscreen);
 394 void si_init_shader_selector_async(void *job, int thread_index);
 395 void si_get_active_slot_masks(const struct tgsi_shader_info *info,
 396                               uint32_t *const_and_shader_buffers,
 397                               uint64_t *samplers_and_images);
 398
 399 /* si_state_draw.c */
 400 void si_init_ia_multi_vgt_param_table(struct si_context *sctx);
 401 void si_emit_cache_flush(struct si_context *sctx);
 402 void si_ce_pre_draw_synchronization(struct si_context *sctx);
 403 void si_ce_post_draw_synchronization(struct si_context *sctx);
 404 void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *dinfo);
 405 void si_trace_emit(struct si_context *sctx);
 406
 407
 408 static inline unsigned
 409 si_tile_mode_index(struct r600_texture *rtex, unsigned level, bool stencil)
 410 {
 411         if (stencil)
 412                 return rtex->surface.u.legacy.stencil_tiling_index[level];
 413         else
 414                 return rtex->surface.u.legacy.tiling_index[level];
 415 }
 416
 417 static inline unsigned si_get_constbuf_slot(unsigned slot)
 418 {
 419         /* Constant buffers are in slots [16..31], ascending */
 420         return SI_NUM_SHADER_BUFFERS + slot;
 421 }
 422
 423 static inline unsigned si_get_shaderbuf_slot(unsigned slot)
 424 {
 425         /* shader buffers are in slots [15..0], descending */
 426         return SI_NUM_SHADER_BUFFERS - 1 - slot;
 427 }
 428
 429 static inline unsigned si_get_sampler_slot(unsigned slot)
 430 {
 431         /* samplers are in slots [8..39], ascending */
 432         return SI_NUM_IMAGES / 2 + slot;
 433 }
 434
 435 static inline unsigned si_get_image_slot(unsigned slot)
 436 {
 437         /* images are in slots [15..0] (sampler slots [7..0]), descending */
 438         return SI_NUM_IMAGES - 1 - slot;
 439 }
 440
 441 #endif