2 * Copyright 2017 Advanced Micro Devices, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
25 /* This file handles register programming of primitive binning. */
27 #include "si_build_pm4.h"
34 struct si_bin_size_map
{
40 typedef struct si_bin_size_map si_bin_size_subtable
[3][10];
42 /* Find the bin size where sum is >= table[i].start and < table[i + 1].start. */
43 static struct uvec2
si_find_bin_size(struct si_screen
*sscreen
,
44 const si_bin_size_subtable table
[],
47 unsigned log_num_rb_per_se
=
48 util_logbase2_ceil(sscreen
->info
.num_render_backends
/
49 sscreen
->info
.max_se
);
50 unsigned log_num_se
= util_logbase2_ceil(sscreen
->info
.max_se
);
53 /* Get the chip-specific subtable. */
54 const struct si_bin_size_map
*subtable
=
55 &table
[log_num_rb_per_se
][log_num_se
][0];
57 for (i
= 0; subtable
[i
].bin_size_x
!= 0; i
++) {
58 if (sum
>= subtable
[i
].start
&& sum
< subtable
[i
+ 1].start
)
62 struct uvec2 size
= {subtable
[i
].bin_size_x
, subtable
[i
].bin_size_y
};
66 static struct uvec2
si_get_color_bin_size(struct si_context
*sctx
,
67 unsigned cb_target_enabled_4bit
)
69 unsigned num_fragments
= sctx
->framebuffer
.nr_color_samples
;
72 /* Compute the sum of all Bpp. */
73 for (unsigned i
= 0; i
< sctx
->framebuffer
.state
.nr_cbufs
; i
++) {
74 if (!(cb_target_enabled_4bit
& (0xf << (i
* 4))))
77 struct si_texture
*tex
=
78 (struct si_texture
*)sctx
->framebuffer
.state
.cbufs
[i
]->texture
;
79 sum
+= tex
->surface
.bpe
;
82 /* Multiply the sum by some function of the number of samples. */
83 if (num_fragments
>= 2) {
84 if (si_get_ps_iter_samples(sctx
) >= 2)
90 static const si_bin_size_subtable table
[] = {
94 /* One shader engine */
102 /* Two shader engines */
110 /* Four shader engines */
120 /* One shader engine */
128 /* Two shader engines */
136 /* Four shader engines */
148 /* One shader engine */
157 /* Two shader engines */
167 /* Four shader engines */
179 return si_find_bin_size(sctx
->screen
, table
, sum
);
182 static struct uvec2
si_get_depth_bin_size(struct si_context
*sctx
)
184 struct si_state_dsa
*dsa
= sctx
->queued
.named
.dsa
;
186 if (!sctx
->framebuffer
.state
.zsbuf
||
187 (!dsa
->depth_enabled
&& !dsa
->stencil_enabled
)) {
188 /* Return the max size. */
189 struct uvec2 size
= {512, 512};
193 struct si_texture
*tex
=
194 (struct si_texture
*)sctx
->framebuffer
.state
.zsbuf
->texture
;
195 unsigned depth_coeff
= dsa
->depth_enabled
? 5 : 0;
196 unsigned stencil_coeff
= tex
->surface
.has_stencil
&&
197 dsa
->stencil_enabled
? 1 : 0;
198 unsigned sum
= 4 * (depth_coeff
+ stencil_coeff
) *
199 MAX2(tex
->buffer
.b
.b
.nr_samples
, 1);
201 static const si_bin_size_subtable table
[] = {
214 // Two shader engines
224 // Four shader engines
247 // Two shader engines
258 // Four shader engines
283 // Two shader engines
295 // Four shader engines
308 return si_find_bin_size(sctx
->screen
, table
, sum
);
311 static void gfx10_get_bin_sizes(struct si_context
*sctx
,
312 unsigned cb_target_enabled_4bit
,
313 struct uvec2
*color_bin_size
,
314 struct uvec2
*depth_bin_size
)
316 unsigned num_sdp_interfaces
= 0;
318 switch (sctx
->family
) {
321 num_sdp_interfaces
= 16;
324 num_sdp_interfaces
= 8;
330 const unsigned ZsTagSize
= 64;
331 const unsigned ZsNumTags
= 312;
332 const unsigned CcTagSize
= 1024;
333 const unsigned CcReadTags
= 31;
334 const unsigned FcTagSize
= 256;
335 const unsigned FcReadTags
= 44;
337 const unsigned num_rbs
= sctx
->screen
->info
.num_render_backends
;
338 const unsigned num_pipes
= MAX2(num_rbs
, num_sdp_interfaces
);
340 const unsigned depthBinSizeTagPart
= ((ZsNumTags
* num_rbs
/ num_pipes
) * (ZsTagSize
* num_pipes
));
341 const unsigned colorBinSizeTagPart
= ((CcReadTags
* num_rbs
/ num_pipes
) * (CcTagSize
* num_pipes
));
342 const unsigned fmaskBinSizeTagPart
= ((FcReadTags
* num_rbs
/ num_pipes
) * (FcTagSize
* num_pipes
));
344 const unsigned minBinSizeX
= 128;
345 const unsigned minBinSizeY
= 64;
347 const unsigned num_fragments
= sctx
->framebuffer
.nr_color_samples
;
348 const unsigned num_samples
= sctx
->framebuffer
.nr_samples
;
349 const bool ps_iter_sample
= si_get_ps_iter_samples(sctx
) >= 2;
351 /* Calculate cColor and cFmask(if applicable) */
354 bool has_fmask
= false;
356 for (unsigned i
= 0; i
< sctx
->framebuffer
.state
.nr_cbufs
; i
++) {
357 if (!sctx
->framebuffer
.state
.cbufs
[i
])
360 struct si_texture
*tex
=
361 (struct si_texture
*)sctx
->framebuffer
.state
.cbufs
[i
]->texture
;
362 const unsigned mmrt
=
363 num_fragments
== 1 ? 1 : (ps_iter_sample
? num_fragments
: 2);
365 cColor
+= tex
->surface
.bpe
* mmrt
;
366 if (num_samples
>= 2 /* if FMASK is bound */) {
367 const unsigned fragmentsLog2
= util_logbase2(num_fragments
);
368 const unsigned samplesLog2
= util_logbase2(num_samples
);
370 static const unsigned cFmaskMrt
[4 /* fragments */][5 /* samples */] = {
371 { 0, 1, 1, 1, 2 }, /* fragments = 1 */
372 { 0, 1, 1, 2, 4 }, /* fragments = 2 */
373 { 0, 1, 1, 4, 8 }, /* fragments = 4 */
374 { 0, 1, 2, 4, 8 } /* fragments = 8 */
376 cFmask
+= cFmaskMrt
[fragmentsLog2
][samplesLog2
];
380 cColor
= MAX2(cColor
, 1u);
382 const unsigned colorLog2Pixels
= util_logbase2(colorBinSizeTagPart
/ cColor
);
383 const unsigned colorBinSizeX
= 1 << ((colorLog2Pixels
+ 1) / 2); /* round up width */
384 const unsigned colorBinSizeY
= 1 << (colorLog2Pixels
/ 2); /* round down height */
386 unsigned binSizeX
= colorBinSizeX
;
387 unsigned binSizeY
= colorBinSizeY
;
390 cFmask
= MAX2(cFmask
, 1u);
392 const unsigned fmaskLog2Pixels
= util_logbase2(fmaskBinSizeTagPart
/ cFmask
);
393 const unsigned fmaskBinSizeX
= 1 << ((fmaskLog2Pixels
+ 1) / 2); /* round up width */
394 const unsigned fmaskBinSizeY
= 1 << (fmaskLog2Pixels
/ 2); /* round down height */
396 /* use the smaller of the Color vs. Fmask bin sizes */
397 if (fmaskLog2Pixels
< colorLog2Pixels
) {
398 binSizeX
= fmaskBinSizeX
;
399 binSizeY
= fmaskBinSizeY
;
403 /* Return size adjusted for minimum bin size */
404 color_bin_size
->x
= MAX2(binSizeX
, minBinSizeX
);
405 color_bin_size
->y
= MAX2(binSizeY
, minBinSizeY
);
407 if (!sctx
->framebuffer
.state
.zsbuf
) {
408 /* Set to max sizes when no depth buffer is bound. */
409 depth_bin_size
->x
= 512;
410 depth_bin_size
->y
= 512;
412 struct si_texture
*zstex
= (struct si_texture
*)sctx
->framebuffer
.state
.zsbuf
->texture
;
413 struct si_state_dsa
*dsa
= sctx
->queued
.named
.dsa
;
415 const unsigned cPerDepthSample
= dsa
->depth_enabled
? 5 : 0;
416 const unsigned cPerStencilSample
= dsa
->stencil_enabled
? 1 : 0;
417 const unsigned cDepth
= (cPerDepthSample
+ cPerStencilSample
) *
418 MAX2(zstex
->buffer
.b
.b
.nr_samples
, 1);
420 const unsigned depthLog2Pixels
= util_logbase2(depthBinSizeTagPart
/ MAX2(cDepth
, 1u));
421 unsigned depthBinSizeX
= 1 << ((depthLog2Pixels
+ 1) / 2);
422 unsigned depthBinSizeY
= 1 << (depthLog2Pixels
/ 2);
424 depth_bin_size
->x
= MAX2(depthBinSizeX
, minBinSizeX
);
425 depth_bin_size
->y
= MAX2(depthBinSizeY
, minBinSizeY
);
429 static void si_emit_dpbb_disable(struct si_context
*sctx
)
431 unsigned initial_cdw
= sctx
->gfx_cs
->current
.cdw
;
433 if (sctx
->chip_class
>= GFX10
) {
434 struct uvec2 bin_size
= {};
435 struct uvec2 bin_size_extend
= {};
438 bin_size
.y
= sctx
->framebuffer
.min_bytes_per_pixel
<= 4 ? 128 : 64;
440 if (bin_size
.x
>= 32)
441 bin_size_extend
.x
= util_logbase2(bin_size
.x
) - 5;
442 if (bin_size
.y
>= 32)
443 bin_size_extend
.y
= util_logbase2(bin_size
.y
) - 5;
445 radeon_opt_set_context_reg(sctx
, R_028C44_PA_SC_BINNER_CNTL_0
,
446 SI_TRACKED_PA_SC_BINNER_CNTL_0
,
447 S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_NEW_SC
) |
448 S_028C44_BIN_SIZE_X(bin_size
.x
== 16) |
449 S_028C44_BIN_SIZE_Y(bin_size
.y
== 16) |
450 S_028C44_BIN_SIZE_X_EXTEND(bin_size_extend
.x
) |
451 S_028C44_BIN_SIZE_Y_EXTEND(bin_size_extend
.y
) |
452 S_028C44_DISABLE_START_OF_PRIM(1) |
453 S_028C44_FLUSH_ON_BINNING_TRANSITION(sctx
->last_binning_enabled
!= 0));
455 radeon_opt_set_context_reg(sctx
, R_028C44_PA_SC_BINNER_CNTL_0
,
456 SI_TRACKED_PA_SC_BINNER_CNTL_0
,
457 S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_LEGACY_SC
) |
458 S_028C44_DISABLE_START_OF_PRIM(1) |
459 S_028C44_FLUSH_ON_BINNING_TRANSITION((sctx
->family
== CHIP_VEGA12
||
460 sctx
->family
== CHIP_VEGA20
||
461 sctx
->family
>= CHIP_RAVEN2
) &&
462 sctx
->last_binning_enabled
!= 0));
465 unsigned db_dfsm_control
= sctx
->chip_class
>= GFX10
? R_028038_DB_DFSM_CONTROL
466 : R_028060_DB_DFSM_CONTROL
;
467 radeon_opt_set_context_reg(sctx
, db_dfsm_control
,
468 SI_TRACKED_DB_DFSM_CONTROL
,
469 S_028060_PUNCHOUT_MODE(V_028060_FORCE_OFF
) |
470 S_028060_POPS_DRAIN_PS_ON_OVERLAP(1));
471 if (initial_cdw
!= sctx
->gfx_cs
->current
.cdw
)
472 sctx
->context_roll
= true;
474 sctx
->last_binning_enabled
= false;
477 void si_emit_dpbb_state(struct si_context
*sctx
)
479 struct si_screen
*sscreen
= sctx
->screen
;
480 struct si_state_blend
*blend
= sctx
->queued
.named
.blend
;
481 struct si_state_dsa
*dsa
= sctx
->queued
.named
.dsa
;
482 unsigned db_shader_control
= sctx
->ps_db_shader_control
;
484 assert(sctx
->chip_class
>= GFX9
);
486 if (!sscreen
->dpbb_allowed
|| sctx
->dpbb_force_off
) {
487 si_emit_dpbb_disable(sctx
);
491 bool ps_can_kill
= G_02880C_KILL_ENABLE(db_shader_control
) ||
492 G_02880C_MASK_EXPORT_ENABLE(db_shader_control
) ||
493 G_02880C_COVERAGE_TO_MASK_ENABLE(db_shader_control
) ||
494 blend
->alpha_to_coverage
;
496 bool db_can_reject_z_trivially
=
497 !G_02880C_Z_EXPORT_ENABLE(db_shader_control
) ||
498 G_02880C_CONSERVATIVE_Z_EXPORT(db_shader_control
) ||
499 G_02880C_DEPTH_BEFORE_SHADER(db_shader_control
);
501 /* Disable DPBB when it's believed to be inefficient. */
503 db_can_reject_z_trivially
&&
504 sctx
->framebuffer
.state
.zsbuf
&&
506 si_emit_dpbb_disable(sctx
);
510 /* Compute the bin size. */
511 /* TODO: We could also look at enabled pixel shader outputs. */
512 unsigned cb_target_enabled_4bit
= sctx
->framebuffer
.colorbuf_enabled_4bit
&
513 blend
->cb_target_enabled_4bit
;
514 struct uvec2 color_bin_size
, depth_bin_size
;
516 if (sctx
->chip_class
>= GFX10
) {
517 gfx10_get_bin_sizes(sctx
, cb_target_enabled_4bit
,
518 &color_bin_size
, &depth_bin_size
);
520 color_bin_size
= si_get_color_bin_size(sctx
, cb_target_enabled_4bit
);
521 depth_bin_size
= si_get_depth_bin_size(sctx
);
524 unsigned color_area
= color_bin_size
.x
* color_bin_size
.y
;
525 unsigned depth_area
= depth_bin_size
.x
* depth_bin_size
.y
;
527 struct uvec2 bin_size
= color_area
< depth_area
? color_bin_size
530 if (!bin_size
.x
|| !bin_size
.y
) {
531 si_emit_dpbb_disable(sctx
);
535 /* Enable DFSM if it's preferred. */
536 unsigned punchout_mode
= V_028060_FORCE_OFF
;
537 bool disable_start_of_prim
= true;
538 bool zs_eqaa_dfsm_bug
= sctx
->chip_class
== GFX9
&&
539 sctx
->framebuffer
.state
.zsbuf
&&
540 sctx
->framebuffer
.nr_samples
!=
541 MAX2(1, sctx
->framebuffer
.state
.zsbuf
->texture
->nr_samples
);
543 if (sscreen
->dfsm_allowed
&&
545 cb_target_enabled_4bit
&&
546 !G_02880C_KILL_ENABLE(db_shader_control
) &&
547 /* These two also imply that DFSM is disabled when PS writes to memory. */
548 !G_02880C_EXEC_ON_HIER_FAIL(db_shader_control
) &&
549 !G_02880C_EXEC_ON_NOOP(db_shader_control
) &&
550 G_02880C_Z_ORDER(db_shader_control
) == V_02880C_EARLY_Z_THEN_LATE_Z
) {
551 punchout_mode
= V_028060_AUTO
;
552 disable_start_of_prim
= (cb_target_enabled_4bit
&
553 blend
->blend_enable_4bit
) != 0;
556 /* Tunable parameters. Also test with DFSM enabled/disabled. */
557 unsigned context_states_per_bin
; /* allowed range: [1, 6] */
558 unsigned persistent_states_per_bin
; /* allowed range: [1, 32] */
559 unsigned fpovs_per_batch
; /* allowed range: [0, 255], 0 = unlimited */
561 /* Tuned for Raven. Vega might need different values. */
562 if (sscreen
->info
.has_dedicated_vram
) {
563 context_states_per_bin
= 1;
564 persistent_states_per_bin
= 1;
566 /* This is a workaround for:
567 * https://bugs.freedesktop.org/show_bug.cgi?id=110214
568 * (an alternative is to insert manual BATCH_BREAK event when
569 * a context_roll is detected). */
570 context_states_per_bin
= sctx
->screen
->info
.has_gfx9_scissor_bug
? 1 : 6;
571 /* Using 32 here can cause GPU hangs on RAVEN1 */
572 persistent_states_per_bin
= 16;
574 fpovs_per_batch
= 63;
576 /* Emit registers. */
577 struct uvec2 bin_size_extend
= {};
578 if (bin_size
.x
>= 32)
579 bin_size_extend
.x
= util_logbase2(bin_size
.x
) - 5;
580 if (bin_size
.y
>= 32)
581 bin_size_extend
.y
= util_logbase2(bin_size
.y
) - 5;
583 unsigned initial_cdw
= sctx
->gfx_cs
->current
.cdw
;
584 radeon_opt_set_context_reg(
585 sctx
, R_028C44_PA_SC_BINNER_CNTL_0
,
586 SI_TRACKED_PA_SC_BINNER_CNTL_0
,
587 S_028C44_BINNING_MODE(V_028C44_BINNING_ALLOWED
) |
588 S_028C44_BIN_SIZE_X(bin_size
.x
== 16) |
589 S_028C44_BIN_SIZE_Y(bin_size
.y
== 16) |
590 S_028C44_BIN_SIZE_X_EXTEND(bin_size_extend
.x
) |
591 S_028C44_BIN_SIZE_Y_EXTEND(bin_size_extend
.y
) |
592 S_028C44_CONTEXT_STATES_PER_BIN(context_states_per_bin
- 1) |
593 S_028C44_PERSISTENT_STATES_PER_BIN(persistent_states_per_bin
- 1) |
594 S_028C44_DISABLE_START_OF_PRIM(disable_start_of_prim
) |
595 S_028C44_FPOVS_PER_BATCH(fpovs_per_batch
) |
596 S_028C44_OPTIMAL_BIN_SELECTION(1) |
597 S_028C44_FLUSH_ON_BINNING_TRANSITION((sctx
->family
== CHIP_VEGA12
||
598 sctx
->family
== CHIP_VEGA20
||
599 sctx
->family
>= CHIP_RAVEN2
) &&
600 sctx
->last_binning_enabled
!= 1));
602 unsigned db_dfsm_control
= sctx
->chip_class
>= GFX10
? R_028038_DB_DFSM_CONTROL
603 : R_028060_DB_DFSM_CONTROL
;
604 radeon_opt_set_context_reg(sctx
, db_dfsm_control
,
605 SI_TRACKED_DB_DFSM_CONTROL
,
606 S_028060_PUNCHOUT_MODE(punchout_mode
) |
607 S_028060_POPS_DRAIN_PS_ON_OVERLAP(1));
608 if (initial_cdw
!= sctx
->gfx_cs
->current
.cdw
)
609 sctx
->context_roll
= true;
611 sctx
->last_binning_enabled
= true;