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25 /* This file handles register programming of primitive binning. */
30 #include "radeon/r600_cs.h"
36 struct si_bin_size_map
{
42 typedef struct si_bin_size_map si_bin_size_subtable
[3][9];
44 /* Find the bin size where sum is >= table[i].start and < table[i + 1].start. */
45 static struct uvec2
si_find_bin_size(struct si_screen
*sscreen
,
46 const si_bin_size_subtable table
[],
49 unsigned log_num_rb_per_se
=
50 util_logbase2_ceil(sscreen
->info
.num_render_backends
/
51 sscreen
->info
.max_se
);
52 unsigned log_num_se
= util_logbase2_ceil(sscreen
->info
.max_se
);
55 /* Get the chip-specific subtable. */
56 const struct si_bin_size_map
*subtable
=
57 &table
[log_num_rb_per_se
][log_num_se
][0];
59 for (i
= 0; subtable
[i
].start
!= UINT_MAX
; i
++) {
60 if (sum
>= subtable
[i
].start
&& sum
< subtable
[i
+ 1].start
)
64 struct uvec2 size
= {subtable
[i
].bin_size_x
, subtable
[i
].bin_size_y
};
68 static struct uvec2
si_get_color_bin_size(struct si_context
*sctx
,
69 unsigned cb_target_enabled_4bit
)
71 unsigned nr_samples
= sctx
->framebuffer
.nr_samples
;
74 /* Compute the sum of all Bpp. */
75 for (unsigned i
= 0; i
< sctx
->framebuffer
.state
.nr_cbufs
; i
++) {
76 if (!(cb_target_enabled_4bit
& (0xf << (i
* 4))))
79 struct r600_texture
*rtex
=
80 (struct r600_texture
*)sctx
->framebuffer
.state
.cbufs
[i
]->texture
;
81 sum
+= rtex
->surface
.bpe
;
84 /* Multiply the sum by some function of the number of samples. */
85 if (nr_samples
>= 2) {
86 if (si_get_ps_iter_samples(sctx
) >= 2)
92 static const si_bin_size_subtable table
[] = {
96 /* One shader engine */
105 /* Two shader engines */
114 /* Four shader engines */
125 /* One shader engine */
134 /* Two shader engines */
143 /* Four shader engines */
156 /* One shader engine */
166 /* Two shader engines */
177 /* Four shader engines */
190 return si_find_bin_size(sctx
->screen
, table
, sum
);
193 static struct uvec2
si_get_depth_bin_size(struct si_context
*sctx
)
195 struct si_state_dsa
*dsa
= sctx
->queued
.named
.dsa
;
197 if (!sctx
->framebuffer
.state
.zsbuf
||
198 (!dsa
->depth_enabled
&& !dsa
->stencil_enabled
)) {
199 /* Return the max size. */
200 struct uvec2 size
= {512, 512};
204 struct r600_texture
*rtex
=
205 (struct r600_texture
*)sctx
->framebuffer
.state
.zsbuf
->texture
;
206 unsigned depth_coeff
= dsa
->depth_enabled
? 5 : 0;
207 unsigned stencil_coeff
= rtex
->surface
.has_stencil
&&
208 dsa
->stencil_enabled
? 1 : 0;
209 unsigned sum
= 4 * (depth_coeff
+ stencil_coeff
) *
210 sctx
->framebuffer
.nr_samples
;
212 static const si_bin_size_subtable table
[] = {
226 // Two shader engines
237 // Four shader engines
262 // Two shader engines
274 // Four shader engines
300 // Two shader engines
312 // Four shader engines
325 return si_find_bin_size(sctx
->screen
, table
, sum
);
328 static void si_emit_dpbb_disable(struct si_context
*sctx
)
330 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx_cs
;
332 radeon_set_context_reg(cs
, R_028C44_PA_SC_BINNER_CNTL_0
,
333 S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_LEGACY_SC
) |
334 S_028C44_DISABLE_START_OF_PRIM(1));
335 radeon_set_context_reg(cs
, R_028060_DB_DFSM_CONTROL
,
336 S_028060_PUNCHOUT_MODE(V_028060_FORCE_OFF
));
339 void si_emit_dpbb_state(struct si_context
*sctx
, struct r600_atom
*state
)
341 struct si_screen
*sscreen
= sctx
->screen
;
342 struct si_state_blend
*blend
= sctx
->queued
.named
.blend
;
343 struct si_state_dsa
*dsa
= sctx
->queued
.named
.dsa
;
344 unsigned db_shader_control
= sctx
->ps_db_shader_control
;
346 assert(sctx
->b
.chip_class
>= GFX9
);
348 if (!sscreen
->dpbb_allowed
|| !blend
|| !dsa
) {
349 si_emit_dpbb_disable(sctx
);
353 bool ps_can_kill
= G_02880C_KILL_ENABLE(db_shader_control
) ||
354 G_02880C_MASK_EXPORT_ENABLE(db_shader_control
) ||
355 G_02880C_COVERAGE_TO_MASK_ENABLE(db_shader_control
) ||
356 blend
->alpha_to_coverage
;
358 /* This is ported from Vulkan, but it doesn't make much sense to me.
359 * Maybe it's for RE-Z? But Vulkan doesn't use RE-Z. TODO: Clarify this.
361 bool ps_can_reject_z_trivially
=
362 !G_02880C_Z_EXPORT_ENABLE(db_shader_control
) ||
363 G_02880C_CONSERVATIVE_Z_EXPORT(db_shader_control
);
365 /* Disable binning if PS can kill trivially with DB writes.
366 * Ported from Vulkan. (heuristic?)
369 ps_can_reject_z_trivially
&&
370 sctx
->framebuffer
.state
.zsbuf
&&
372 si_emit_dpbb_disable(sctx
);
376 /* Compute the bin size. */
377 /* TODO: We could also look at enabled pixel shader outputs. */
378 unsigned cb_target_enabled_4bit
= sctx
->framebuffer
.colorbuf_enabled_4bit
&
379 blend
->cb_target_enabled_4bit
;
380 struct uvec2 color_bin_size
=
381 si_get_color_bin_size(sctx
, cb_target_enabled_4bit
);
382 struct uvec2 depth_bin_size
= si_get_depth_bin_size(sctx
);
384 unsigned color_area
= color_bin_size
.x
* color_bin_size
.y
;
385 unsigned depth_area
= depth_bin_size
.x
* depth_bin_size
.y
;
387 struct uvec2 bin_size
= color_area
< depth_area
? color_bin_size
390 if (!bin_size
.x
|| !bin_size
.y
) {
391 si_emit_dpbb_disable(sctx
);
395 /* Enable DFSM if it's preferred. */
396 unsigned punchout_mode
= V_028060_FORCE_OFF
;
397 bool disable_start_of_prim
= true;
399 if (sscreen
->dfsm_allowed
&&
400 cb_target_enabled_4bit
&&
401 !G_02880C_KILL_ENABLE(db_shader_control
) &&
402 /* These two also imply that DFSM is disabled when PS writes to memory. */
403 !G_02880C_EXEC_ON_HIER_FAIL(db_shader_control
) &&
404 !G_02880C_EXEC_ON_NOOP(db_shader_control
) &&
405 G_02880C_Z_ORDER(db_shader_control
) == V_02880C_EARLY_Z_THEN_LATE_Z
) {
406 punchout_mode
= V_028060_AUTO
;
407 disable_start_of_prim
= (cb_target_enabled_4bit
&
408 blend
->blend_enable_4bit
) != 0;
411 /* Tunable parameters. Also test with DFSM enabled/disabled. */
412 unsigned context_states_per_bin
; /* allowed range: [0, 5] */
413 unsigned persistent_states_per_bin
; /* allowed range: [0, 31] */
414 unsigned fpovs_per_batch
; /* allowed range: [0, 255], 0 = unlimited */
416 switch (sctx
->b
.family
) {
420 /* Tuned for Raven. Vega might need different values. */
421 context_states_per_bin
= 5;
422 persistent_states_per_bin
= 31;
423 fpovs_per_batch
= 63;
429 /* Emit registers. */
430 struct uvec2 bin_size_extend
= {};
431 if (bin_size
.x
>= 32)
432 bin_size_extend
.x
= util_logbase2(bin_size
.x
) - 5;
433 if (bin_size
.y
>= 32)
434 bin_size_extend
.y
= util_logbase2(bin_size
.y
) - 5;
436 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx_cs
;
437 radeon_set_context_reg(cs
, R_028C44_PA_SC_BINNER_CNTL_0
,
438 S_028C44_BINNING_MODE(V_028C44_BINNING_ALLOWED
) |
439 S_028C44_BIN_SIZE_X(bin_size
.x
== 16) |
440 S_028C44_BIN_SIZE_Y(bin_size
.y
== 16) |
441 S_028C44_BIN_SIZE_X_EXTEND(bin_size_extend
.x
) |
442 S_028C44_BIN_SIZE_Y_EXTEND(bin_size_extend
.y
) |
443 S_028C44_CONTEXT_STATES_PER_BIN(context_states_per_bin
) |
444 S_028C44_PERSISTENT_STATES_PER_BIN(persistent_states_per_bin
) |
445 S_028C44_DISABLE_START_OF_PRIM(disable_start_of_prim
) |
446 S_028C44_FPOVS_PER_BATCH(fpovs_per_batch
) |
447 S_028C44_OPTIMAL_BIN_SELECTION(1));
448 radeon_set_context_reg(cs
, R_028060_DB_DFSM_CONTROL
,
449 S_028060_PUNCHOUT_MODE(punchout_mode
));