2 * Copyright 2017 Advanced Micro Devices, Inc.
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10 * the Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
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22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
25 /* This file handles register programming of primitive binning. */
27 #include "si_build_pm4.h"
34 struct si_bin_size_map
{
40 typedef struct si_bin_size_map si_bin_size_subtable
[3][9];
42 /* Find the bin size where sum is >= table[i].start and < table[i + 1].start. */
43 static struct uvec2
si_find_bin_size(struct si_screen
*sscreen
,
44 const si_bin_size_subtable table
[],
47 unsigned log_num_rb_per_se
=
48 util_logbase2_ceil(sscreen
->info
.num_render_backends
/
49 sscreen
->info
.max_se
);
50 unsigned log_num_se
= util_logbase2_ceil(sscreen
->info
.max_se
);
53 /* Get the chip-specific subtable. */
54 const struct si_bin_size_map
*subtable
=
55 &table
[log_num_rb_per_se
][log_num_se
][0];
57 for (i
= 0; subtable
[i
].start
!= UINT_MAX
; i
++) {
58 if (sum
>= subtable
[i
].start
&& sum
< subtable
[i
+ 1].start
)
62 struct uvec2 size
= {subtable
[i
].bin_size_x
, subtable
[i
].bin_size_y
};
66 static struct uvec2
si_get_color_bin_size(struct si_context
*sctx
,
67 unsigned cb_target_enabled_4bit
)
69 unsigned nr_samples
= sctx
->framebuffer
.nr_samples
;
72 /* Compute the sum of all Bpp. */
73 for (unsigned i
= 0; i
< sctx
->framebuffer
.state
.nr_cbufs
; i
++) {
74 if (!(cb_target_enabled_4bit
& (0xf << (i
* 4))))
77 struct r600_texture
*rtex
=
78 (struct r600_texture
*)sctx
->framebuffer
.state
.cbufs
[i
]->texture
;
79 sum
+= rtex
->surface
.bpe
;
82 /* Multiply the sum by some function of the number of samples. */
83 if (nr_samples
>= 2) {
84 if (si_get_ps_iter_samples(sctx
) >= 2)
90 static const si_bin_size_subtable table
[] = {
94 /* One shader engine */
103 /* Two shader engines */
112 /* Four shader engines */
123 /* One shader engine */
132 /* Two shader engines */
141 /* Four shader engines */
154 /* One shader engine */
164 /* Two shader engines */
175 /* Four shader engines */
188 return si_find_bin_size(sctx
->screen
, table
, sum
);
191 static struct uvec2
si_get_depth_bin_size(struct si_context
*sctx
)
193 struct si_state_dsa
*dsa
= sctx
->queued
.named
.dsa
;
195 if (!sctx
->framebuffer
.state
.zsbuf
||
196 (!dsa
->depth_enabled
&& !dsa
->stencil_enabled
)) {
197 /* Return the max size. */
198 struct uvec2 size
= {512, 512};
202 struct r600_texture
*rtex
=
203 (struct r600_texture
*)sctx
->framebuffer
.state
.zsbuf
->texture
;
204 unsigned depth_coeff
= dsa
->depth_enabled
? 5 : 0;
205 unsigned stencil_coeff
= rtex
->surface
.has_stencil
&&
206 dsa
->stencil_enabled
? 1 : 0;
207 unsigned sum
= 4 * (depth_coeff
+ stencil_coeff
) *
208 sctx
->framebuffer
.nr_samples
;
210 static const si_bin_size_subtable table
[] = {
224 // Two shader engines
235 // Four shader engines
260 // Two shader engines
272 // Four shader engines
298 // Two shader engines
310 // Four shader engines
323 return si_find_bin_size(sctx
->screen
, table
, sum
);
326 static void si_emit_dpbb_disable(struct si_context
*sctx
)
328 struct radeon_winsys_cs
*cs
= sctx
->gfx_cs
;
330 radeon_set_context_reg(cs
, R_028C44_PA_SC_BINNER_CNTL_0
,
331 S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_LEGACY_SC
) |
332 S_028C44_DISABLE_START_OF_PRIM(1));
333 radeon_set_context_reg(cs
, R_028060_DB_DFSM_CONTROL
,
334 S_028060_PUNCHOUT_MODE(V_028060_FORCE_OFF
));
337 void si_emit_dpbb_state(struct si_context
*sctx
, struct r600_atom
*state
)
339 struct si_screen
*sscreen
= sctx
->screen
;
340 struct si_state_blend
*blend
= sctx
->queued
.named
.blend
;
341 struct si_state_dsa
*dsa
= sctx
->queued
.named
.dsa
;
342 unsigned db_shader_control
= sctx
->ps_db_shader_control
;
344 assert(sctx
->chip_class
>= GFX9
);
346 if (!sscreen
->dpbb_allowed
|| !blend
|| !dsa
) {
347 si_emit_dpbb_disable(sctx
);
351 bool ps_can_kill
= G_02880C_KILL_ENABLE(db_shader_control
) ||
352 G_02880C_MASK_EXPORT_ENABLE(db_shader_control
) ||
353 G_02880C_COVERAGE_TO_MASK_ENABLE(db_shader_control
) ||
354 blend
->alpha_to_coverage
;
356 /* This is ported from Vulkan, but it doesn't make much sense to me.
357 * Maybe it's for RE-Z? But Vulkan doesn't use RE-Z. TODO: Clarify this.
359 bool ps_can_reject_z_trivially
=
360 !G_02880C_Z_EXPORT_ENABLE(db_shader_control
) ||
361 G_02880C_CONSERVATIVE_Z_EXPORT(db_shader_control
);
363 /* Disable binning if PS can kill trivially with DB writes.
364 * Ported from Vulkan. (heuristic?)
367 ps_can_reject_z_trivially
&&
368 sctx
->framebuffer
.state
.zsbuf
&&
370 si_emit_dpbb_disable(sctx
);
374 /* Compute the bin size. */
375 /* TODO: We could also look at enabled pixel shader outputs. */
376 unsigned cb_target_enabled_4bit
= sctx
->framebuffer
.colorbuf_enabled_4bit
&
377 blend
->cb_target_enabled_4bit
;
378 struct uvec2 color_bin_size
=
379 si_get_color_bin_size(sctx
, cb_target_enabled_4bit
);
380 struct uvec2 depth_bin_size
= si_get_depth_bin_size(sctx
);
382 unsigned color_area
= color_bin_size
.x
* color_bin_size
.y
;
383 unsigned depth_area
= depth_bin_size
.x
* depth_bin_size
.y
;
385 struct uvec2 bin_size
= color_area
< depth_area
? color_bin_size
388 if (!bin_size
.x
|| !bin_size
.y
) {
389 si_emit_dpbb_disable(sctx
);
393 /* Enable DFSM if it's preferred. */
394 unsigned punchout_mode
= V_028060_FORCE_OFF
;
395 bool disable_start_of_prim
= true;
397 if (sscreen
->dfsm_allowed
&&
398 cb_target_enabled_4bit
&&
399 !G_02880C_KILL_ENABLE(db_shader_control
) &&
400 /* These two also imply that DFSM is disabled when PS writes to memory. */
401 !G_02880C_EXEC_ON_HIER_FAIL(db_shader_control
) &&
402 !G_02880C_EXEC_ON_NOOP(db_shader_control
) &&
403 G_02880C_Z_ORDER(db_shader_control
) == V_02880C_EARLY_Z_THEN_LATE_Z
) {
404 punchout_mode
= V_028060_AUTO
;
405 disable_start_of_prim
= (cb_target_enabled_4bit
&
406 blend
->blend_enable_4bit
) != 0;
409 /* Tunable parameters. Also test with DFSM enabled/disabled. */
410 unsigned context_states_per_bin
; /* allowed range: [0, 5] */
411 unsigned persistent_states_per_bin
; /* allowed range: [0, 31] */
412 unsigned fpovs_per_batch
; /* allowed range: [0, 255], 0 = unlimited */
414 switch (sctx
->family
) {
418 /* Tuned for Raven. Vega might need different values. */
419 context_states_per_bin
= 5;
420 persistent_states_per_bin
= 31;
421 fpovs_per_batch
= 63;
427 /* Emit registers. */
428 struct uvec2 bin_size_extend
= {};
429 if (bin_size
.x
>= 32)
430 bin_size_extend
.x
= util_logbase2(bin_size
.x
) - 5;
431 if (bin_size
.y
>= 32)
432 bin_size_extend
.y
= util_logbase2(bin_size
.y
) - 5;
434 struct radeon_winsys_cs
*cs
= sctx
->gfx_cs
;
435 radeon_set_context_reg(cs
, R_028C44_PA_SC_BINNER_CNTL_0
,
436 S_028C44_BINNING_MODE(V_028C44_BINNING_ALLOWED
) |
437 S_028C44_BIN_SIZE_X(bin_size
.x
== 16) |
438 S_028C44_BIN_SIZE_Y(bin_size
.y
== 16) |
439 S_028C44_BIN_SIZE_X_EXTEND(bin_size_extend
.x
) |
440 S_028C44_BIN_SIZE_Y_EXTEND(bin_size_extend
.y
) |
441 S_028C44_CONTEXT_STATES_PER_BIN(context_states_per_bin
) |
442 S_028C44_PERSISTENT_STATES_PER_BIN(persistent_states_per_bin
) |
443 S_028C44_DISABLE_START_OF_PRIM(disable_start_of_prim
) |
444 S_028C44_FPOVS_PER_BATCH(fpovs_per_batch
) |
445 S_028C44_OPTIMAL_BIN_SELECTION(1));
446 radeon_set_context_reg(cs
, R_028060_DB_DFSM_CONTROL
,
447 S_028060_PUNCHOUT_MODE(punchout_mode
));