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radeonsi: tune primitive binning for small chips
[mesa.git] / src / gallium / drivers / radeonsi / si_state_binning.c
1 /*
2 * Copyright 2017 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 /* This file handles register programming of primitive binning. */
26
27 #include "si_build_pm4.h"
28 #include "sid.h"
29
30 struct uvec2 {
31 unsigned x, y;
32 };
33
34 struct si_bin_size_map {
35 unsigned start;
36 unsigned bin_size_x;
37 unsigned bin_size_y;
38 };
39
40 typedef struct si_bin_size_map si_bin_size_subtable[3][10];
41
42 /* Find the bin size where sum is >= table[i].start and < table[i + 1].start. */
43 static struct uvec2 si_find_bin_size(struct si_screen *sscreen,
44 const si_bin_size_subtable table[],
45 unsigned sum)
46 {
47 unsigned log_num_rb_per_se =
48 util_logbase2_ceil(sscreen->info.num_render_backends /
49 sscreen->info.max_se);
50 unsigned log_num_se = util_logbase2_ceil(sscreen->info.max_se);
51 unsigned i;
52
53 /* Get the chip-specific subtable. */
54 const struct si_bin_size_map *subtable =
55 &table[log_num_rb_per_se][log_num_se][0];
56
57 for (i = 0; subtable[i].bin_size_x != 0; i++) {
58 if (sum >= subtable[i].start && sum < subtable[i + 1].start)
59 break;
60 }
61
62 struct uvec2 size = {subtable[i].bin_size_x, subtable[i].bin_size_y};
63 return size;
64 }
65
66 static struct uvec2 si_get_color_bin_size(struct si_context *sctx,
67 unsigned cb_target_enabled_4bit)
68 {
69 unsigned num_fragments = sctx->framebuffer.nr_color_samples;
70 unsigned sum = 0;
71
72 /* Compute the sum of all Bpp. */
73 for (unsigned i = 0; i < sctx->framebuffer.state.nr_cbufs; i++) {
74 if (!(cb_target_enabled_4bit & (0xf << (i * 4))))
75 continue;
76
77 struct si_texture *tex =
78 (struct si_texture*)sctx->framebuffer.state.cbufs[i]->texture;
79 sum += tex->surface.bpe;
80 }
81
82 /* Multiply the sum by some function of the number of samples. */
83 if (num_fragments >= 2) {
84 if (si_get_ps_iter_samples(sctx) >= 2)
85 sum *= num_fragments;
86 else
87 sum *= 2;
88 }
89
90 static const si_bin_size_subtable table[] = {
91 {
92 /* One RB / SE */
93 {
94 /* One shader engine */
95 { 0, 128, 128 },
96 { 1, 64, 128 },
97 { 2, 32, 128 },
98 { 3, 16, 128 },
99 { 17, 0, 0 },
100 },
101 {
102 /* Two shader engines */
103 { 0, 128, 128 },
104 { 2, 64, 128 },
105 { 3, 32, 128 },
106 { 5, 16, 128 },
107 { 17, 0, 0 },
108 },
109 {
110 /* Four shader engines */
111 { 0, 128, 128 },
112 { 3, 64, 128 },
113 { 5, 16, 128 },
114 { 17, 0, 0 },
115 },
116 },
117 {
118 /* Two RB / SE */
119 {
120 /* One shader engine */
121 { 0, 128, 128 },
122 { 2, 64, 128 },
123 { 3, 32, 128 },
124 { 9, 16, 128 },
125 { 33, 0, 0 },
126 },
127 {
128 /* Two shader engines */
129 { 0, 128, 128 },
130 { 3, 64, 128 },
131 { 5, 32, 128 },
132 { 9, 16, 128 },
133 { 33, 0, 0 },
134 },
135 {
136 /* Four shader engines */
137 { 0, 256, 256 },
138 { 2, 128, 256 },
139 { 3, 128, 128 },
140 { 5, 64, 128 },
141 { 9, 16, 128 },
142 { 33, 0, 0 },
143 },
144 },
145 {
146 /* Four RB / SE */
147 {
148 /* One shader engine */
149 { 0, 128, 256 },
150 { 2, 128, 128 },
151 { 3, 64, 128 },
152 { 5, 32, 128 },
153 { 9, 16, 128 },
154 { 17, 0, 0 },
155 },
156 {
157 /* Two shader engines */
158 { 0, 256, 256 },
159 { 2, 128, 256 },
160 { 3, 128, 128 },
161 { 5, 64, 128 },
162 { 9, 32, 128 },
163 { 17, 16, 128 },
164 { 33, 0, 0 },
165 },
166 {
167 /* Four shader engines */
168 { 0, 256, 512 },
169 { 2, 128, 512 },
170 { 3, 64, 512 },
171 { 5, 32, 512 },
172 { 9, 32, 256 },
173 { 17, 32, 128 },
174 { 33, 0, 0 },
175 },
176 },
177 };
178
179 return si_find_bin_size(sctx->screen, table, sum);
180 }
181
182 static struct uvec2 si_get_depth_bin_size(struct si_context *sctx)
183 {
184 struct si_state_dsa *dsa = sctx->queued.named.dsa;
185
186 if (!sctx->framebuffer.state.zsbuf ||
187 (!dsa->depth_enabled && !dsa->stencil_enabled)) {
188 /* Return the max size. */
189 struct uvec2 size = {512, 512};
190 return size;
191 }
192
193 struct si_texture *tex =
194 (struct si_texture*)sctx->framebuffer.state.zsbuf->texture;
195 unsigned depth_coeff = dsa->depth_enabled ? 5 : 0;
196 unsigned stencil_coeff = tex->surface.has_stencil &&
197 dsa->stencil_enabled ? 1 : 0;
198 unsigned sum = 4 * (depth_coeff + stencil_coeff) *
199 MAX2(tex->buffer.b.b.nr_samples, 1);
200
201 static const si_bin_size_subtable table[] = {
202 {
203 // One RB / SE
204 {
205 // One shader engine
206 { 0, 64, 512 },
207 { 2, 64, 256 },
208 { 4, 64, 128 },
209 { 7, 32, 128 },
210 { 13, 16, 128 },
211 { 49, 0, 0 },
212 },
213 {
214 // Two shader engines
215 { 0, 128, 512 },
216 { 2, 64, 512 },
217 { 4, 64, 256 },
218 { 7, 64, 128 },
219 { 13, 32, 128 },
220 { 25, 16, 128 },
221 { 49, 0, 0 },
222 },
223 {
224 // Four shader engines
225 { 0, 256, 512 },
226 { 2, 128, 512 },
227 { 4, 64, 512 },
228 { 7, 64, 256 },
229 { 13, 64, 128 },
230 { 25, 16, 128 },
231 { 49, 0, 0 },
232 },
233 },
234 {
235 // Two RB / SE
236 {
237 // One shader engine
238 { 0, 128, 512 },
239 { 2, 64, 512 },
240 { 4, 64, 256 },
241 { 7, 64, 128 },
242 { 13, 32, 128 },
243 { 25, 16, 128 },
244 { 97, 0, 0 },
245 },
246 {
247 // Two shader engines
248 { 0, 256, 512 },
249 { 2, 128, 512 },
250 { 4, 64, 512 },
251 { 7, 64, 256 },
252 { 13, 64, 128 },
253 { 25, 32, 128 },
254 { 49, 16, 128 },
255 { 97, 0, 0 },
256 },
257 {
258 // Four shader engines
259 { 0, 512, 512 },
260 { 2, 256, 512 },
261 { 4, 128, 512 },
262 { 7, 64, 512 },
263 { 13, 64, 256 },
264 { 25, 64, 128 },
265 { 49, 16, 128 },
266 { 97, 0, 0 },
267 },
268 },
269 {
270 // Four RB / SE
271 {
272 // One shader engine
273 { 0, 256, 512 },
274 { 2, 128, 512 },
275 { 4, 64, 512 },
276 { 7, 64, 256 },
277 { 13, 64, 128 },
278 { 25, 32, 128 },
279 { 49, 16, 128 },
280 { 193, 0, 0 },
281 },
282 {
283 // Two shader engines
284 { 0, 512, 512 },
285 { 2, 256, 512 },
286 { 4, 128, 512 },
287 { 7, 64, 512 },
288 { 13, 64, 256 },
289 { 25, 64, 128 },
290 { 49, 32, 128 },
291 { 97, 16, 128 },
292 { 193, 0, 0 },
293 },
294 {
295 // Four shader engines
296 { 0, 512, 512 },
297 { 4, 256, 512 },
298 { 7, 128, 512 },
299 { 13, 64, 512 },
300 { 25, 32, 512 },
301 { 49, 32, 256 },
302 { 97, 16, 128 },
303 { 193, 0, 0 },
304 },
305 },
306 };
307
308 return si_find_bin_size(sctx->screen, table, sum);
309 }
310
311 static void gfx10_get_bin_sizes(struct si_context *sctx,
312 unsigned cb_target_enabled_4bit,
313 struct uvec2 *color_bin_size,
314 struct uvec2 *depth_bin_size)
315 {
316 const unsigned ZsTagSize = 64;
317 const unsigned ZsNumTags = 312;
318 const unsigned CcTagSize = 1024;
319 const unsigned CcReadTags = 31;
320 const unsigned FcTagSize = 256;
321 const unsigned FcReadTags = 44;
322
323 const unsigned num_rbs = sctx->screen->info.num_render_backends;
324 const unsigned num_pipes = MAX2(num_rbs, sctx->screen->info.num_sdp_interfaces);
325
326 const unsigned depthBinSizeTagPart = ((ZsNumTags * num_rbs / num_pipes) * (ZsTagSize * num_pipes));
327 const unsigned colorBinSizeTagPart = ((CcReadTags * num_rbs / num_pipes) * (CcTagSize * num_pipes));
328 const unsigned fmaskBinSizeTagPart = ((FcReadTags * num_rbs / num_pipes) * (FcTagSize * num_pipes));
329
330 const unsigned minBinSizeX = 128;
331 const unsigned minBinSizeY = 64;
332
333 const unsigned num_fragments = sctx->framebuffer.nr_color_samples;
334 const unsigned num_samples = sctx->framebuffer.nr_samples;
335 const bool ps_iter_sample = si_get_ps_iter_samples(sctx) >= 2;
336
337 /* Calculate cColor and cFmask(if applicable) */
338 unsigned cColor = 0;
339 unsigned cFmask = 0;
340 bool has_fmask = false;
341
342 for (unsigned i = 0; i < sctx->framebuffer.state.nr_cbufs; i++) {
343 if (!sctx->framebuffer.state.cbufs[i])
344 continue;
345
346 struct si_texture *tex =
347 (struct si_texture*)sctx->framebuffer.state.cbufs[i]->texture;
348 const unsigned mmrt =
349 num_fragments == 1 ? 1 : (ps_iter_sample ? num_fragments : 2);
350
351 cColor += tex->surface.bpe * mmrt;
352 if (num_samples >= 2 /* if FMASK is bound */) {
353 const unsigned fragmentsLog2 = util_logbase2(num_fragments);
354 const unsigned samplesLog2 = util_logbase2(num_samples);
355
356 static const unsigned cFmaskMrt[4 /* fragments */][5 /* samples */] = {
357 { 0, 1, 1, 1, 2 }, /* fragments = 1 */
358 { 0, 1, 1, 2, 4 }, /* fragments = 2 */
359 { 0, 1, 1, 4, 8 }, /* fragments = 4 */
360 { 0, 1, 2, 4, 8 } /* fragments = 8 */
361 };
362 cFmask += cFmaskMrt[fragmentsLog2][samplesLog2];
363 has_fmask = true;
364 }
365 }
366 cColor = MAX2(cColor, 1u);
367
368 const unsigned colorLog2Pixels = util_logbase2(colorBinSizeTagPart / cColor);
369 const unsigned colorBinSizeX = 1 << ((colorLog2Pixels + 1) / 2); /* round up width */
370 const unsigned colorBinSizeY = 1 << (colorLog2Pixels / 2); /* round down height */
371
372 unsigned binSizeX = colorBinSizeX;
373 unsigned binSizeY = colorBinSizeY;
374
375 if (has_fmask) {
376 cFmask = MAX2(cFmask, 1u);
377
378 const unsigned fmaskLog2Pixels = util_logbase2(fmaskBinSizeTagPart / cFmask);
379 const unsigned fmaskBinSizeX = 1 << ((fmaskLog2Pixels + 1) / 2); /* round up width */
380 const unsigned fmaskBinSizeY = 1 << (fmaskLog2Pixels / 2); /* round down height */
381
382 /* use the smaller of the Color vs. Fmask bin sizes */
383 if (fmaskLog2Pixels < colorLog2Pixels) {
384 binSizeX = fmaskBinSizeX;
385 binSizeY = fmaskBinSizeY;
386 }
387 }
388
389 /* Return size adjusted for minimum bin size */
390 color_bin_size->x = MAX2(binSizeX, minBinSizeX);
391 color_bin_size->y = MAX2(binSizeY, minBinSizeY);
392
393 if (!sctx->framebuffer.state.zsbuf) {
394 /* Set to max sizes when no depth buffer is bound. */
395 depth_bin_size->x = 512;
396 depth_bin_size->y = 512;
397 } else {
398 struct si_texture *zstex = (struct si_texture*)sctx->framebuffer.state.zsbuf->texture;
399 struct si_state_dsa *dsa = sctx->queued.named.dsa;
400
401 const unsigned cPerDepthSample = dsa->depth_enabled ? 5 : 0;
402 const unsigned cPerStencilSample = dsa->stencil_enabled ? 1 : 0;
403 const unsigned cDepth = (cPerDepthSample + cPerStencilSample) *
404 MAX2(zstex->buffer.b.b.nr_samples, 1);
405
406 const unsigned depthLog2Pixels = util_logbase2(depthBinSizeTagPart / MAX2(cDepth, 1u));
407 unsigned depthBinSizeX = 1 << ((depthLog2Pixels + 1) / 2);
408 unsigned depthBinSizeY = 1 << (depthLog2Pixels / 2);
409
410 depth_bin_size->x = MAX2(depthBinSizeX, minBinSizeX);
411 depth_bin_size->y = MAX2(depthBinSizeY, minBinSizeY);
412 }
413 }
414
415 static void si_emit_dpbb_disable(struct si_context *sctx)
416 {
417 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
418
419 if (sctx->chip_class >= GFX10) {
420 struct uvec2 bin_size = {};
421 struct uvec2 bin_size_extend = {};
422
423 bin_size.x = 128;
424 bin_size.y = sctx->framebuffer.min_bytes_per_pixel <= 4 ? 128 : 64;
425
426 if (bin_size.x >= 32)
427 bin_size_extend.x = util_logbase2(bin_size.x) - 5;
428 if (bin_size.y >= 32)
429 bin_size_extend.y = util_logbase2(bin_size.y) - 5;
430
431 radeon_opt_set_context_reg(sctx, R_028C44_PA_SC_BINNER_CNTL_0,
432 SI_TRACKED_PA_SC_BINNER_CNTL_0,
433 S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_NEW_SC) |
434 S_028C44_BIN_SIZE_X(bin_size.x == 16) |
435 S_028C44_BIN_SIZE_Y(bin_size.y == 16) |
436 S_028C44_BIN_SIZE_X_EXTEND(bin_size_extend.x) |
437 S_028C44_BIN_SIZE_Y_EXTEND(bin_size_extend.y) |
438 S_028C44_DISABLE_START_OF_PRIM(1) |
439 S_028C44_FLUSH_ON_BINNING_TRANSITION(sctx->last_binning_enabled != 0));
440 } else {
441 radeon_opt_set_context_reg(sctx, R_028C44_PA_SC_BINNER_CNTL_0,
442 SI_TRACKED_PA_SC_BINNER_CNTL_0,
443 S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_LEGACY_SC) |
444 S_028C44_DISABLE_START_OF_PRIM(1) |
445 S_028C44_FLUSH_ON_BINNING_TRANSITION((sctx->family == CHIP_VEGA12 ||
446 sctx->family == CHIP_VEGA20 ||
447 sctx->family >= CHIP_RAVEN2) &&
448 sctx->last_binning_enabled != 0));
449 }
450
451 unsigned db_dfsm_control = sctx->chip_class >= GFX10 ? R_028038_DB_DFSM_CONTROL
452 : R_028060_DB_DFSM_CONTROL;
453 radeon_opt_set_context_reg(sctx, db_dfsm_control,
454 SI_TRACKED_DB_DFSM_CONTROL,
455 S_028060_PUNCHOUT_MODE(V_028060_FORCE_OFF) |
456 S_028060_POPS_DRAIN_PS_ON_OVERLAP(1));
457 if (initial_cdw != sctx->gfx_cs->current.cdw)
458 sctx->context_roll = true;
459
460 sctx->last_binning_enabled = false;
461 }
462
463 void si_emit_dpbb_state(struct si_context *sctx)
464 {
465 struct si_screen *sscreen = sctx->screen;
466 struct si_state_blend *blend = sctx->queued.named.blend;
467 struct si_state_dsa *dsa = sctx->queued.named.dsa;
468 unsigned db_shader_control = sctx->ps_db_shader_control;
469
470 assert(sctx->chip_class >= GFX9);
471
472 if (!sscreen->dpbb_allowed || sctx->dpbb_force_off) {
473 si_emit_dpbb_disable(sctx);
474 return;
475 }
476
477 bool ps_can_kill = G_02880C_KILL_ENABLE(db_shader_control) ||
478 G_02880C_MASK_EXPORT_ENABLE(db_shader_control) ||
479 G_02880C_COVERAGE_TO_MASK_ENABLE(db_shader_control) ||
480 blend->alpha_to_coverage;
481
482 bool db_can_reject_z_trivially =
483 !G_02880C_Z_EXPORT_ENABLE(db_shader_control) ||
484 G_02880C_CONSERVATIVE_Z_EXPORT(db_shader_control) ||
485 G_02880C_DEPTH_BEFORE_SHADER(db_shader_control);
486
487 /* Disable DPBB when it's believed to be inefficient. */
488 if (sscreen->info.num_render_backends > 4 &&
489 ps_can_kill &&
490 db_can_reject_z_trivially &&
491 sctx->framebuffer.state.zsbuf &&
492 dsa->db_can_write) {
493 si_emit_dpbb_disable(sctx);
494 return;
495 }
496
497 /* Compute the bin size. */
498 /* TODO: We could also look at enabled pixel shader outputs. */
499 unsigned cb_target_enabled_4bit = sctx->framebuffer.colorbuf_enabled_4bit &
500 blend->cb_target_enabled_4bit;
501 struct uvec2 color_bin_size, depth_bin_size;
502
503 if (sctx->chip_class >= GFX10) {
504 gfx10_get_bin_sizes(sctx, cb_target_enabled_4bit,
505 &color_bin_size, &depth_bin_size);
506 } else {
507 color_bin_size = si_get_color_bin_size(sctx, cb_target_enabled_4bit);
508 depth_bin_size = si_get_depth_bin_size(sctx);
509 }
510
511 unsigned color_area = color_bin_size.x * color_bin_size.y;
512 unsigned depth_area = depth_bin_size.x * depth_bin_size.y;
513
514 struct uvec2 bin_size = color_area < depth_area ? color_bin_size
515 : depth_bin_size;
516
517 if (!bin_size.x || !bin_size.y) {
518 si_emit_dpbb_disable(sctx);
519 return;
520 }
521
522 /* Enable DFSM if it's preferred. */
523 unsigned punchout_mode = V_028060_FORCE_OFF;
524 bool disable_start_of_prim = true;
525 bool zs_eqaa_dfsm_bug = sctx->chip_class == GFX9 &&
526 sctx->framebuffer.state.zsbuf &&
527 sctx->framebuffer.nr_samples !=
528 MAX2(1, sctx->framebuffer.state.zsbuf->texture->nr_samples);
529
530 if (sscreen->dfsm_allowed &&
531 !zs_eqaa_dfsm_bug &&
532 cb_target_enabled_4bit &&
533 !G_02880C_KILL_ENABLE(db_shader_control) &&
534 /* These two also imply that DFSM is disabled when PS writes to memory. */
535 !G_02880C_EXEC_ON_HIER_FAIL(db_shader_control) &&
536 !G_02880C_EXEC_ON_NOOP(db_shader_control) &&
537 G_02880C_Z_ORDER(db_shader_control) == V_02880C_EARLY_Z_THEN_LATE_Z) {
538 punchout_mode = V_028060_AUTO;
539 disable_start_of_prim = (cb_target_enabled_4bit &
540 blend->blend_enable_4bit) != 0;
541 }
542
543 /* Tunable parameters. Also test with DFSM enabled/disabled. */
544 unsigned context_states_per_bin; /* allowed range: [1, 6] */
545 unsigned persistent_states_per_bin; /* allowed range: [1, 32] */
546 unsigned fpovs_per_batch; /* allowed range: [0, 255], 0 = unlimited */
547
548 /* Tuned for Raven. Vega might need different values. */
549 if (sscreen->info.has_dedicated_vram) {
550 if (sscreen->info.num_render_backends > 4) {
551 context_states_per_bin = 1;
552 persistent_states_per_bin = 1;
553 } else {
554 context_states_per_bin = 3;
555 persistent_states_per_bin = 8;
556 }
557 } else {
558 /* This is a workaround for:
559 * https://bugs.freedesktop.org/show_bug.cgi?id=110214
560 * (an alternative is to insert manual BATCH_BREAK event when
561 * a context_roll is detected). */
562 context_states_per_bin = sctx->screen->info.has_gfx9_scissor_bug ? 1 : 6;
563 /* Using 32 here can cause GPU hangs on RAVEN1 */
564 persistent_states_per_bin = 16;
565 }
566 fpovs_per_batch = 63;
567
568 /* Emit registers. */
569 struct uvec2 bin_size_extend = {};
570 if (bin_size.x >= 32)
571 bin_size_extend.x = util_logbase2(bin_size.x) - 5;
572 if (bin_size.y >= 32)
573 bin_size_extend.y = util_logbase2(bin_size.y) - 5;
574
575 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
576 radeon_opt_set_context_reg(
577 sctx, R_028C44_PA_SC_BINNER_CNTL_0,
578 SI_TRACKED_PA_SC_BINNER_CNTL_0,
579 S_028C44_BINNING_MODE(V_028C44_BINNING_ALLOWED) |
580 S_028C44_BIN_SIZE_X(bin_size.x == 16) |
581 S_028C44_BIN_SIZE_Y(bin_size.y == 16) |
582 S_028C44_BIN_SIZE_X_EXTEND(bin_size_extend.x) |
583 S_028C44_BIN_SIZE_Y_EXTEND(bin_size_extend.y) |
584 S_028C44_CONTEXT_STATES_PER_BIN(context_states_per_bin - 1) |
585 S_028C44_PERSISTENT_STATES_PER_BIN(persistent_states_per_bin - 1) |
586 S_028C44_DISABLE_START_OF_PRIM(disable_start_of_prim) |
587 S_028C44_FPOVS_PER_BATCH(fpovs_per_batch) |
588 S_028C44_OPTIMAL_BIN_SELECTION(1) |
589 S_028C44_FLUSH_ON_BINNING_TRANSITION((sctx->family == CHIP_VEGA12 ||
590 sctx->family == CHIP_VEGA20 ||
591 sctx->family >= CHIP_RAVEN2) &&
592 sctx->last_binning_enabled != 1));
593
594 unsigned db_dfsm_control = sctx->chip_class >= GFX10 ? R_028038_DB_DFSM_CONTROL
595 : R_028060_DB_DFSM_CONTROL;
596 radeon_opt_set_context_reg(sctx, db_dfsm_control,
597 SI_TRACKED_DB_DFSM_CONTROL,
598 S_028060_PUNCHOUT_MODE(punchout_mode) |
599 S_028060_POPS_DRAIN_PS_ON_OVERLAP(1));
600 if (initial_cdw != sctx->gfx_cs->current.cdw)
601 sctx->context_roll = true;
602
603 sctx->last_binning_enabled = true;
604 }