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radeonsi: remove unused atom parameter from si_atom::emit
[mesa.git] / src / gallium / drivers / radeonsi / si_state_binning.c
1 /*
2 * Copyright 2017 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 /* This file handles register programming of primitive binning. */
26
27 #include "si_build_pm4.h"
28 #include "gfx9d.h"
29
30 struct uvec2 {
31 unsigned x, y;
32 };
33
34 struct si_bin_size_map {
35 unsigned start;
36 unsigned bin_size_x;
37 unsigned bin_size_y;
38 };
39
40 typedef struct si_bin_size_map si_bin_size_subtable[3][9];
41
42 /* Find the bin size where sum is >= table[i].start and < table[i + 1].start. */
43 static struct uvec2 si_find_bin_size(struct si_screen *sscreen,
44 const si_bin_size_subtable table[],
45 unsigned sum)
46 {
47 unsigned log_num_rb_per_se =
48 util_logbase2_ceil(sscreen->info.num_render_backends /
49 sscreen->info.max_se);
50 unsigned log_num_se = util_logbase2_ceil(sscreen->info.max_se);
51 unsigned i;
52
53 /* Get the chip-specific subtable. */
54 const struct si_bin_size_map *subtable =
55 &table[log_num_rb_per_se][log_num_se][0];
56
57 for (i = 0; subtable[i].start != UINT_MAX; i++) {
58 if (sum >= subtable[i].start && sum < subtable[i + 1].start)
59 break;
60 }
61
62 struct uvec2 size = {subtable[i].bin_size_x, subtable[i].bin_size_y};
63 return size;
64 }
65
66 static struct uvec2 si_get_color_bin_size(struct si_context *sctx,
67 unsigned cb_target_enabled_4bit)
68 {
69 unsigned nr_samples = sctx->framebuffer.nr_samples;
70 unsigned sum = 0;
71
72 /* Compute the sum of all Bpp. */
73 for (unsigned i = 0; i < sctx->framebuffer.state.nr_cbufs; i++) {
74 if (!(cb_target_enabled_4bit & (0xf << (i * 4))))
75 continue;
76
77 struct r600_texture *rtex =
78 (struct r600_texture*)sctx->framebuffer.state.cbufs[i]->texture;
79 sum += rtex->surface.bpe;
80 }
81
82 /* Multiply the sum by some function of the number of samples. */
83 if (nr_samples >= 2) {
84 if (si_get_ps_iter_samples(sctx) >= 2)
85 sum *= nr_samples;
86 else
87 sum *= 2;
88 }
89
90 static const si_bin_size_subtable table[] = {
91 {
92 /* One RB / SE */
93 {
94 /* One shader engine */
95 { 0, 128, 128 },
96 { 1, 64, 128 },
97 { 2, 32, 128 },
98 { 3, 16, 128 },
99 { 17, 0, 0 },
100 { UINT_MAX, 0, 0 },
101 },
102 {
103 /* Two shader engines */
104 { 0, 128, 128 },
105 { 2, 64, 128 },
106 { 3, 32, 128 },
107 { 5, 16, 128 },
108 { 17, 0, 0 },
109 { UINT_MAX, 0, 0 },
110 },
111 {
112 /* Four shader engines */
113 { 0, 128, 128 },
114 { 3, 64, 128 },
115 { 5, 16, 128 },
116 { 17, 0, 0 },
117 { UINT_MAX, 0, 0 },
118 },
119 },
120 {
121 /* Two RB / SE */
122 {
123 /* One shader engine */
124 { 0, 128, 128 },
125 { 2, 64, 128 },
126 { 3, 32, 128 },
127 { 5, 16, 128 },
128 { 33, 0, 0 },
129 { UINT_MAX, 0, 0 },
130 },
131 {
132 /* Two shader engines */
133 { 0, 128, 128 },
134 { 3, 64, 128 },
135 { 5, 32, 128 },
136 { 9, 16, 128 },
137 { 33, 0, 0 },
138 { UINT_MAX, 0, 0 },
139 },
140 {
141 /* Four shader engines */
142 { 0, 256, 256 },
143 { 2, 128, 256 },
144 { 3, 128, 128 },
145 { 5, 64, 128 },
146 { 9, 16, 128 },
147 { 33, 0, 0 },
148 { UINT_MAX, 0, 0 },
149 },
150 },
151 {
152 /* Four RB / SE */
153 {
154 /* One shader engine */
155 { 0, 128, 256 },
156 { 2, 128, 128 },
157 { 3, 64, 128 },
158 { 5, 32, 128 },
159 { 9, 16, 128 },
160 { 33, 0, 0 },
161 { UINT_MAX, 0, 0 },
162 },
163 {
164 /* Two shader engines */
165 { 0, 256, 256 },
166 { 2, 128, 256 },
167 { 3, 128, 128 },
168 { 5, 64, 128 },
169 { 9, 32, 128 },
170 { 17, 16, 128 },
171 { 33, 0, 0 },
172 { UINT_MAX, 0, 0 },
173 },
174 {
175 /* Four shader engines */
176 { 0, 256, 512 },
177 { 2, 256, 256 },
178 { 3, 128, 256 },
179 { 5, 128, 128 },
180 { 9, 64, 128 },
181 { 17, 16, 128 },
182 { 33, 0, 0 },
183 { UINT_MAX, 0, 0 },
184 },
185 },
186 };
187
188 return si_find_bin_size(sctx->screen, table, sum);
189 }
190
191 static struct uvec2 si_get_depth_bin_size(struct si_context *sctx)
192 {
193 struct si_state_dsa *dsa = sctx->queued.named.dsa;
194
195 if (!sctx->framebuffer.state.zsbuf ||
196 (!dsa->depth_enabled && !dsa->stencil_enabled)) {
197 /* Return the max size. */
198 struct uvec2 size = {512, 512};
199 return size;
200 }
201
202 struct r600_texture *rtex =
203 (struct r600_texture*)sctx->framebuffer.state.zsbuf->texture;
204 unsigned depth_coeff = dsa->depth_enabled ? 5 : 0;
205 unsigned stencil_coeff = rtex->surface.has_stencil &&
206 dsa->stencil_enabled ? 1 : 0;
207 unsigned sum = 4 * (depth_coeff + stencil_coeff) *
208 sctx->framebuffer.nr_samples;
209
210 static const si_bin_size_subtable table[] = {
211 {
212 // One RB / SE
213 {
214 // One shader engine
215 { 0, 128, 256 },
216 { 2, 128, 128 },
217 { 4, 64, 128 },
218 { 7, 32, 128 },
219 { 13, 16, 128 },
220 { 49, 0, 0 },
221 { UINT_MAX, 0, 0 },
222 },
223 {
224 // Two shader engines
225 { 0, 256, 256 },
226 { 2, 128, 256 },
227 { 4, 128, 128 },
228 { 7, 64, 128 },
229 { 13, 32, 128 },
230 { 25, 16, 128 },
231 { 49, 0, 0 },
232 { UINT_MAX, 0, 0 },
233 },
234 {
235 // Four shader engines
236 { 0, 256, 512 },
237 { 2, 256, 256 },
238 { 4, 128, 256 },
239 { 7, 128, 128 },
240 { 13, 64, 128 },
241 { 25, 16, 128 },
242 { 49, 0, 0 },
243 { UINT_MAX, 0, 0 },
244 },
245 },
246 {
247 // Two RB / SE
248 {
249 // One shader engine
250 { 0, 256, 256 },
251 { 2, 128, 256 },
252 { 4, 128, 128 },
253 { 7, 64, 128 },
254 { 13, 32, 128 },
255 { 25, 16, 128 },
256 { 97, 0, 0 },
257 { UINT_MAX, 0, 0 },
258 },
259 {
260 // Two shader engines
261 { 0, 256, 512 },
262 { 2, 256, 256 },
263 { 4, 128, 256 },
264 { 7, 128, 128 },
265 { 13, 64, 128 },
266 { 25, 32, 128 },
267 { 49, 16, 128 },
268 { 97, 0, 0 },
269 { UINT_MAX, 0, 0 },
270 },
271 {
272 // Four shader engines
273 { 0, 512, 512 },
274 { 2, 256, 512 },
275 { 4, 256, 256 },
276 { 7, 128, 256 },
277 { 13, 128, 128 },
278 { 25, 64, 128 },
279 { 49, 16, 128 },
280 { 97, 0, 0 },
281 { UINT_MAX, 0, 0 },
282 },
283 },
284 {
285 // Four RB / SE
286 {
287 // One shader engine
288 { 0, 256, 512 },
289 { 2, 256, 256 },
290 { 4, 128, 256 },
291 { 7, 128, 128 },
292 { 13, 64, 128 },
293 { 25, 32, 128 },
294 { 49, 16, 128 },
295 { UINT_MAX, 0, 0 },
296 },
297 {
298 // Two shader engines
299 { 0, 512, 512 },
300 { 2, 256, 512 },
301 { 4, 256, 256 },
302 { 7, 128, 256 },
303 { 13, 128, 128 },
304 { 25, 64, 128 },
305 { 49, 32, 128 },
306 { 97, 16, 128 },
307 { UINT_MAX, 0, 0 },
308 },
309 {
310 // Four shader engines
311 { 0, 512, 512 },
312 { 4, 256, 512 },
313 { 7, 256, 256 },
314 { 13, 128, 256 },
315 { 25, 128, 128 },
316 { 49, 64, 128 },
317 { 97, 16, 128 },
318 { UINT_MAX, 0, 0 },
319 },
320 },
321 };
322
323 return si_find_bin_size(sctx->screen, table, sum);
324 }
325
326 static void si_emit_dpbb_disable(struct si_context *sctx)
327 {
328 struct radeon_winsys_cs *cs = sctx->gfx_cs;
329
330 radeon_set_context_reg(cs, R_028C44_PA_SC_BINNER_CNTL_0,
331 S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_LEGACY_SC) |
332 S_028C44_DISABLE_START_OF_PRIM(1));
333 radeon_set_context_reg(cs, R_028060_DB_DFSM_CONTROL,
334 S_028060_PUNCHOUT_MODE(V_028060_FORCE_OFF));
335 }
336
337 void si_emit_dpbb_state(struct si_context *sctx)
338 {
339 struct si_screen *sscreen = sctx->screen;
340 struct si_state_blend *blend = sctx->queued.named.blend;
341 struct si_state_dsa *dsa = sctx->queued.named.dsa;
342 unsigned db_shader_control = sctx->ps_db_shader_control;
343
344 assert(sctx->chip_class >= GFX9);
345
346 if (!sscreen->dpbb_allowed || !blend || !dsa) {
347 si_emit_dpbb_disable(sctx);
348 return;
349 }
350
351 bool ps_can_kill = G_02880C_KILL_ENABLE(db_shader_control) ||
352 G_02880C_MASK_EXPORT_ENABLE(db_shader_control) ||
353 G_02880C_COVERAGE_TO_MASK_ENABLE(db_shader_control) ||
354 blend->alpha_to_coverage;
355
356 /* This is ported from Vulkan, but it doesn't make much sense to me.
357 * Maybe it's for RE-Z? But Vulkan doesn't use RE-Z. TODO: Clarify this.
358 */
359 bool ps_can_reject_z_trivially =
360 !G_02880C_Z_EXPORT_ENABLE(db_shader_control) ||
361 G_02880C_CONSERVATIVE_Z_EXPORT(db_shader_control);
362
363 /* Disable binning if PS can kill trivially with DB writes.
364 * Ported from Vulkan. (heuristic?)
365 */
366 if (ps_can_kill &&
367 ps_can_reject_z_trivially &&
368 sctx->framebuffer.state.zsbuf &&
369 dsa->db_can_write) {
370 si_emit_dpbb_disable(sctx);
371 return;
372 }
373
374 /* Compute the bin size. */
375 /* TODO: We could also look at enabled pixel shader outputs. */
376 unsigned cb_target_enabled_4bit = sctx->framebuffer.colorbuf_enabled_4bit &
377 blend->cb_target_enabled_4bit;
378 struct uvec2 color_bin_size =
379 si_get_color_bin_size(sctx, cb_target_enabled_4bit);
380 struct uvec2 depth_bin_size = si_get_depth_bin_size(sctx);
381
382 unsigned color_area = color_bin_size.x * color_bin_size.y;
383 unsigned depth_area = depth_bin_size.x * depth_bin_size.y;
384
385 struct uvec2 bin_size = color_area < depth_area ? color_bin_size
386 : depth_bin_size;
387
388 if (!bin_size.x || !bin_size.y) {
389 si_emit_dpbb_disable(sctx);
390 return;
391 }
392
393 /* Enable DFSM if it's preferred. */
394 unsigned punchout_mode = V_028060_FORCE_OFF;
395 bool disable_start_of_prim = true;
396
397 if (sscreen->dfsm_allowed &&
398 cb_target_enabled_4bit &&
399 !G_02880C_KILL_ENABLE(db_shader_control) &&
400 /* These two also imply that DFSM is disabled when PS writes to memory. */
401 !G_02880C_EXEC_ON_HIER_FAIL(db_shader_control) &&
402 !G_02880C_EXEC_ON_NOOP(db_shader_control) &&
403 G_02880C_Z_ORDER(db_shader_control) == V_02880C_EARLY_Z_THEN_LATE_Z) {
404 punchout_mode = V_028060_AUTO;
405 disable_start_of_prim = (cb_target_enabled_4bit &
406 blend->blend_enable_4bit) != 0;
407 }
408
409 /* Tunable parameters. Also test with DFSM enabled/disabled. */
410 unsigned context_states_per_bin; /* allowed range: [0, 5] */
411 unsigned persistent_states_per_bin; /* allowed range: [0, 31] */
412 unsigned fpovs_per_batch; /* allowed range: [0, 255], 0 = unlimited */
413
414 switch (sctx->family) {
415 case CHIP_VEGA10:
416 case CHIP_VEGA12:
417 case CHIP_RAVEN:
418 /* Tuned for Raven. Vega might need different values. */
419 context_states_per_bin = 5;
420 persistent_states_per_bin = 31;
421 fpovs_per_batch = 63;
422 break;
423 default:
424 assert(0);
425 }
426
427 /* Emit registers. */
428 struct uvec2 bin_size_extend = {};
429 if (bin_size.x >= 32)
430 bin_size_extend.x = util_logbase2(bin_size.x) - 5;
431 if (bin_size.y >= 32)
432 bin_size_extend.y = util_logbase2(bin_size.y) - 5;
433
434 struct radeon_winsys_cs *cs = sctx->gfx_cs;
435 radeon_set_context_reg(cs, R_028C44_PA_SC_BINNER_CNTL_0,
436 S_028C44_BINNING_MODE(V_028C44_BINNING_ALLOWED) |
437 S_028C44_BIN_SIZE_X(bin_size.x == 16) |
438 S_028C44_BIN_SIZE_Y(bin_size.y == 16) |
439 S_028C44_BIN_SIZE_X_EXTEND(bin_size_extend.x) |
440 S_028C44_BIN_SIZE_Y_EXTEND(bin_size_extend.y) |
441 S_028C44_CONTEXT_STATES_PER_BIN(context_states_per_bin) |
442 S_028C44_PERSISTENT_STATES_PER_BIN(persistent_states_per_bin) |
443 S_028C44_DISABLE_START_OF_PRIM(disable_start_of_prim) |
444 S_028C44_FPOVS_PER_BATCH(fpovs_per_batch) |
445 S_028C44_OPTIMAL_BIN_SELECTION(1));
446 radeon_set_context_reg(cs, R_028060_DB_DFSM_CONTROL,
447 S_028060_PUNCHOUT_MODE(punchout_mode));
448 }