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radeonsi/gfx9: remove UINT_MAX array terminators in bin size tables
[mesa.git] / src / gallium / drivers / radeonsi / si_state_binning.c
1 /*
2 * Copyright 2017 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 /* This file handles register programming of primitive binning. */
26
27 #include "si_build_pm4.h"
28 #include "gfx9d.h"
29
30 struct uvec2 {
31 unsigned x, y;
32 };
33
34 struct si_bin_size_map {
35 unsigned start;
36 unsigned bin_size_x;
37 unsigned bin_size_y;
38 };
39
40 typedef struct si_bin_size_map si_bin_size_subtable[3][10];
41
42 /* Find the bin size where sum is >= table[i].start and < table[i + 1].start. */
43 static struct uvec2 si_find_bin_size(struct si_screen *sscreen,
44 const si_bin_size_subtable table[],
45 unsigned sum)
46 {
47 unsigned log_num_rb_per_se =
48 util_logbase2_ceil(sscreen->info.num_render_backends /
49 sscreen->info.max_se);
50 unsigned log_num_se = util_logbase2_ceil(sscreen->info.max_se);
51 unsigned i;
52
53 /* Get the chip-specific subtable. */
54 const struct si_bin_size_map *subtable =
55 &table[log_num_rb_per_se][log_num_se][0];
56
57 for (i = 0; subtable[i].bin_size_x != 0; i++) {
58 if (sum >= subtable[i].start && sum < subtable[i + 1].start)
59 break;
60 }
61
62 struct uvec2 size = {subtable[i].bin_size_x, subtable[i].bin_size_y};
63 return size;
64 }
65
66 static struct uvec2 si_get_color_bin_size(struct si_context *sctx,
67 unsigned cb_target_enabled_4bit)
68 {
69 unsigned num_fragments = sctx->framebuffer.nr_color_samples;
70 unsigned sum = 0;
71
72 /* Compute the sum of all Bpp. */
73 for (unsigned i = 0; i < sctx->framebuffer.state.nr_cbufs; i++) {
74 if (!(cb_target_enabled_4bit & (0xf << (i * 4))))
75 continue;
76
77 struct r600_texture *rtex =
78 (struct r600_texture*)sctx->framebuffer.state.cbufs[i]->texture;
79 sum += rtex->surface.bpe;
80 }
81
82 /* Multiply the sum by some function of the number of samples. */
83 if (num_fragments >= 2) {
84 if (si_get_ps_iter_samples(sctx) >= 2)
85 sum *= num_fragments;
86 else
87 sum *= 2;
88 }
89
90 static const si_bin_size_subtable table[] = {
91 {
92 /* One RB / SE */
93 {
94 /* One shader engine */
95 { 0, 128, 128 },
96 { 1, 64, 128 },
97 { 2, 32, 128 },
98 { 3, 16, 128 },
99 { 17, 0, 0 },
100 },
101 {
102 /* Two shader engines */
103 { 0, 128, 128 },
104 { 2, 64, 128 },
105 { 3, 32, 128 },
106 { 5, 16, 128 },
107 { 17, 0, 0 },
108 },
109 {
110 /* Four shader engines */
111 { 0, 128, 128 },
112 { 3, 64, 128 },
113 { 5, 16, 128 },
114 { 17, 0, 0 },
115 },
116 },
117 {
118 /* Two RB / SE */
119 {
120 /* One shader engine */
121 { 0, 128, 128 },
122 { 2, 64, 128 },
123 { 3, 32, 128 },
124 { 9, 16, 128 },
125 { 33, 0, 0 },
126 },
127 {
128 /* Two shader engines */
129 { 0, 128, 128 },
130 { 3, 64, 128 },
131 { 5, 32, 128 },
132 { 9, 16, 128 },
133 { 33, 0, 0 },
134 },
135 {
136 /* Four shader engines */
137 { 0, 256, 256 },
138 { 2, 128, 256 },
139 { 3, 128, 128 },
140 { 5, 64, 128 },
141 { 9, 16, 128 },
142 { 33, 0, 0 },
143 },
144 },
145 {
146 /* Four RB / SE */
147 {
148 /* One shader engine */
149 { 0, 128, 256 },
150 { 2, 128, 128 },
151 { 3, 64, 128 },
152 { 5, 32, 128 },
153 { 9, 16, 128 },
154 { 17, 0, 0 },
155 },
156 {
157 /* Two shader engines */
158 { 0, 256, 256 },
159 { 2, 128, 256 },
160 { 3, 128, 128 },
161 { 5, 64, 128 },
162 { 9, 32, 128 },
163 { 17, 16, 128 },
164 { 33, 0, 0 },
165 },
166 {
167 /* Four shader engines */
168 { 0, 256, 512 },
169 { 2, 128, 512 },
170 { 3, 64, 512 },
171 { 5, 32, 512 },
172 { 9, 32, 256 },
173 { 17, 32, 128 },
174 { 33, 0, 0 },
175 },
176 },
177 };
178
179 return si_find_bin_size(sctx->screen, table, sum);
180 }
181
182 static struct uvec2 si_get_depth_bin_size(struct si_context *sctx)
183 {
184 struct si_state_dsa *dsa = sctx->queued.named.dsa;
185
186 if (!sctx->framebuffer.state.zsbuf ||
187 (!dsa->depth_enabled && !dsa->stencil_enabled)) {
188 /* Return the max size. */
189 struct uvec2 size = {512, 512};
190 return size;
191 }
192
193 struct r600_texture *rtex =
194 (struct r600_texture*)sctx->framebuffer.state.zsbuf->texture;
195 unsigned depth_coeff = dsa->depth_enabled ? 5 : 0;
196 unsigned stencil_coeff = rtex->surface.has_stencil &&
197 dsa->stencil_enabled ? 1 : 0;
198 unsigned sum = 4 * (depth_coeff + stencil_coeff) *
199 rtex->buffer.b.b.nr_samples;
200
201 static const si_bin_size_subtable table[] = {
202 {
203 // One RB / SE
204 {
205 // One shader engine
206 { 0, 64, 512 },
207 { 2, 64, 256 },
208 { 4, 64, 128 },
209 { 7, 32, 128 },
210 { 13, 16, 128 },
211 { 49, 0, 0 },
212 },
213 {
214 // Two shader engines
215 { 0, 128, 512 },
216 { 2, 64, 512 },
217 { 4, 64, 256 },
218 { 7, 64, 128 },
219 { 13, 32, 128 },
220 { 25, 16, 128 },
221 { 49, 0, 0 },
222 },
223 {
224 // Four shader engines
225 { 0, 256, 512 },
226 { 2, 128, 512 },
227 { 4, 64, 512 },
228 { 7, 64, 256 },
229 { 13, 64, 128 },
230 { 25, 16, 128 },
231 { 49, 0, 0 },
232 },
233 },
234 {
235 // Two RB / SE
236 {
237 // One shader engine
238 { 0, 128, 512 },
239 { 2, 64, 512 },
240 { 4, 64, 256 },
241 { 7, 64, 128 },
242 { 13, 32, 128 },
243 { 25, 16, 128 },
244 { 97, 0, 0 },
245 },
246 {
247 // Two shader engines
248 { 0, 256, 512 },
249 { 2, 128, 512 },
250 { 4, 64, 512 },
251 { 7, 64, 256 },
252 { 13, 64, 128 },
253 { 25, 32, 128 },
254 { 49, 16, 128 },
255 { 97, 0, 0 },
256 },
257 {
258 // Four shader engines
259 { 0, 512, 512 },
260 { 2, 256, 512 },
261 { 4, 128, 512 },
262 { 7, 64, 512 },
263 { 13, 64, 256 },
264 { 25, 64, 128 },
265 { 49, 16, 128 },
266 { 97, 0, 0 },
267 },
268 },
269 {
270 // Four RB / SE
271 {
272 // One shader engine
273 { 0, 256, 512 },
274 { 2, 128, 512 },
275 { 4, 64, 512 },
276 { 7, 64, 256 },
277 { 13, 64, 128 },
278 { 25, 32, 128 },
279 { 49, 16, 128 },
280 { 193, 0, 0 },
281 },
282 {
283 // Two shader engines
284 { 0, 512, 512 },
285 { 2, 256, 512 },
286 { 4, 128, 512 },
287 { 7, 64, 512 },
288 { 13, 64, 256 },
289 { 25, 64, 128 },
290 { 49, 32, 128 },
291 { 97, 16, 128 },
292 { 193, 0, 0 },
293 },
294 {
295 // Four shader engines
296 { 0, 512, 512 },
297 { 4, 256, 512 },
298 { 7, 128, 512 },
299 { 13, 64, 512 },
300 { 25, 32, 512 },
301 { 49, 32, 256 },
302 { 97, 16, 128 },
303 { 193, 0, 0 },
304 },
305 },
306 };
307
308 return si_find_bin_size(sctx->screen, table, sum);
309 }
310
311 static void si_emit_dpbb_disable(struct si_context *sctx)
312 {
313 radeon_opt_set_context_reg(sctx, R_028C44_PA_SC_BINNER_CNTL_0,
314 SI_TRACKED_PA_SC_BINNER_CNTL_0,
315 S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_LEGACY_SC) |
316 S_028C44_DISABLE_START_OF_PRIM(1));
317 radeon_opt_set_context_reg(sctx, R_028060_DB_DFSM_CONTROL,
318 SI_TRACKED_DB_DFSM_CONTROL,
319 S_028060_PUNCHOUT_MODE(V_028060_FORCE_OFF));
320 }
321
322 void si_emit_dpbb_state(struct si_context *sctx)
323 {
324 struct si_screen *sscreen = sctx->screen;
325 struct si_state_blend *blend = sctx->queued.named.blend;
326 struct si_state_dsa *dsa = sctx->queued.named.dsa;
327 unsigned db_shader_control = sctx->ps_db_shader_control;
328
329 assert(sctx->chip_class >= GFX9);
330
331 if (!sscreen->dpbb_allowed || !blend || !dsa || sctx->dpbb_force_off) {
332 si_emit_dpbb_disable(sctx);
333 return;
334 }
335
336 bool ps_can_kill = G_02880C_KILL_ENABLE(db_shader_control) ||
337 G_02880C_MASK_EXPORT_ENABLE(db_shader_control) ||
338 G_02880C_COVERAGE_TO_MASK_ENABLE(db_shader_control) ||
339 blend->alpha_to_coverage;
340
341 /* This is ported from Vulkan, but it doesn't make much sense to me.
342 * Maybe it's for RE-Z? But Vulkan doesn't use RE-Z. TODO: Clarify this.
343 */
344 bool ps_can_reject_z_trivially =
345 !G_02880C_Z_EXPORT_ENABLE(db_shader_control) ||
346 G_02880C_CONSERVATIVE_Z_EXPORT(db_shader_control);
347
348 /* Disable binning if PS can kill trivially with DB writes.
349 * Ported from Vulkan. (heuristic?)
350 */
351 if (ps_can_kill &&
352 ps_can_reject_z_trivially &&
353 sctx->framebuffer.state.zsbuf &&
354 dsa->db_can_write) {
355 si_emit_dpbb_disable(sctx);
356 return;
357 }
358
359 /* Compute the bin size. */
360 /* TODO: We could also look at enabled pixel shader outputs. */
361 unsigned cb_target_enabled_4bit = sctx->framebuffer.colorbuf_enabled_4bit &
362 blend->cb_target_enabled_4bit;
363 struct uvec2 color_bin_size =
364 si_get_color_bin_size(sctx, cb_target_enabled_4bit);
365 struct uvec2 depth_bin_size = si_get_depth_bin_size(sctx);
366
367 unsigned color_area = color_bin_size.x * color_bin_size.y;
368 unsigned depth_area = depth_bin_size.x * depth_bin_size.y;
369
370 struct uvec2 bin_size = color_area < depth_area ? color_bin_size
371 : depth_bin_size;
372
373 if (!bin_size.x || !bin_size.y) {
374 si_emit_dpbb_disable(sctx);
375 return;
376 }
377
378 /* Enable DFSM if it's preferred. */
379 unsigned punchout_mode = V_028060_FORCE_OFF;
380 bool disable_start_of_prim = true;
381 bool zs_eqaa_dfsm_bug = sctx->chip_class == GFX9 &&
382 sctx->framebuffer.state.zsbuf &&
383 sctx->framebuffer.nr_samples !=
384 MAX2(1, sctx->framebuffer.state.zsbuf->texture->nr_samples);
385
386 if (sscreen->dfsm_allowed &&
387 !zs_eqaa_dfsm_bug &&
388 cb_target_enabled_4bit &&
389 !G_02880C_KILL_ENABLE(db_shader_control) &&
390 /* These two also imply that DFSM is disabled when PS writes to memory. */
391 !G_02880C_EXEC_ON_HIER_FAIL(db_shader_control) &&
392 !G_02880C_EXEC_ON_NOOP(db_shader_control) &&
393 G_02880C_Z_ORDER(db_shader_control) == V_02880C_EARLY_Z_THEN_LATE_Z) {
394 punchout_mode = V_028060_AUTO;
395 disable_start_of_prim = (cb_target_enabled_4bit &
396 blend->blend_enable_4bit) != 0;
397 }
398
399 /* Tunable parameters. Also test with DFSM enabled/disabled. */
400 unsigned context_states_per_bin; /* allowed range: [0, 5] */
401 unsigned persistent_states_per_bin; /* allowed range: [0, 31] */
402 unsigned fpovs_per_batch; /* allowed range: [0, 255], 0 = unlimited */
403
404 switch (sctx->family) {
405 case CHIP_VEGA10:
406 case CHIP_VEGA12:
407 case CHIP_RAVEN:
408 /* Tuned for Raven. Vega might need different values. */
409 context_states_per_bin = 5;
410 persistent_states_per_bin = 31;
411 fpovs_per_batch = 63;
412 break;
413 default:
414 assert(0);
415 }
416
417 /* Emit registers. */
418 struct uvec2 bin_size_extend = {};
419 if (bin_size.x >= 32)
420 bin_size_extend.x = util_logbase2(bin_size.x) - 5;
421 if (bin_size.y >= 32)
422 bin_size_extend.y = util_logbase2(bin_size.y) - 5;
423
424 radeon_opt_set_context_reg(
425 sctx, R_028C44_PA_SC_BINNER_CNTL_0,
426 SI_TRACKED_PA_SC_BINNER_CNTL_0,
427 S_028C44_BINNING_MODE(V_028C44_BINNING_ALLOWED) |
428 S_028C44_BIN_SIZE_X(bin_size.x == 16) |
429 S_028C44_BIN_SIZE_Y(bin_size.y == 16) |
430 S_028C44_BIN_SIZE_X_EXTEND(bin_size_extend.x) |
431 S_028C44_BIN_SIZE_Y_EXTEND(bin_size_extend.y) |
432 S_028C44_CONTEXT_STATES_PER_BIN(context_states_per_bin) |
433 S_028C44_PERSISTENT_STATES_PER_BIN(persistent_states_per_bin) |
434 S_028C44_DISABLE_START_OF_PRIM(disable_start_of_prim) |
435 S_028C44_FPOVS_PER_BATCH(fpovs_per_batch) |
436 S_028C44_OPTIMAL_BIN_SELECTION(1));
437 radeon_opt_set_context_reg(sctx, R_028060_DB_DFSM_CONTROL,
438 SI_TRACKED_DB_DFSM_CONTROL,
439 S_028060_PUNCHOUT_MODE(punchout_mode));
440 }