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targets/dri: update scons build to handle __driDriverGetExtensions_vmwgfx
[mesa.git] / src / gallium / drivers / radeonsi / si_state_draw.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Christian König <christian.koenig@amd.com>
25 */
26
27 #include "si_pipe.h"
28 #include "si_shader.h"
29 #include "../radeon/r600_cs.h"
30 #include "sid.h"
31
32 #include "util/u_blitter.h"
33 #include "util/u_format.h"
34 #include "util/u_index_modify.h"
35 #include "util/u_memory.h"
36 #include "util/u_upload_mgr.h"
37
38 /*
39 * Shaders
40 */
41
42 static void si_pipe_shader_es(struct pipe_context *ctx, struct si_pipe_shader *shader)
43 {
44 struct si_context *sctx = (struct si_context *)ctx;
45 struct si_pm4_state *pm4;
46 unsigned num_sgprs, num_user_sgprs;
47 unsigned vgpr_comp_cnt;
48 uint64_t va;
49
50 si_pm4_delete_state(sctx, es, shader->pm4);
51 pm4 = shader->pm4 = si_pm4_alloc_state(sctx);
52
53 if (pm4 == NULL)
54 return;
55
56 va = r600_resource_va(ctx->screen, (void *)shader->bo);
57 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_DATA);
58
59 vgpr_comp_cnt = shader->shader.uses_instanceid ? 3 : 0;
60
61 num_user_sgprs = SI_VS_NUM_USER_SGPR;
62 num_sgprs = shader->num_sgprs;
63 /* One SGPR after user SGPRs is pre-loaded with es2gs_offset */
64 if ((num_user_sgprs + 1) > num_sgprs) {
65 /* Last 2 reserved SGPRs are used for VCC */
66 num_sgprs = num_user_sgprs + 1 + 2;
67 }
68 assert(num_sgprs <= 104);
69
70 si_pm4_set_reg(pm4, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8);
71 si_pm4_set_reg(pm4, R_00B324_SPI_SHADER_PGM_HI_ES, va >> 40);
72 si_pm4_set_reg(pm4, R_00B328_SPI_SHADER_PGM_RSRC1_ES,
73 S_00B328_VGPRS((shader->num_vgprs - 1) / 4) |
74 S_00B328_SGPRS((num_sgprs - 1) / 8) |
75 S_00B328_VGPR_COMP_CNT(vgpr_comp_cnt));
76 si_pm4_set_reg(pm4, R_00B32C_SPI_SHADER_PGM_RSRC2_ES,
77 S_00B32C_USER_SGPR(num_user_sgprs));
78
79 sctx->b.flags |= R600_CONTEXT_INV_SHADER_CACHE;
80 }
81
82 static void si_pipe_shader_gs(struct pipe_context *ctx, struct si_pipe_shader *shader)
83 {
84 struct si_context *sctx = (struct si_context *)ctx;
85 unsigned gs_vert_itemsize = shader->shader.noutput * (16 >> 2);
86 unsigned gs_max_vert_out = shader->shader.gs_max_out_vertices;
87 unsigned gsvs_itemsize = gs_vert_itemsize * gs_max_vert_out;
88 unsigned cut_mode;
89 struct si_pm4_state *pm4;
90 unsigned num_sgprs, num_user_sgprs;
91 uint64_t va;
92
93 /* The GSVS_RING_ITEMSIZE register takes 15 bits */
94 assert(gsvs_itemsize < (1 << 15));
95
96 si_pm4_delete_state(sctx, gs, shader->pm4);
97 pm4 = shader->pm4 = si_pm4_alloc_state(sctx);
98
99 if (pm4 == NULL)
100 return;
101
102 if (gs_max_vert_out <= 128) {
103 cut_mode = V_028A40_GS_CUT_128;
104 } else if (gs_max_vert_out <= 256) {
105 cut_mode = V_028A40_GS_CUT_256;
106 } else if (gs_max_vert_out <= 512) {
107 cut_mode = V_028A40_GS_CUT_512;
108 } else {
109 assert(gs_max_vert_out <= 1024);
110 cut_mode = V_028A40_GS_CUT_1024;
111 }
112
113 si_pm4_set_reg(pm4, R_028A40_VGT_GS_MODE,
114 S_028A40_MODE(V_028A40_GS_SCENARIO_G) |
115 S_028A40_CUT_MODE(cut_mode)|
116 S_028A40_ES_WRITE_OPTIMIZE(1) |
117 S_028A40_GS_WRITE_OPTIMIZE(1));
118
119 si_pm4_set_reg(pm4, R_028A60_VGT_GSVS_RING_OFFSET_1, gsvs_itemsize);
120 si_pm4_set_reg(pm4, R_028A64_VGT_GSVS_RING_OFFSET_2, gsvs_itemsize);
121 si_pm4_set_reg(pm4, R_028A68_VGT_GSVS_RING_OFFSET_3, gsvs_itemsize);
122
123 si_pm4_set_reg(pm4, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
124 shader->shader.nparam * (16 >> 2));
125 si_pm4_set_reg(pm4, R_028AB0_VGT_GSVS_RING_ITEMSIZE, gsvs_itemsize);
126
127 si_pm4_set_reg(pm4, R_028B38_VGT_GS_MAX_VERT_OUT, gs_max_vert_out);
128
129 si_pm4_set_reg(pm4, R_028B5C_VGT_GS_VERT_ITEMSIZE, gs_vert_itemsize);
130
131 va = r600_resource_va(ctx->screen, (void *)shader->bo);
132 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_DATA);
133 si_pm4_set_reg(pm4, R_00B220_SPI_SHADER_PGM_LO_GS, va >> 8);
134 si_pm4_set_reg(pm4, R_00B224_SPI_SHADER_PGM_HI_GS, va >> 40);
135
136 num_user_sgprs = SI_GS_NUM_USER_SGPR;
137 num_sgprs = shader->num_sgprs;
138 /* Two SGPRs after user SGPRs are pre-loaded with gs2vs_offset, gs_wave_id */
139 if ((num_user_sgprs + 2) > num_sgprs) {
140 /* Last 2 reserved SGPRs are used for VCC */
141 num_sgprs = num_user_sgprs + 2 + 2;
142 }
143 assert(num_sgprs <= 104);
144
145 si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS,
146 S_00B228_VGPRS((shader->num_vgprs - 1) / 4) |
147 S_00B228_SGPRS((num_sgprs - 1) / 8));
148 si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS,
149 S_00B22C_USER_SGPR(num_user_sgprs));
150
151 sctx->b.flags |= R600_CONTEXT_INV_SHADER_CACHE;
152 }
153
154 static void si_pipe_shader_vs(struct pipe_context *ctx, struct si_pipe_shader *shader)
155 {
156 struct si_context *sctx = (struct si_context *)ctx;
157 struct si_pm4_state *pm4;
158 unsigned num_sgprs, num_user_sgprs;
159 unsigned nparams, i, vgpr_comp_cnt;
160 uint64_t va;
161
162 si_pm4_delete_state(sctx, vs, shader->pm4);
163 pm4 = shader->pm4 = si_pm4_alloc_state(sctx);
164
165 if (pm4 == NULL)
166 return;
167
168 va = r600_resource_va(ctx->screen, (void *)shader->bo);
169 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_DATA);
170
171 vgpr_comp_cnt = shader->shader.uses_instanceid ? 3 : 0;
172
173 num_user_sgprs = SI_VS_NUM_USER_SGPR;
174 num_sgprs = shader->num_sgprs;
175 if (num_user_sgprs > num_sgprs) {
176 /* Last 2 reserved SGPRs are used for VCC */
177 num_sgprs = num_user_sgprs + 2;
178 }
179 assert(num_sgprs <= 104);
180
181 /* Certain attributes (position, psize, etc.) don't count as params.
182 * VS is required to export at least one param and r600_shader_from_tgsi()
183 * takes care of adding a dummy export.
184 */
185 for (nparams = 0, i = 0 ; i < shader->shader.noutput; i++) {
186 switch (shader->shader.output[i].name) {
187 case TGSI_SEMANTIC_CLIPVERTEX:
188 case TGSI_SEMANTIC_POSITION:
189 case TGSI_SEMANTIC_PSIZE:
190 break;
191 default:
192 nparams++;
193 }
194 }
195 if (nparams < 1)
196 nparams = 1;
197
198 si_pm4_set_reg(pm4, R_0286C4_SPI_VS_OUT_CONFIG,
199 S_0286C4_VS_EXPORT_COUNT(nparams - 1));
200
201 si_pm4_set_reg(pm4, R_02870C_SPI_SHADER_POS_FORMAT,
202 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
203 S_02870C_POS1_EXPORT_FORMAT(shader->shader.nr_pos_exports > 1 ?
204 V_02870C_SPI_SHADER_4COMP :
205 V_02870C_SPI_SHADER_NONE) |
206 S_02870C_POS2_EXPORT_FORMAT(shader->shader.nr_pos_exports > 2 ?
207 V_02870C_SPI_SHADER_4COMP :
208 V_02870C_SPI_SHADER_NONE) |
209 S_02870C_POS3_EXPORT_FORMAT(shader->shader.nr_pos_exports > 3 ?
210 V_02870C_SPI_SHADER_4COMP :
211 V_02870C_SPI_SHADER_NONE));
212
213 si_pm4_set_reg(pm4, R_00B120_SPI_SHADER_PGM_LO_VS, va >> 8);
214 si_pm4_set_reg(pm4, R_00B124_SPI_SHADER_PGM_HI_VS, va >> 40);
215 si_pm4_set_reg(pm4, R_00B128_SPI_SHADER_PGM_RSRC1_VS,
216 S_00B128_VGPRS((shader->num_vgprs - 1) / 4) |
217 S_00B128_SGPRS((num_sgprs - 1) / 8) |
218 S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt));
219 si_pm4_set_reg(pm4, R_00B12C_SPI_SHADER_PGM_RSRC2_VS,
220 S_00B12C_USER_SGPR(num_user_sgprs) |
221 S_00B12C_SO_BASE0_EN(!!shader->selector->so.stride[0]) |
222 S_00B12C_SO_BASE1_EN(!!shader->selector->so.stride[1]) |
223 S_00B12C_SO_BASE2_EN(!!shader->selector->so.stride[2]) |
224 S_00B12C_SO_BASE3_EN(!!shader->selector->so.stride[3]) |
225 S_00B12C_SO_EN(!!shader->selector->so.num_outputs));
226
227 sctx->b.flags |= R600_CONTEXT_INV_SHADER_CACHE;
228 }
229
230 static void si_pipe_shader_ps(struct pipe_context *ctx, struct si_pipe_shader *shader)
231 {
232 struct si_context *sctx = (struct si_context *)ctx;
233 struct si_pm4_state *pm4;
234 unsigned i, spi_ps_in_control, db_shader_control;
235 unsigned num_sgprs, num_user_sgprs;
236 unsigned spi_baryc_cntl = 0, spi_ps_input_ena;
237 uint64_t va;
238
239 si_pm4_delete_state(sctx, ps, shader->pm4);
240 pm4 = shader->pm4 = si_pm4_alloc_state(sctx);
241
242 if (pm4 == NULL)
243 return;
244
245 db_shader_control = S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z) |
246 S_02880C_ALPHA_TO_MASK_DISABLE(sctx->framebuffer.cb0_is_integer);
247
248 for (i = 0; i < shader->shader.ninput; i++) {
249 switch (shader->shader.input[i].name) {
250 case TGSI_SEMANTIC_POSITION:
251 if (shader->shader.input[i].centroid) {
252 /* SPI_BARYC_CNTL.POS_FLOAT_LOCATION
253 * Possible vaules:
254 * 0 -> Position = pixel center (default)
255 * 1 -> Position = pixel centroid
256 * 2 -> Position = iterated sample number XXX:
257 * What does this mean?
258 */
259 spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(1);
260 }
261 /* Fall through */
262 case TGSI_SEMANTIC_FACE:
263 continue;
264 }
265 }
266
267 db_shader_control |= shader->db_shader_control;
268
269 if (shader->shader.uses_kill || shader->key.ps.alpha_func != PIPE_FUNC_ALWAYS)
270 db_shader_control |= S_02880C_KILL_ENABLE(1);
271
272 if (sctx->b.chip_class >= CIK)
273 db_shader_control |=
274 S_02880C_CONSERVATIVE_Z_EXPORT(shader->shader.ps_conservative_z);
275
276 spi_ps_in_control = S_0286D8_NUM_INTERP(shader->shader.nparam) |
277 S_0286D8_BC_OPTIMIZE_DISABLE(1);
278
279 si_pm4_set_reg(pm4, R_0286E0_SPI_BARYC_CNTL, spi_baryc_cntl);
280 spi_ps_input_ena = shader->spi_ps_input_ena;
281 /* we need to enable at least one of them, otherwise we hang the GPU */
282 assert(G_0286CC_PERSP_SAMPLE_ENA(spi_ps_input_ena) ||
283 G_0286CC_PERSP_CENTER_ENA(spi_ps_input_ena) ||
284 G_0286CC_PERSP_CENTROID_ENA(spi_ps_input_ena) ||
285 G_0286CC_PERSP_PULL_MODEL_ENA(spi_ps_input_ena) ||
286 G_0286CC_LINEAR_SAMPLE_ENA(spi_ps_input_ena) ||
287 G_0286CC_LINEAR_CENTER_ENA(spi_ps_input_ena) ||
288 G_0286CC_LINEAR_CENTROID_ENA(spi_ps_input_ena) ||
289 G_0286CC_LINE_STIPPLE_TEX_ENA(spi_ps_input_ena));
290
291 si_pm4_set_reg(pm4, R_0286CC_SPI_PS_INPUT_ENA, spi_ps_input_ena);
292 si_pm4_set_reg(pm4, R_0286D0_SPI_PS_INPUT_ADDR, spi_ps_input_ena);
293 si_pm4_set_reg(pm4, R_0286D8_SPI_PS_IN_CONTROL, spi_ps_in_control);
294
295 si_pm4_set_reg(pm4, R_028710_SPI_SHADER_Z_FORMAT, shader->spi_shader_z_format);
296 si_pm4_set_reg(pm4, R_028714_SPI_SHADER_COL_FORMAT,
297 shader->spi_shader_col_format);
298 si_pm4_set_reg(pm4, R_02823C_CB_SHADER_MASK, shader->cb_shader_mask);
299
300 va = r600_resource_va(ctx->screen, (void *)shader->bo);
301 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_DATA);
302 si_pm4_set_reg(pm4, R_00B020_SPI_SHADER_PGM_LO_PS, va >> 8);
303 si_pm4_set_reg(pm4, R_00B024_SPI_SHADER_PGM_HI_PS, va >> 40);
304
305 num_user_sgprs = SI_PS_NUM_USER_SGPR;
306 num_sgprs = shader->num_sgprs;
307 /* One SGPR after user SGPRs is pre-loaded with {prim_mask, lds_offset} */
308 if ((num_user_sgprs + 1) > num_sgprs) {
309 /* Last 2 reserved SGPRs are used for VCC */
310 num_sgprs = num_user_sgprs + 1 + 2;
311 }
312 assert(num_sgprs <= 104);
313
314 si_pm4_set_reg(pm4, R_00B028_SPI_SHADER_PGM_RSRC1_PS,
315 S_00B028_VGPRS((shader->num_vgprs - 1) / 4) |
316 S_00B028_SGPRS((num_sgprs - 1) / 8));
317 si_pm4_set_reg(pm4, R_00B02C_SPI_SHADER_PGM_RSRC2_PS,
318 S_00B02C_EXTRA_LDS_SIZE(shader->lds_size) |
319 S_00B02C_USER_SGPR(num_user_sgprs));
320
321 si_pm4_set_reg(pm4, R_02880C_DB_SHADER_CONTROL, db_shader_control);
322
323 shader->cb0_is_integer = sctx->framebuffer.cb0_is_integer;
324 shader->sprite_coord_enable = sctx->sprite_coord_enable;
325 sctx->b.flags |= R600_CONTEXT_INV_SHADER_CACHE;
326 }
327
328 /*
329 * Drawing
330 */
331
332 static unsigned si_conv_pipe_prim(unsigned pprim)
333 {
334 static const unsigned prim_conv[] = {
335 [PIPE_PRIM_POINTS] = V_008958_DI_PT_POINTLIST,
336 [PIPE_PRIM_LINES] = V_008958_DI_PT_LINELIST,
337 [PIPE_PRIM_LINE_LOOP] = V_008958_DI_PT_LINELOOP,
338 [PIPE_PRIM_LINE_STRIP] = V_008958_DI_PT_LINESTRIP,
339 [PIPE_PRIM_TRIANGLES] = V_008958_DI_PT_TRILIST,
340 [PIPE_PRIM_TRIANGLE_STRIP] = V_008958_DI_PT_TRISTRIP,
341 [PIPE_PRIM_TRIANGLE_FAN] = V_008958_DI_PT_TRIFAN,
342 [PIPE_PRIM_QUADS] = V_008958_DI_PT_QUADLIST,
343 [PIPE_PRIM_QUAD_STRIP] = V_008958_DI_PT_QUADSTRIP,
344 [PIPE_PRIM_POLYGON] = V_008958_DI_PT_POLYGON,
345 [PIPE_PRIM_LINES_ADJACENCY] = V_008958_DI_PT_LINELIST_ADJ,
346 [PIPE_PRIM_LINE_STRIP_ADJACENCY] = V_008958_DI_PT_LINESTRIP_ADJ,
347 [PIPE_PRIM_TRIANGLES_ADJACENCY] = V_008958_DI_PT_TRILIST_ADJ,
348 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY] = V_008958_DI_PT_TRISTRIP_ADJ
349 };
350 unsigned result = prim_conv[pprim];
351 if (result == ~0) {
352 R600_ERR("unsupported primitive type %d\n", pprim);
353 }
354 return result;
355 }
356
357 static unsigned si_conv_prim_to_gs_out(unsigned mode)
358 {
359 static const int prim_conv[] = {
360 [PIPE_PRIM_POINTS] = V_028A6C_OUTPRIM_TYPE_POINTLIST,
361 [PIPE_PRIM_LINES] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
362 [PIPE_PRIM_LINE_LOOP] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
363 [PIPE_PRIM_LINE_STRIP] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
364 [PIPE_PRIM_TRIANGLES] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
365 [PIPE_PRIM_TRIANGLE_STRIP] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
366 [PIPE_PRIM_TRIANGLE_FAN] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
367 [PIPE_PRIM_QUADS] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
368 [PIPE_PRIM_QUAD_STRIP] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
369 [PIPE_PRIM_POLYGON] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
370 [PIPE_PRIM_LINES_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
371 [PIPE_PRIM_LINE_STRIP_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
372 [PIPE_PRIM_TRIANGLES_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
373 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
374 };
375 assert(mode < Elements(prim_conv));
376
377 return prim_conv[mode];
378 }
379
380 static bool si_update_draw_info_state(struct si_context *sctx,
381 const struct pipe_draw_info *info,
382 const struct pipe_index_buffer *ib)
383 {
384 struct si_pm4_state *pm4 = si_pm4_alloc_state(sctx);
385 struct si_shader *vs = si_get_vs_state(sctx);
386 unsigned prim = si_conv_pipe_prim(info->mode);
387 unsigned gs_out_prim =
388 si_conv_prim_to_gs_out(sctx->gs_shader ?
389 sctx->gs_shader->current->shader.gs_output_prim :
390 info->mode);
391 unsigned ls_mask = 0;
392
393 if (pm4 == NULL)
394 return false;
395
396 if (prim == ~0) {
397 FREE(pm4);
398 return false;
399 }
400
401 if (sctx->b.chip_class >= CIK) {
402 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
403 bool wd_switch_on_eop = prim == V_008958_DI_PT_POLYGON ||
404 prim == V_008958_DI_PT_LINELOOP ||
405 prim == V_008958_DI_PT_TRIFAN ||
406 prim == V_008958_DI_PT_TRISTRIP_ADJ ||
407 info->primitive_restart ||
408 (rs ? rs->line_stipple_enable : false);
409 /* If the WD switch is false, the IA switch must be false too. */
410 bool ia_switch_on_eop = wd_switch_on_eop;
411
412 si_pm4_set_reg(pm4, R_028B74_VGT_DISPATCH_DRAW_INDEX,
413 ib->index_size == 4 ? 0xFC000000 : 0xFC00);
414
415 si_pm4_cmd_begin(pm4, PKT3_DRAW_PREAMBLE);
416 si_pm4_cmd_add(pm4, prim); /* VGT_PRIMITIVE_TYPE */
417 si_pm4_cmd_add(pm4, /* IA_MULTI_VGT_PARAM */
418 S_028AA8_SWITCH_ON_EOP(ia_switch_on_eop) |
419 S_028AA8_PARTIAL_VS_WAVE_ON(1) |
420 S_028AA8_PRIMGROUP_SIZE(63) |
421 S_028AA8_WD_SWITCH_ON_EOP(wd_switch_on_eop));
422 si_pm4_cmd_add(pm4, 0); /* VGT_LS_HS_CONFIG */
423 si_pm4_cmd_end(pm4, false);
424 } else {
425 si_pm4_set_reg(pm4, R_008958_VGT_PRIMITIVE_TYPE, prim);
426 }
427
428 si_pm4_set_reg(pm4, R_028A6C_VGT_GS_OUT_PRIM_TYPE, gs_out_prim);
429 si_pm4_set_reg(pm4, R_028408_VGT_INDX_OFFSET,
430 info->indexed ? info->index_bias : info->start);
431 si_pm4_set_reg(pm4, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, info->restart_index);
432 si_pm4_set_reg(pm4, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, info->primitive_restart);
433 si_pm4_set_reg(pm4, SI_SGPR_START_INSTANCE * 4 +
434 (sctx->gs_shader ? R_00B330_SPI_SHADER_USER_DATA_ES_0 :
435 R_00B130_SPI_SHADER_USER_DATA_VS_0),
436 info->start_instance);
437
438 if (prim == V_008958_DI_PT_LINELIST)
439 ls_mask = 1;
440 else if (prim == V_008958_DI_PT_LINESTRIP)
441 ls_mask = 2;
442 si_pm4_set_reg(pm4, R_028A0C_PA_SC_LINE_STIPPLE,
443 S_028A0C_AUTO_RESET_CNTL(ls_mask) |
444 sctx->pa_sc_line_stipple);
445
446 if (info->mode == PIPE_PRIM_QUADS || info->mode == PIPE_PRIM_QUAD_STRIP || info->mode == PIPE_PRIM_POLYGON) {
447 si_pm4_set_reg(pm4, R_028814_PA_SU_SC_MODE_CNTL,
448 S_028814_PROVOKING_VTX_LAST(1) | sctx->pa_su_sc_mode_cntl);
449 } else {
450 si_pm4_set_reg(pm4, R_028814_PA_SU_SC_MODE_CNTL, sctx->pa_su_sc_mode_cntl);
451 }
452 si_pm4_set_reg(pm4, R_02881C_PA_CL_VS_OUT_CNTL,
453 S_02881C_USE_VTX_POINT_SIZE(vs->vs_out_point_size) |
454 S_02881C_USE_VTX_EDGE_FLAG(vs->vs_out_edgeflag) |
455 S_02881C_USE_VTX_RENDER_TARGET_INDX(vs->vs_out_layer) |
456 S_02881C_VS_OUT_CCDIST0_VEC_ENA((vs->clip_dist_write & 0x0F) != 0) |
457 S_02881C_VS_OUT_CCDIST1_VEC_ENA((vs->clip_dist_write & 0xF0) != 0) |
458 S_02881C_VS_OUT_MISC_VEC_ENA(vs->vs_out_misc_write) |
459 (sctx->queued.named.rasterizer->clip_plane_enable &
460 vs->clip_dist_write));
461 si_pm4_set_reg(pm4, R_028810_PA_CL_CLIP_CNTL,
462 sctx->queued.named.rasterizer->pa_cl_clip_cntl |
463 (vs->clip_dist_write ? 0 :
464 sctx->queued.named.rasterizer->clip_plane_enable & 0x3F));
465
466 si_pm4_set_state(sctx, draw_info, pm4);
467 return true;
468 }
469
470 static void si_update_spi_map(struct si_context *sctx)
471 {
472 struct si_shader *ps = &sctx->ps_shader->current->shader;
473 struct si_shader *vs = si_get_vs_state(sctx);
474 struct si_pm4_state *pm4 = si_pm4_alloc_state(sctx);
475 unsigned i, j, tmp;
476
477 for (i = 0; i < ps->ninput; i++) {
478 unsigned name = ps->input[i].name;
479 unsigned param_offset = ps->input[i].param_offset;
480
481 if (name == TGSI_SEMANTIC_POSITION)
482 /* Read from preloaded VGPRs, not parameters */
483 continue;
484
485 bcolor:
486 tmp = 0;
487
488 if (ps->input[i].interpolate == TGSI_INTERPOLATE_CONSTANT ||
489 (ps->input[i].interpolate == TGSI_INTERPOLATE_COLOR &&
490 sctx->ps_shader->current->key.ps.flatshade)) {
491 tmp |= S_028644_FLAT_SHADE(1);
492 }
493
494 if (name == TGSI_SEMANTIC_GENERIC &&
495 sctx->sprite_coord_enable & (1 << ps->input[i].sid)) {
496 tmp |= S_028644_PT_SPRITE_TEX(1);
497 }
498
499 for (j = 0; j < vs->noutput; j++) {
500 if (name == vs->output[j].name &&
501 ps->input[i].sid == vs->output[j].sid) {
502 tmp |= S_028644_OFFSET(vs->output[j].param_offset);
503 break;
504 }
505 }
506
507 if (j == vs->noutput) {
508 /* No corresponding output found, load defaults into input */
509 tmp |= S_028644_OFFSET(0x20);
510 }
511
512 si_pm4_set_reg(pm4,
513 R_028644_SPI_PS_INPUT_CNTL_0 + param_offset * 4,
514 tmp);
515
516 if (name == TGSI_SEMANTIC_COLOR &&
517 sctx->ps_shader->current->key.ps.color_two_side) {
518 name = TGSI_SEMANTIC_BCOLOR;
519 param_offset++;
520 goto bcolor;
521 }
522 }
523
524 si_pm4_set_state(sctx, spi, pm4);
525 }
526
527 /* Initialize state related to ESGS / GSVS ring buffers */
528 static void si_init_gs_rings(struct si_context *sctx)
529 {
530 unsigned size = 128 * 1024;
531
532 assert(!sctx->gs_rings);
533 sctx->gs_rings = si_pm4_alloc_state(sctx);
534
535 sctx->esgs_ring.buffer =
536 pipe_buffer_create(sctx->b.b.screen, PIPE_BIND_CUSTOM,
537 PIPE_USAGE_DEFAULT, size);
538 sctx->esgs_ring.buffer_size = size;
539
540 size = 64 * 1024 * 1024;
541 sctx->gsvs_ring.buffer =
542 pipe_buffer_create(sctx->b.b.screen, PIPE_BIND_CUSTOM,
543 PIPE_USAGE_DEFAULT, size);
544 sctx->gsvs_ring.buffer_size = size;
545
546 if (sctx->b.chip_class >= CIK) {
547 si_pm4_set_reg(sctx->gs_rings, R_030900_VGT_ESGS_RING_SIZE,
548 sctx->esgs_ring.buffer_size / 256);
549 si_pm4_set_reg(sctx->gs_rings, R_030904_VGT_GSVS_RING_SIZE,
550 sctx->gsvs_ring.buffer_size / 256);
551 } else {
552 si_pm4_set_reg(sctx->gs_rings, R_0088C8_VGT_ESGS_RING_SIZE,
553 sctx->esgs_ring.buffer_size / 256);
554 si_pm4_set_reg(sctx->gs_rings, R_0088CC_VGT_GSVS_RING_SIZE,
555 sctx->gsvs_ring.buffer_size / 256);
556 }
557
558 si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_VERTEX, SI_RING_ESGS,
559 &sctx->esgs_ring, 0, sctx->esgs_ring.buffer_size,
560 true, true, 4, 64);
561 si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_GEOMETRY, SI_RING_ESGS,
562 &sctx->esgs_ring, 0, sctx->esgs_ring.buffer_size,
563 false, false, 0, 0);
564 si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_VERTEX, SI_RING_GSVS,
565 &sctx->gsvs_ring, 0, sctx->gsvs_ring.buffer_size,
566 false, false, 0, 0);
567 }
568
569 static void si_update_derived_state(struct si_context *sctx)
570 {
571 struct pipe_context * ctx = (struct pipe_context*)sctx;
572
573 if (!sctx->blitter->running) {
574 /* Flush depth textures which need to be flushed. */
575 for (int i = 0; i < SI_NUM_SHADERS; i++) {
576 if (sctx->samplers[i].depth_texture_mask) {
577 si_flush_depth_textures(sctx, &sctx->samplers[i]);
578 }
579 if (sctx->samplers[i].compressed_colortex_mask) {
580 si_decompress_color_textures(sctx, &sctx->samplers[i]);
581 }
582 }
583 }
584
585 if (sctx->gs_shader) {
586 si_shader_select(ctx, sctx->gs_shader);
587
588 if (!sctx->gs_shader->current->pm4) {
589 si_pipe_shader_gs(ctx, sctx->gs_shader->current);
590 si_pipe_shader_vs(ctx,
591 sctx->gs_shader->current->gs_copy_shader);
592 }
593
594 si_pm4_bind_state(sctx, gs, sctx->gs_shader->current->pm4);
595 si_pm4_bind_state(sctx, vs, sctx->gs_shader->current->gs_copy_shader->pm4);
596
597 sctx->b.streamout.stride_in_dw = sctx->gs_shader->so.stride;
598
599 si_shader_select(ctx, sctx->vs_shader);
600
601 if (!sctx->vs_shader->current->pm4)
602 si_pipe_shader_es(ctx, sctx->vs_shader->current);
603
604 si_pm4_bind_state(sctx, es, sctx->vs_shader->current->pm4);
605
606 if (!sctx->gs_rings)
607 si_init_gs_rings(sctx);
608 if (sctx->emitted.named.gs_rings != sctx->gs_rings)
609 sctx->b.flags |= R600_CONTEXT_VGT_FLUSH;
610 si_pm4_bind_state(sctx, gs_rings, sctx->gs_rings);
611
612 si_set_ring_buffer(ctx, PIPE_SHADER_GEOMETRY, SI_RING_GSVS,
613 &sctx->gsvs_ring,
614 sctx->gs_shader->current->shader.gs_max_out_vertices *
615 sctx->gs_shader->current->shader.noutput * 16,
616 64, true, true, 4, 16);
617
618 if (!sctx->gs_on) {
619 sctx->gs_on = si_pm4_alloc_state(sctx);
620
621 si_pm4_set_reg(sctx->gs_on, R_028B54_VGT_SHADER_STAGES_EN,
622 S_028B54_ES_EN(V_028B54_ES_STAGE_REAL) |
623 S_028B54_GS_EN(1) |
624 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER));
625 }
626 si_pm4_bind_state(sctx, gs_onoff, sctx->gs_on);
627 } else {
628 si_shader_select(ctx, sctx->vs_shader);
629
630 if (!sctx->vs_shader->current->pm4)
631 si_pipe_shader_vs(ctx, sctx->vs_shader->current);
632
633 si_pm4_bind_state(sctx, vs, sctx->vs_shader->current->pm4);
634
635 sctx->b.streamout.stride_in_dw = sctx->vs_shader->so.stride;
636
637 if (!sctx->gs_off) {
638 sctx->gs_off = si_pm4_alloc_state(sctx);
639
640 si_pm4_set_reg(sctx->gs_off, R_028A40_VGT_GS_MODE, 0);
641 si_pm4_set_reg(sctx->gs_off, R_028B54_VGT_SHADER_STAGES_EN, 0);
642 }
643 si_pm4_bind_state(sctx, gs_onoff, sctx->gs_off);
644 si_pm4_bind_state(sctx, gs_rings, NULL);
645 si_pm4_bind_state(sctx, gs, NULL);
646 si_pm4_bind_state(sctx, es, NULL);
647 }
648
649 si_shader_select(ctx, sctx->ps_shader);
650
651 if (!sctx->ps_shader->current->pm4 ||
652 sctx->ps_shader->current->cb0_is_integer != sctx->framebuffer.cb0_is_integer)
653 si_pipe_shader_ps(ctx, sctx->ps_shader->current);
654
655 si_pm4_bind_state(sctx, ps, sctx->ps_shader->current->pm4);
656
657 if (si_pm4_state_changed(sctx, ps) || si_pm4_state_changed(sctx, vs)) {
658 /* XXX: Emitting the PS state even when only the VS changed
659 * fixes random failures with piglit glsl-max-varyings.
660 * Not sure why...
661 */
662 sctx->emitted.named.ps = NULL;
663 si_update_spi_map(sctx);
664 }
665 }
666
667 static void si_vertex_buffer_update(struct si_context *sctx)
668 {
669 struct pipe_context *ctx = &sctx->b.b;
670 struct si_pm4_state *pm4 = si_pm4_alloc_state(sctx);
671 bool bound[PIPE_MAX_ATTRIBS] = {};
672 unsigned i, count;
673 uint64_t va;
674
675 sctx->b.flags |= R600_CONTEXT_INV_TEX_CACHE;
676
677 count = sctx->vertex_elements->count;
678 assert(count <= 256 / 4);
679
680 si_pm4_sh_data_begin(pm4);
681 for (i = 0 ; i < count; i++) {
682 struct pipe_vertex_element *ve = &sctx->vertex_elements->elements[i];
683 struct pipe_vertex_buffer *vb;
684 struct r600_resource *rbuffer;
685 unsigned offset;
686
687 if (ve->vertex_buffer_index >= sctx->nr_vertex_buffers)
688 continue;
689
690 vb = &sctx->vertex_buffer[ve->vertex_buffer_index];
691 rbuffer = (struct r600_resource*)vb->buffer;
692 if (rbuffer == NULL)
693 continue;
694
695 offset = 0;
696 offset += vb->buffer_offset;
697 offset += ve->src_offset;
698
699 va = r600_resource_va(ctx->screen, (void*)rbuffer);
700 va += offset;
701
702 /* Fill in T# buffer resource description */
703 si_pm4_sh_data_add(pm4, va & 0xFFFFFFFF);
704 si_pm4_sh_data_add(pm4, (S_008F04_BASE_ADDRESS_HI(va >> 32) |
705 S_008F04_STRIDE(vb->stride)));
706 if (vb->stride)
707 /* Round up by rounding down and adding 1 */
708 si_pm4_sh_data_add(pm4,
709 (vb->buffer->width0 - offset -
710 util_format_get_blocksize(ve->src_format)) /
711 vb->stride + 1);
712 else
713 si_pm4_sh_data_add(pm4, vb->buffer->width0 - offset);
714 si_pm4_sh_data_add(pm4, sctx->vertex_elements->rsrc_word3[i]);
715
716 if (!bound[ve->vertex_buffer_index]) {
717 si_pm4_add_bo(pm4, rbuffer, RADEON_USAGE_READ,
718 RADEON_PRIO_SHADER_BUFFER_RO);
719 bound[ve->vertex_buffer_index] = true;
720 }
721 }
722 si_pm4_sh_data_end(pm4, sctx->gs_shader ?
723 R_00B330_SPI_SHADER_USER_DATA_ES_0 :
724 R_00B130_SPI_SHADER_USER_DATA_VS_0,
725 SI_SGPR_VERTEX_BUFFER);
726 si_pm4_set_state(sctx, vertex_buffers, pm4);
727 }
728
729 static void si_state_draw(struct si_context *sctx,
730 const struct pipe_draw_info *info,
731 const struct pipe_index_buffer *ib)
732 {
733 struct si_pm4_state *pm4 = si_pm4_alloc_state(sctx);
734
735 if (pm4 == NULL)
736 return;
737
738 /* queries need some special values
739 * (this is non-zero if any query is active) */
740 if (sctx->b.num_occlusion_queries > 0) {
741 if (sctx->b.chip_class >= CIK) {
742 si_pm4_set_reg(pm4, R_028004_DB_COUNT_CONTROL,
743 S_028004_PERFECT_ZPASS_COUNTS(1) |
744 S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples) |
745 S_028004_ZPASS_ENABLE(1) |
746 S_028004_SLICE_EVEN_ENABLE(1) |
747 S_028004_SLICE_ODD_ENABLE(1));
748 } else {
749 si_pm4_set_reg(pm4, R_028004_DB_COUNT_CONTROL,
750 S_028004_PERFECT_ZPASS_COUNTS(1) |
751 S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples));
752 }
753 }
754
755 if (info->count_from_stream_output) {
756 struct r600_so_target *t =
757 (struct r600_so_target*)info->count_from_stream_output;
758 uint64_t va = r600_resource_va(&sctx->screen->b.b,
759 &t->buf_filled_size->b.b);
760 va += t->buf_filled_size_offset;
761
762 si_pm4_set_reg(pm4, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE,
763 t->stride_in_dw);
764
765 si_pm4_cmd_begin(pm4, PKT3_COPY_DATA);
766 si_pm4_cmd_add(pm4,
767 COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
768 COPY_DATA_DST_SEL(COPY_DATA_REG) |
769 COPY_DATA_WR_CONFIRM);
770 si_pm4_cmd_add(pm4, va); /* src address lo */
771 si_pm4_cmd_add(pm4, va >> 32UL); /* src address hi */
772 si_pm4_cmd_add(pm4, R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE >> 2);
773 si_pm4_cmd_add(pm4, 0); /* unused */
774 si_pm4_add_bo(pm4, t->buf_filled_size, RADEON_USAGE_READ,
775 RADEON_PRIO_MIN);
776 si_pm4_cmd_end(pm4, true);
777 }
778
779 /* draw packet */
780 si_pm4_cmd_begin(pm4, PKT3_INDEX_TYPE);
781 if (ib->index_size == 4) {
782 si_pm4_cmd_add(pm4, V_028A7C_VGT_INDEX_32 | (SI_BIG_ENDIAN ?
783 V_028A7C_VGT_DMA_SWAP_32_BIT : 0));
784 } else {
785 si_pm4_cmd_add(pm4, V_028A7C_VGT_INDEX_16 | (SI_BIG_ENDIAN ?
786 V_028A7C_VGT_DMA_SWAP_16_BIT : 0));
787 }
788 si_pm4_cmd_end(pm4, sctx->b.predicate_drawing);
789
790 si_pm4_cmd_begin(pm4, PKT3_NUM_INSTANCES);
791 si_pm4_cmd_add(pm4, info->instance_count);
792 si_pm4_cmd_end(pm4, sctx->b.predicate_drawing);
793
794 if (info->indexed) {
795 uint32_t max_size = (ib->buffer->width0 - ib->offset) /
796 sctx->index_buffer.index_size;
797 uint64_t va;
798 va = r600_resource_va(&sctx->screen->b.b, ib->buffer);
799 va += ib->offset;
800
801 si_pm4_add_bo(pm4, (struct r600_resource *)ib->buffer, RADEON_USAGE_READ,
802 RADEON_PRIO_MIN);
803 si_cmd_draw_index_2(pm4, max_size, va, info->count,
804 V_0287F0_DI_SRC_SEL_DMA,
805 sctx->b.predicate_drawing);
806 } else {
807 uint32_t initiator = V_0287F0_DI_SRC_SEL_AUTO_INDEX;
808 initiator |= S_0287F0_USE_OPAQUE(!!info->count_from_stream_output);
809 si_cmd_draw_index_auto(pm4, info->count, initiator, sctx->b.predicate_drawing);
810 }
811
812 si_pm4_set_state(sctx, draw, pm4);
813 }
814
815 void si_emit_cache_flush(struct r600_common_context *sctx, struct r600_atom *atom)
816 {
817 struct radeon_winsys_cs *cs = sctx->rings.gfx.cs;
818 uint32_t cp_coher_cntl = 0;
819
820 /* XXX SI flushes both ICACHE and KCACHE if either flag is set.
821 * XXX CIK shouldn't have this issue. Test CIK before separating the flags
822 * XXX to ensure there is no regression. Also find out if there is another
823 * XXX way to flush either ICACHE or KCACHE but not both for SI. */
824 if (sctx->flags & (R600_CONTEXT_INV_SHADER_CACHE |
825 R600_CONTEXT_INV_CONST_CACHE)) {
826 cp_coher_cntl |= S_0085F0_SH_ICACHE_ACTION_ENA(1) |
827 S_0085F0_SH_KCACHE_ACTION_ENA(1);
828 }
829 if (sctx->flags & (R600_CONTEXT_INV_TEX_CACHE |
830 R600_CONTEXT_STREAMOUT_FLUSH)) {
831 cp_coher_cntl |= S_0085F0_TC_ACTION_ENA(1) |
832 S_0085F0_TCL1_ACTION_ENA(1);
833 }
834 if (sctx->flags & R600_CONTEXT_FLUSH_AND_INV_CB) {
835 cp_coher_cntl |= S_0085F0_CB_ACTION_ENA(1) |
836 S_0085F0_CB0_DEST_BASE_ENA(1) |
837 S_0085F0_CB1_DEST_BASE_ENA(1) |
838 S_0085F0_CB2_DEST_BASE_ENA(1) |
839 S_0085F0_CB3_DEST_BASE_ENA(1) |
840 S_0085F0_CB4_DEST_BASE_ENA(1) |
841 S_0085F0_CB5_DEST_BASE_ENA(1) |
842 S_0085F0_CB6_DEST_BASE_ENA(1) |
843 S_0085F0_CB7_DEST_BASE_ENA(1);
844 }
845 if (sctx->flags & R600_CONTEXT_FLUSH_AND_INV_DB) {
846 cp_coher_cntl |= S_0085F0_DB_ACTION_ENA(1) |
847 S_0085F0_DB_DEST_BASE_ENA(1);
848 }
849
850 if (cp_coher_cntl) {
851 if (sctx->chip_class >= CIK) {
852 radeon_emit(cs, PKT3(PKT3_ACQUIRE_MEM, 5, 0));
853 radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */
854 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
855 radeon_emit(cs, 0xff); /* CP_COHER_SIZE_HI */
856 radeon_emit(cs, 0); /* CP_COHER_BASE */
857 radeon_emit(cs, 0); /* CP_COHER_BASE_HI */
858 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
859 } else {
860 radeon_emit(cs, PKT3(PKT3_SURFACE_SYNC, 3, 0));
861 radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */
862 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
863 radeon_emit(cs, 0); /* CP_COHER_BASE */
864 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
865 }
866 }
867
868 if (sctx->flags & R600_CONTEXT_FLUSH_AND_INV_CB_META) {
869 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
870 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_META) | EVENT_INDEX(0));
871 }
872 if (sctx->flags & R600_CONTEXT_FLUSH_AND_INV_DB_META) {
873 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
874 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_DB_META) | EVENT_INDEX(0));
875 }
876
877 if (sctx->flags & (R600_CONTEXT_WAIT_3D_IDLE |
878 R600_CONTEXT_PS_PARTIAL_FLUSH)) {
879 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
880 radeon_emit(cs, EVENT_TYPE(V_028A90_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
881 } else if (sctx->flags & R600_CONTEXT_STREAMOUT_FLUSH) {
882 /* Needed if streamout buffers are going to be used as a source. */
883 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
884 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
885 }
886
887 if (sctx->flags & R600_CONTEXT_VGT_FLUSH) {
888 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
889 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
890 }
891
892 sctx->flags = 0;
893 }
894
895 const struct r600_atom si_atom_cache_flush = { si_emit_cache_flush, 13 }; /* number of CS dwords */
896
897 void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info)
898 {
899 struct si_context *sctx = (struct si_context *)ctx;
900 struct pipe_index_buffer ib = {};
901 uint32_t i;
902
903 if (!info->count && (info->indexed || !info->count_from_stream_output))
904 return;
905
906 if (!sctx->ps_shader || !sctx->vs_shader)
907 return;
908
909 si_update_derived_state(sctx);
910 si_vertex_buffer_update(sctx);
911
912 if (info->indexed) {
913 /* Initialize the index buffer struct. */
914 pipe_resource_reference(&ib.buffer, sctx->index_buffer.buffer);
915 ib.user_buffer = sctx->index_buffer.user_buffer;
916 ib.index_size = sctx->index_buffer.index_size;
917 ib.offset = sctx->index_buffer.offset + info->start * ib.index_size;
918
919 /* Translate or upload, if needed. */
920 if (ib.index_size == 1) {
921 struct pipe_resource *out_buffer = NULL;
922 unsigned out_offset;
923 void *ptr;
924
925 u_upload_alloc(sctx->b.uploader, 0, info->count * 2,
926 &out_offset, &out_buffer, &ptr);
927
928 util_shorten_ubyte_elts_to_userptr(
929 &sctx->b.b, &ib, 0, ib.offset, info->count, ptr);
930
931 pipe_resource_reference(&ib.buffer, NULL);
932 ib.user_buffer = NULL;
933 ib.buffer = out_buffer;
934 ib.offset = out_offset;
935 ib.index_size = 2;
936 }
937
938 if (ib.user_buffer && !ib.buffer) {
939 u_upload_data(sctx->b.uploader, 0, info->count * ib.index_size,
940 ib.user_buffer, &ib.offset, &ib.buffer);
941 }
942 }
943
944 if (!si_update_draw_info_state(sctx, info, &ib))
945 return;
946
947 si_state_draw(sctx, info, &ib);
948
949 sctx->pm4_dirty_cdwords += si_pm4_dirty_dw(sctx);
950
951 /* Check flush flags. */
952 if (sctx->b.flags)
953 sctx->atoms.s.cache_flush->dirty = true;
954
955 si_need_cs_space(sctx, 0, TRUE);
956
957 /* Emit states. */
958 for (i = 0; i < SI_NUM_ATOMS(sctx); i++) {
959 if (sctx->atoms.array[i]->dirty) {
960 sctx->atoms.array[i]->emit(&sctx->b, sctx->atoms.array[i]);
961 sctx->atoms.array[i]->dirty = false;
962 }
963 }
964
965 si_pm4_emit_dirty(sctx);
966 sctx->pm4_dirty_cdwords = 0;
967
968 #if SI_TRACE_CS
969 if (sctx->screen->b.trace_bo) {
970 si_trace_emit(sctx);
971 }
972 #endif
973
974 /* Set the depth buffer as dirty. */
975 if (sctx->framebuffer.state.zsbuf) {
976 struct pipe_surface *surf = sctx->framebuffer.state.zsbuf;
977 struct r600_texture *rtex = (struct r600_texture *)surf->texture;
978
979 rtex->dirty_level_mask |= 1 << surf->u.tex.level;
980 }
981 if (sctx->framebuffer.compressed_cb_mask) {
982 struct pipe_surface *surf;
983 struct r600_texture *rtex;
984 unsigned mask = sctx->framebuffer.compressed_cb_mask;
985
986 do {
987 unsigned i = u_bit_scan(&mask);
988 surf = sctx->framebuffer.state.cbufs[i];
989 rtex = (struct r600_texture*)surf->texture;
990
991 rtex->dirty_level_mask |= 1 << surf->u.tex.level;
992 } while (mask);
993 }
994
995 pipe_resource_reference(&ib.buffer, NULL);
996 sctx->b.num_draw_calls++;
997 }