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radeonsi: apply a multi-wave workgroup SPI bug workaround to affected CIK chips
[mesa.git] / src / gallium / drivers / radeonsi / si_state_draw.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Christian König <christian.koenig@amd.com>
25 */
26
27 #include "si_pipe.h"
28 #include "radeon/r600_cs.h"
29 #include "sid.h"
30
31 #include "util/u_index_modify.h"
32 #include "util/u_upload_mgr.h"
33 #include "util/u_prim.h"
34
35 static unsigned si_conv_pipe_prim(unsigned mode)
36 {
37 static const unsigned prim_conv[] = {
38 [PIPE_PRIM_POINTS] = V_008958_DI_PT_POINTLIST,
39 [PIPE_PRIM_LINES] = V_008958_DI_PT_LINELIST,
40 [PIPE_PRIM_LINE_LOOP] = V_008958_DI_PT_LINELOOP,
41 [PIPE_PRIM_LINE_STRIP] = V_008958_DI_PT_LINESTRIP,
42 [PIPE_PRIM_TRIANGLES] = V_008958_DI_PT_TRILIST,
43 [PIPE_PRIM_TRIANGLE_STRIP] = V_008958_DI_PT_TRISTRIP,
44 [PIPE_PRIM_TRIANGLE_FAN] = V_008958_DI_PT_TRIFAN,
45 [PIPE_PRIM_QUADS] = V_008958_DI_PT_QUADLIST,
46 [PIPE_PRIM_QUAD_STRIP] = V_008958_DI_PT_QUADSTRIP,
47 [PIPE_PRIM_POLYGON] = V_008958_DI_PT_POLYGON,
48 [PIPE_PRIM_LINES_ADJACENCY] = V_008958_DI_PT_LINELIST_ADJ,
49 [PIPE_PRIM_LINE_STRIP_ADJACENCY] = V_008958_DI_PT_LINESTRIP_ADJ,
50 [PIPE_PRIM_TRIANGLES_ADJACENCY] = V_008958_DI_PT_TRILIST_ADJ,
51 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY] = V_008958_DI_PT_TRISTRIP_ADJ,
52 [PIPE_PRIM_PATCHES] = V_008958_DI_PT_PATCH,
53 [R600_PRIM_RECTANGLE_LIST] = V_008958_DI_PT_RECTLIST
54 };
55 assert(mode < ARRAY_SIZE(prim_conv));
56 return prim_conv[mode];
57 }
58
59 static unsigned si_conv_prim_to_gs_out(unsigned mode)
60 {
61 static const int prim_conv[] = {
62 [PIPE_PRIM_POINTS] = V_028A6C_OUTPRIM_TYPE_POINTLIST,
63 [PIPE_PRIM_LINES] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
64 [PIPE_PRIM_LINE_LOOP] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
65 [PIPE_PRIM_LINE_STRIP] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
66 [PIPE_PRIM_TRIANGLES] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
67 [PIPE_PRIM_TRIANGLE_STRIP] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
68 [PIPE_PRIM_TRIANGLE_FAN] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
69 [PIPE_PRIM_QUADS] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
70 [PIPE_PRIM_QUAD_STRIP] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
71 [PIPE_PRIM_POLYGON] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
72 [PIPE_PRIM_LINES_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
73 [PIPE_PRIM_LINE_STRIP_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
74 [PIPE_PRIM_TRIANGLES_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
75 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
76 [PIPE_PRIM_PATCHES] = V_028A6C_OUTPRIM_TYPE_POINTLIST,
77 [R600_PRIM_RECTANGLE_LIST] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
78 };
79 assert(mode < ARRAY_SIZE(prim_conv));
80
81 return prim_conv[mode];
82 }
83
84 /**
85 * This calculates the LDS size for tessellation shaders (VS, TCS, TES).
86 * LS.LDS_SIZE is shared by all 3 shader stages.
87 *
88 * The information about LDS and other non-compile-time parameters is then
89 * written to userdata SGPRs.
90 */
91 static void si_emit_derived_tess_state(struct si_context *sctx,
92 const struct pipe_draw_info *info,
93 unsigned *num_patches)
94 {
95 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
96 struct si_shader_ctx_state *ls = &sctx->vs_shader;
97 /* The TES pointer will only be used for sctx->last_tcs.
98 * It would be wrong to think that TCS = TES. */
99 struct si_shader_selector *tcs =
100 sctx->tcs_shader.cso ? sctx->tcs_shader.cso : sctx->tes_shader.cso;
101 unsigned tes_sh_base = sctx->shader_userdata.sh_base[PIPE_SHADER_TESS_EVAL];
102 unsigned num_tcs_input_cp = info->vertices_per_patch;
103 unsigned num_tcs_output_cp, num_tcs_inputs, num_tcs_outputs;
104 unsigned num_tcs_patch_outputs;
105 unsigned input_vertex_size, output_vertex_size, pervertex_output_patch_size;
106 unsigned input_patch_size, output_patch_size, output_patch0_offset;
107 unsigned perpatch_output_offset, lds_size, ls_rsrc2;
108 unsigned tcs_in_layout, tcs_out_layout, tcs_out_offsets;
109 unsigned offchip_layout, hardware_lds_size, ls_hs_config;
110
111 if (sctx->last_ls == ls->current &&
112 sctx->last_tcs == tcs &&
113 sctx->last_tes_sh_base == tes_sh_base &&
114 sctx->last_num_tcs_input_cp == num_tcs_input_cp) {
115 *num_patches = sctx->last_num_patches;
116 return;
117 }
118
119 sctx->last_ls = ls->current;
120 sctx->last_tcs = tcs;
121 sctx->last_tes_sh_base = tes_sh_base;
122 sctx->last_num_tcs_input_cp = num_tcs_input_cp;
123
124 /* This calculates how shader inputs and outputs among VS, TCS, and TES
125 * are laid out in LDS. */
126 num_tcs_inputs = util_last_bit64(ls->cso->outputs_written);
127
128 if (sctx->tcs_shader.cso) {
129 num_tcs_outputs = util_last_bit64(tcs->outputs_written);
130 num_tcs_output_cp = tcs->info.properties[TGSI_PROPERTY_TCS_VERTICES_OUT];
131 num_tcs_patch_outputs = util_last_bit64(tcs->patch_outputs_written);
132 } else {
133 /* No TCS. Route varyings from LS to TES. */
134 num_tcs_outputs = num_tcs_inputs;
135 num_tcs_output_cp = num_tcs_input_cp;
136 num_tcs_patch_outputs = 2; /* TESSINNER + TESSOUTER */
137 }
138
139 input_vertex_size = num_tcs_inputs * 16;
140 output_vertex_size = num_tcs_outputs * 16;
141
142 input_patch_size = num_tcs_input_cp * input_vertex_size;
143
144 pervertex_output_patch_size = num_tcs_output_cp * output_vertex_size;
145 output_patch_size = pervertex_output_patch_size + num_tcs_patch_outputs * 16;
146
147 /* Ensure that we only need one wave per SIMD so we don't need to check
148 * resource usage. Also ensures that the number of tcs in and out
149 * vertices per threadgroup are at most 256.
150 */
151 *num_patches = 64 / MAX2(num_tcs_input_cp, num_tcs_output_cp) * 4;
152
153 /* Make sure that the data fits in LDS. This assumes the shaders only
154 * use LDS for the inputs and outputs.
155 */
156 hardware_lds_size = sctx->b.chip_class >= CIK ? 65536 : 32768;
157 *num_patches = MIN2(*num_patches, hardware_lds_size / (input_patch_size +
158 output_patch_size));
159
160 /* Make sure the output data fits in the offchip buffer */
161 *num_patches = MIN2(*num_patches,
162 (sctx->screen->tess_offchip_block_dw_size * 4) /
163 output_patch_size);
164
165 /* Not necessary for correctness, but improves performance. The
166 * specific value is taken from the proprietary driver.
167 */
168 *num_patches = MIN2(*num_patches, 40);
169 sctx->last_num_patches = *num_patches;
170
171 output_patch0_offset = input_patch_size * *num_patches;
172 perpatch_output_offset = output_patch0_offset + pervertex_output_patch_size;
173
174 lds_size = output_patch0_offset + output_patch_size * *num_patches;
175 ls_rsrc2 = ls->current->config.rsrc2;
176
177 if (sctx->b.chip_class >= CIK) {
178 assert(lds_size <= 65536);
179 lds_size = align(lds_size, 512) / 512;
180 } else {
181 assert(lds_size <= 32768);
182 lds_size = align(lds_size, 256) / 256;
183 }
184 si_multiwave_lds_size_workaround(sctx->screen, &lds_size);
185 ls_rsrc2 |= S_00B52C_LDS_SIZE(lds_size);
186
187 /* Due to a hw bug, RSRC2_LS must be written twice with another
188 * LS register written in between. */
189 if (sctx->b.chip_class == CIK && sctx->b.family != CHIP_HAWAII)
190 radeon_set_sh_reg(cs, R_00B52C_SPI_SHADER_PGM_RSRC2_LS, ls_rsrc2);
191 radeon_set_sh_reg_seq(cs, R_00B528_SPI_SHADER_PGM_RSRC1_LS, 2);
192 radeon_emit(cs, ls->current->config.rsrc1);
193 radeon_emit(cs, ls_rsrc2);
194
195 /* Compute userdata SGPRs. */
196 assert(((input_vertex_size / 4) & ~0xff) == 0);
197 assert(((output_vertex_size / 4) & ~0xff) == 0);
198 assert(((input_patch_size / 4) & ~0x1fff) == 0);
199 assert(((output_patch_size / 4) & ~0x1fff) == 0);
200 assert(((output_patch0_offset / 16) & ~0xffff) == 0);
201 assert(((perpatch_output_offset / 16) & ~0xffff) == 0);
202 assert(num_tcs_input_cp <= 32);
203 assert(num_tcs_output_cp <= 32);
204
205 tcs_in_layout = (input_patch_size / 4) |
206 ((input_vertex_size / 4) << 13);
207 tcs_out_layout = (output_patch_size / 4) |
208 ((output_vertex_size / 4) << 13);
209 tcs_out_offsets = (output_patch0_offset / 16) |
210 ((perpatch_output_offset / 16) << 16);
211 offchip_layout = (pervertex_output_patch_size * *num_patches << 16) |
212 (num_tcs_output_cp << 9) | *num_patches;
213
214 /* Set them for LS. */
215 radeon_set_sh_reg(cs,
216 R_00B530_SPI_SHADER_USER_DATA_LS_0 + SI_SGPR_LS_OUT_LAYOUT * 4,
217 tcs_in_layout);
218
219 /* Set them for TCS. */
220 radeon_set_sh_reg_seq(cs,
221 R_00B430_SPI_SHADER_USER_DATA_HS_0 + SI_SGPR_TCS_OFFCHIP_LAYOUT * 4, 4);
222 radeon_emit(cs, offchip_layout);
223 radeon_emit(cs, tcs_out_offsets);
224 radeon_emit(cs, tcs_out_layout | (num_tcs_input_cp << 26));
225 radeon_emit(cs, tcs_in_layout);
226
227 /* Set them for TES. */
228 radeon_set_sh_reg_seq(cs, tes_sh_base + SI_SGPR_TCS_OFFCHIP_LAYOUT * 4, 1);
229 radeon_emit(cs, offchip_layout);
230
231 ls_hs_config = S_028B58_NUM_PATCHES(*num_patches) |
232 S_028B58_HS_NUM_INPUT_CP(num_tcs_input_cp) |
233 S_028B58_HS_NUM_OUTPUT_CP(num_tcs_output_cp);
234
235 if (sctx->b.chip_class >= CIK)
236 radeon_set_context_reg_idx(cs, R_028B58_VGT_LS_HS_CONFIG, 2,
237 ls_hs_config);
238 else
239 radeon_set_context_reg(cs, R_028B58_VGT_LS_HS_CONFIG,
240 ls_hs_config);
241 }
242
243 static unsigned si_num_prims_for_vertices(const struct pipe_draw_info *info)
244 {
245 switch (info->mode) {
246 case PIPE_PRIM_PATCHES:
247 return info->count / info->vertices_per_patch;
248 case R600_PRIM_RECTANGLE_LIST:
249 return info->count / 3;
250 default:
251 return u_prims_for_vertices(info->mode, info->count);
252 }
253 }
254
255 static unsigned si_get_ia_multi_vgt_param(struct si_context *sctx,
256 const struct pipe_draw_info *info,
257 unsigned num_patches)
258 {
259 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
260 unsigned prim = info->mode;
261 unsigned primgroup_size = 128; /* recommended without a GS */
262 unsigned max_primgroup_in_wave = 2;
263
264 /* SWITCH_ON_EOP(0) is always preferable. */
265 bool wd_switch_on_eop = false;
266 bool ia_switch_on_eop = false;
267 bool ia_switch_on_eoi = false;
268 bool partial_vs_wave = false;
269 bool partial_es_wave = false;
270
271 if (sctx->gs_shader.cso)
272 primgroup_size = 64; /* recommended with a GS */
273
274 if (sctx->tes_shader.cso) {
275 /* primgroup_size must be set to a multiple of NUM_PATCHES */
276 primgroup_size = num_patches;
277
278 /* SWITCH_ON_EOI must be set if PrimID is used. */
279 if ((sctx->tcs_shader.cso && sctx->tcs_shader.cso->info.uses_primid) ||
280 sctx->tes_shader.cso->info.uses_primid)
281 ia_switch_on_eoi = true;
282
283 /* Bug with tessellation and GS on Bonaire and older 2 SE chips. */
284 if ((sctx->b.family == CHIP_TAHITI ||
285 sctx->b.family == CHIP_PITCAIRN ||
286 sctx->b.family == CHIP_BONAIRE) &&
287 sctx->gs_shader.cso)
288 partial_vs_wave = true;
289
290 /* Needed for 028B6C_DISTRIBUTION_MODE != 0 */
291 if (sctx->screen->has_distributed_tess) {
292 if (sctx->gs_shader.cso)
293 partial_es_wave = true;
294 else
295 partial_vs_wave = true;
296 }
297 }
298
299 /* This is a hardware requirement. */
300 if ((rs && rs->line_stipple_enable) ||
301 (sctx->b.screen->debug_flags & DBG_SWITCH_ON_EOP)) {
302 ia_switch_on_eop = true;
303 wd_switch_on_eop = true;
304 }
305
306 if (sctx->b.chip_class >= CIK) {
307 /* WD_SWITCH_ON_EOP has no effect on GPUs with less than
308 * 4 shader engines. Set 1 to pass the assertion below.
309 * The other cases are hardware requirements.
310 *
311 * Polaris supports primitive restart with WD_SWITCH_ON_EOP=0
312 * for points, line strips, and tri strips.
313 */
314 if (sctx->b.screen->info.max_se < 4 ||
315 prim == PIPE_PRIM_POLYGON ||
316 prim == PIPE_PRIM_LINE_LOOP ||
317 prim == PIPE_PRIM_TRIANGLE_FAN ||
318 prim == PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY ||
319 (info->primitive_restart &&
320 (sctx->b.family < CHIP_POLARIS10 ||
321 (prim != PIPE_PRIM_POINTS &&
322 prim != PIPE_PRIM_LINE_STRIP &&
323 prim != PIPE_PRIM_TRIANGLE_STRIP))) ||
324 info->count_from_stream_output)
325 wd_switch_on_eop = true;
326
327 /* Hawaii hangs if instancing is enabled and WD_SWITCH_ON_EOP is 0.
328 * We don't know that for indirect drawing, so treat it as
329 * always problematic. */
330 if (sctx->b.family == CHIP_HAWAII &&
331 (info->indirect || info->instance_count > 1))
332 wd_switch_on_eop = true;
333
334 /* Performance recommendation for 4 SE Gfx7-8 parts if
335 * instances are smaller than a primgroup.
336 * Assume indirect draws always use small instances.
337 * This is needed for good VS wave utilization.
338 */
339 if (sctx->b.chip_class <= VI &&
340 sctx->b.screen->info.max_se >= 4 &&
341 (info->indirect ||
342 (info->instance_count > 1 &&
343 si_num_prims_for_vertices(info) < primgroup_size)))
344 wd_switch_on_eop = true;
345
346 /* Required on CIK and later. */
347 if (sctx->b.screen->info.max_se > 2 && !wd_switch_on_eop)
348 ia_switch_on_eoi = true;
349
350 /* Required by Hawaii and, for some special cases, by VI. */
351 if (ia_switch_on_eoi &&
352 (sctx->b.family == CHIP_HAWAII ||
353 (sctx->b.chip_class == VI &&
354 (sctx->gs_shader.cso || max_primgroup_in_wave != 2))))
355 partial_vs_wave = true;
356
357 /* Instancing bug on Bonaire. */
358 if (sctx->b.family == CHIP_BONAIRE && ia_switch_on_eoi &&
359 (info->indirect || info->instance_count > 1))
360 partial_vs_wave = true;
361
362 /* GS hw bug with single-primitive instances and SWITCH_ON_EOI.
363 * The hw doc says all multi-SE chips are affected, but Vulkan
364 * only applies it to Hawaii. Do what Vulkan does.
365 */
366 if (sctx->b.family == CHIP_HAWAII &&
367 sctx->gs_shader.cso &&
368 ia_switch_on_eoi &&
369 (info->indirect ||
370 (info->instance_count > 1 &&
371 si_num_prims_for_vertices(info) <= 1)))
372 sctx->b.flags |= SI_CONTEXT_VGT_FLUSH;
373
374
375 /* If the WD switch is false, the IA switch must be false too. */
376 assert(wd_switch_on_eop || !ia_switch_on_eop);
377 }
378
379 /* If SWITCH_ON_EOI is set, PARTIAL_ES_WAVE must be set too. */
380 if (ia_switch_on_eoi)
381 partial_es_wave = true;
382
383 /* GS requirement. */
384 if (SI_GS_PER_ES / primgroup_size >= sctx->screen->gs_table_depth - 3)
385 partial_es_wave = true;
386
387 return S_028AA8_SWITCH_ON_EOP(ia_switch_on_eop) |
388 S_028AA8_SWITCH_ON_EOI(ia_switch_on_eoi) |
389 S_028AA8_PARTIAL_VS_WAVE_ON(partial_vs_wave) |
390 S_028AA8_PARTIAL_ES_WAVE_ON(partial_es_wave) |
391 S_028AA8_PRIMGROUP_SIZE(primgroup_size - 1) |
392 S_028AA8_WD_SWITCH_ON_EOP(sctx->b.chip_class >= CIK ? wd_switch_on_eop : 0) |
393 S_028AA8_MAX_PRIMGRP_IN_WAVE(sctx->b.chip_class >= VI ?
394 max_primgroup_in_wave : 0);
395 }
396
397 static void si_emit_scratch_reloc(struct si_context *sctx)
398 {
399 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
400
401 if (!sctx->emit_scratch_reloc)
402 return;
403
404 radeon_set_context_reg(cs, R_0286E8_SPI_TMPRING_SIZE,
405 sctx->spi_tmpring_size);
406
407 if (sctx->scratch_buffer) {
408 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
409 sctx->scratch_buffer, RADEON_USAGE_READWRITE,
410 RADEON_PRIO_SCRATCH_BUFFER);
411
412 }
413 sctx->emit_scratch_reloc = false;
414 }
415
416 /* rast_prim is the primitive type after GS. */
417 static void si_emit_rasterizer_prim_state(struct si_context *sctx)
418 {
419 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
420 unsigned rast_prim = sctx->current_rast_prim;
421 struct si_state_rasterizer *rs = sctx->emitted.named.rasterizer;
422
423 /* Skip this if not rendering lines. */
424 if (rast_prim != PIPE_PRIM_LINES &&
425 rast_prim != PIPE_PRIM_LINE_LOOP &&
426 rast_prim != PIPE_PRIM_LINE_STRIP &&
427 rast_prim != PIPE_PRIM_LINES_ADJACENCY &&
428 rast_prim != PIPE_PRIM_LINE_STRIP_ADJACENCY)
429 return;
430
431 if (rast_prim == sctx->last_rast_prim &&
432 rs->pa_sc_line_stipple == sctx->last_sc_line_stipple)
433 return;
434
435 /* For lines, reset the stipple pattern at each primitive. Otherwise,
436 * reset the stipple pattern at each packet (line strips, line loops).
437 */
438 radeon_set_context_reg(cs, R_028A0C_PA_SC_LINE_STIPPLE,
439 rs->pa_sc_line_stipple |
440 S_028A0C_AUTO_RESET_CNTL(rast_prim == PIPE_PRIM_LINES ? 1 : 2));
441
442 sctx->last_rast_prim = rast_prim;
443 sctx->last_sc_line_stipple = rs->pa_sc_line_stipple;
444 }
445
446 static void si_emit_draw_registers(struct si_context *sctx,
447 const struct pipe_draw_info *info)
448 {
449 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
450 unsigned prim = si_conv_pipe_prim(info->mode);
451 unsigned gs_out_prim = si_conv_prim_to_gs_out(sctx->current_rast_prim);
452 unsigned ia_multi_vgt_param, num_patches = 0;
453
454 /* Polaris needs different VTX_REUSE_DEPTH settings depending on
455 * whether the "fractional odd" tessellation spacing is used.
456 */
457 if (sctx->b.family >= CHIP_POLARIS10) {
458 struct si_shader_selector *tes = sctx->tes_shader.cso;
459 unsigned vtx_reuse_depth = 30;
460
461 if (tes &&
462 tes->info.properties[TGSI_PROPERTY_TES_SPACING] ==
463 PIPE_TESS_SPACING_FRACTIONAL_ODD)
464 vtx_reuse_depth = 14;
465
466 if (vtx_reuse_depth != sctx->last_vtx_reuse_depth) {
467 radeon_set_context_reg(cs, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
468 vtx_reuse_depth);
469 sctx->last_vtx_reuse_depth = vtx_reuse_depth;
470 }
471 }
472
473 if (sctx->tes_shader.cso)
474 si_emit_derived_tess_state(sctx, info, &num_patches);
475
476 ia_multi_vgt_param = si_get_ia_multi_vgt_param(sctx, info, num_patches);
477
478 /* Draw state. */
479 if (ia_multi_vgt_param != sctx->last_multi_vgt_param) {
480 if (sctx->b.chip_class >= CIK)
481 radeon_set_context_reg_idx(cs, R_028AA8_IA_MULTI_VGT_PARAM, 1, ia_multi_vgt_param);
482 else
483 radeon_set_context_reg(cs, R_028AA8_IA_MULTI_VGT_PARAM, ia_multi_vgt_param);
484
485 sctx->last_multi_vgt_param = ia_multi_vgt_param;
486 }
487 if (prim != sctx->last_prim) {
488 if (sctx->b.chip_class >= CIK)
489 radeon_set_uconfig_reg_idx(cs, R_030908_VGT_PRIMITIVE_TYPE, 1, prim);
490 else
491 radeon_set_config_reg(cs, R_008958_VGT_PRIMITIVE_TYPE, prim);
492
493 sctx->last_prim = prim;
494 }
495
496 if (gs_out_prim != sctx->last_gs_out_prim) {
497 radeon_set_context_reg(cs, R_028A6C_VGT_GS_OUT_PRIM_TYPE, gs_out_prim);
498 sctx->last_gs_out_prim = gs_out_prim;
499 }
500
501 /* Primitive restart. */
502 if (info->primitive_restart != sctx->last_primitive_restart_en) {
503 radeon_set_context_reg(cs, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, info->primitive_restart);
504 sctx->last_primitive_restart_en = info->primitive_restart;
505
506 }
507 if (info->primitive_restart &&
508 (info->restart_index != sctx->last_restart_index ||
509 sctx->last_restart_index == SI_RESTART_INDEX_UNKNOWN)) {
510 radeon_set_context_reg(cs, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
511 info->restart_index);
512 sctx->last_restart_index = info->restart_index;
513 }
514 }
515
516 static void si_emit_draw_packets(struct si_context *sctx,
517 const struct pipe_draw_info *info,
518 const struct pipe_index_buffer *ib)
519 {
520 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
521 unsigned sh_base_reg = sctx->shader_userdata.sh_base[PIPE_SHADER_VERTEX];
522 bool render_cond_bit = sctx->b.render_cond && !sctx->b.render_cond_force_off;
523 uint32_t index_max_size = 0;
524 uint64_t index_va = 0;
525
526 if (info->count_from_stream_output) {
527 struct r600_so_target *t =
528 (struct r600_so_target*)info->count_from_stream_output;
529 uint64_t va = t->buf_filled_size->gpu_address +
530 t->buf_filled_size_offset;
531
532 radeon_set_context_reg(cs, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE,
533 t->stride_in_dw);
534
535 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
536 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
537 COPY_DATA_DST_SEL(COPY_DATA_REG) |
538 COPY_DATA_WR_CONFIRM);
539 radeon_emit(cs, va); /* src address lo */
540 radeon_emit(cs, va >> 32); /* src address hi */
541 radeon_emit(cs, R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE >> 2);
542 radeon_emit(cs, 0); /* unused */
543
544 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
545 t->buf_filled_size, RADEON_USAGE_READ,
546 RADEON_PRIO_SO_FILLED_SIZE);
547 }
548
549 /* draw packet */
550 if (info->indexed) {
551 if (ib->index_size != sctx->last_index_size) {
552 radeon_emit(cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
553
554 /* index type */
555 switch (ib->index_size) {
556 case 1:
557 radeon_emit(cs, V_028A7C_VGT_INDEX_8);
558 break;
559 case 2:
560 radeon_emit(cs, V_028A7C_VGT_INDEX_16 |
561 (SI_BIG_ENDIAN && sctx->b.chip_class <= CIK ?
562 V_028A7C_VGT_DMA_SWAP_16_BIT : 0));
563 break;
564 case 4:
565 radeon_emit(cs, V_028A7C_VGT_INDEX_32 |
566 (SI_BIG_ENDIAN && sctx->b.chip_class <= CIK ?
567 V_028A7C_VGT_DMA_SWAP_32_BIT : 0));
568 break;
569 default:
570 assert(!"unreachable");
571 return;
572 }
573
574 sctx->last_index_size = ib->index_size;
575 }
576
577 index_max_size = (ib->buffer->width0 - ib->offset) /
578 ib->index_size;
579 index_va = r600_resource(ib->buffer)->gpu_address + ib->offset;
580
581 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
582 (struct r600_resource *)ib->buffer,
583 RADEON_USAGE_READ, RADEON_PRIO_INDEX_BUFFER);
584 } else {
585 /* On CI and later, non-indexed draws overwrite VGT_INDEX_TYPE,
586 * so the state must be re-emitted before the next indexed draw.
587 */
588 if (sctx->b.chip_class >= CIK)
589 sctx->last_index_size = -1;
590 }
591
592 if (!info->indirect) {
593 int base_vertex;
594
595 radeon_emit(cs, PKT3(PKT3_NUM_INSTANCES, 0, 0));
596 radeon_emit(cs, info->instance_count);
597
598 /* Base vertex and start instance. */
599 base_vertex = info->indexed ? info->index_bias : info->start;
600
601 if (base_vertex != sctx->last_base_vertex ||
602 sctx->last_base_vertex == SI_BASE_VERTEX_UNKNOWN ||
603 info->start_instance != sctx->last_start_instance ||
604 info->drawid != sctx->last_drawid ||
605 sh_base_reg != sctx->last_sh_base_reg) {
606 radeon_set_sh_reg_seq(cs, sh_base_reg + SI_SGPR_BASE_VERTEX * 4, 3);
607 radeon_emit(cs, base_vertex);
608 radeon_emit(cs, info->start_instance);
609 radeon_emit(cs, info->drawid);
610
611 sctx->last_base_vertex = base_vertex;
612 sctx->last_start_instance = info->start_instance;
613 sctx->last_drawid = info->drawid;
614 sctx->last_sh_base_reg = sh_base_reg;
615 }
616 } else {
617 uint64_t indirect_va = r600_resource(info->indirect)->gpu_address;
618
619 assert(indirect_va % 8 == 0);
620
621 si_invalidate_draw_sh_constants(sctx);
622
623 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
624 radeon_emit(cs, 1);
625 radeon_emit(cs, indirect_va);
626 radeon_emit(cs, indirect_va >> 32);
627
628 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
629 (struct r600_resource *)info->indirect,
630 RADEON_USAGE_READ, RADEON_PRIO_DRAW_INDIRECT);
631 }
632
633 if (info->indirect) {
634 unsigned di_src_sel = info->indexed ? V_0287F0_DI_SRC_SEL_DMA
635 : V_0287F0_DI_SRC_SEL_AUTO_INDEX;
636
637 assert(info->indirect_offset % 4 == 0);
638
639 if (info->indexed) {
640 radeon_emit(cs, PKT3(PKT3_INDEX_BASE, 1, 0));
641 radeon_emit(cs, index_va);
642 radeon_emit(cs, index_va >> 32);
643
644 radeon_emit(cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
645 radeon_emit(cs, index_max_size);
646 }
647
648 if (!sctx->screen->has_draw_indirect_multi) {
649 radeon_emit(cs, PKT3(info->indexed ? PKT3_DRAW_INDEX_INDIRECT
650 : PKT3_DRAW_INDIRECT,
651 3, render_cond_bit));
652 radeon_emit(cs, info->indirect_offset);
653 radeon_emit(cs, (sh_base_reg + SI_SGPR_BASE_VERTEX * 4 - SI_SH_REG_OFFSET) >> 2);
654 radeon_emit(cs, (sh_base_reg + SI_SGPR_START_INSTANCE * 4 - SI_SH_REG_OFFSET) >> 2);
655 radeon_emit(cs, di_src_sel);
656 } else {
657 uint64_t count_va = 0;
658
659 if (info->indirect_params) {
660 struct r600_resource *params_buf =
661 (struct r600_resource *)info->indirect_params;
662
663 radeon_add_to_buffer_list(
664 &sctx->b, &sctx->b.gfx, params_buf,
665 RADEON_USAGE_READ, RADEON_PRIO_DRAW_INDIRECT);
666
667 count_va = params_buf->gpu_address + info->indirect_params_offset;
668 }
669
670 radeon_emit(cs, PKT3(info->indexed ? PKT3_DRAW_INDEX_INDIRECT_MULTI :
671 PKT3_DRAW_INDIRECT_MULTI,
672 8, render_cond_bit));
673 radeon_emit(cs, info->indirect_offset);
674 radeon_emit(cs, (sh_base_reg + SI_SGPR_BASE_VERTEX * 4 - SI_SH_REG_OFFSET) >> 2);
675 radeon_emit(cs, (sh_base_reg + SI_SGPR_START_INSTANCE * 4 - SI_SH_REG_OFFSET) >> 2);
676 radeon_emit(cs, ((sh_base_reg + SI_SGPR_DRAWID * 4 - SI_SH_REG_OFFSET) >> 2) |
677 S_2C3_DRAW_INDEX_ENABLE(1) |
678 S_2C3_COUNT_INDIRECT_ENABLE(!!info->indirect_params));
679 radeon_emit(cs, info->indirect_count);
680 radeon_emit(cs, count_va);
681 radeon_emit(cs, count_va >> 32);
682 radeon_emit(cs, info->indirect_stride);
683 radeon_emit(cs, di_src_sel);
684 }
685 } else {
686 if (info->indexed) {
687 index_va += info->start * ib->index_size;
688
689 radeon_emit(cs, PKT3(PKT3_DRAW_INDEX_2, 4, render_cond_bit));
690 radeon_emit(cs, index_max_size);
691 radeon_emit(cs, index_va);
692 radeon_emit(cs, (index_va >> 32UL) & 0xFF);
693 radeon_emit(cs, info->count);
694 radeon_emit(cs, V_0287F0_DI_SRC_SEL_DMA);
695 } else {
696 radeon_emit(cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, render_cond_bit));
697 radeon_emit(cs, info->count);
698 radeon_emit(cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
699 S_0287F0_USE_OPAQUE(!!info->count_from_stream_output));
700 }
701 }
702 }
703
704 static void si_emit_surface_sync(struct r600_common_context *rctx,
705 unsigned cp_coher_cntl)
706 {
707 struct radeon_winsys_cs *cs = rctx->gfx.cs;
708
709 /* ACQUIRE_MEM is only required on a compute ring. */
710 radeon_emit(cs, PKT3(PKT3_SURFACE_SYNC, 3, 0));
711 radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */
712 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
713 radeon_emit(cs, 0); /* CP_COHER_BASE */
714 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
715 }
716
717 void si_emit_cache_flush(struct si_context *sctx)
718 {
719 struct r600_common_context *rctx = &sctx->b;
720 struct radeon_winsys_cs *cs = rctx->gfx.cs;
721 uint32_t cp_coher_cntl = 0;
722
723 /* SI has a bug that it always flushes ICACHE and KCACHE if either
724 * bit is set. An alternative way is to write SQC_CACHES, but that
725 * doesn't seem to work reliably. Since the bug doesn't affect
726 * correctness (it only does more work than necessary) and
727 * the performance impact is likely negligible, there is no plan
728 * to add a workaround for it.
729 */
730
731 if (rctx->flags & SI_CONTEXT_INV_ICACHE)
732 cp_coher_cntl |= S_0085F0_SH_ICACHE_ACTION_ENA(1);
733 if (rctx->flags & SI_CONTEXT_INV_SMEM_L1)
734 cp_coher_cntl |= S_0085F0_SH_KCACHE_ACTION_ENA(1);
735
736 if (rctx->flags & SI_CONTEXT_FLUSH_AND_INV_CB) {
737 cp_coher_cntl |= S_0085F0_CB_ACTION_ENA(1) |
738 S_0085F0_CB0_DEST_BASE_ENA(1) |
739 S_0085F0_CB1_DEST_BASE_ENA(1) |
740 S_0085F0_CB2_DEST_BASE_ENA(1) |
741 S_0085F0_CB3_DEST_BASE_ENA(1) |
742 S_0085F0_CB4_DEST_BASE_ENA(1) |
743 S_0085F0_CB5_DEST_BASE_ENA(1) |
744 S_0085F0_CB6_DEST_BASE_ENA(1) |
745 S_0085F0_CB7_DEST_BASE_ENA(1);
746
747 /* Necessary for DCC */
748 if (rctx->chip_class == VI)
749 r600_gfx_write_event_eop(rctx, V_028A90_FLUSH_AND_INV_CB_DATA_TS,
750 0, 0, NULL, 0, 0, 0);
751 }
752 if (rctx->flags & SI_CONTEXT_FLUSH_AND_INV_DB) {
753 cp_coher_cntl |= S_0085F0_DB_ACTION_ENA(1) |
754 S_0085F0_DB_DEST_BASE_ENA(1);
755 }
756
757 if (rctx->flags & SI_CONTEXT_FLUSH_AND_INV_CB_META) {
758 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
759 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_META) | EVENT_INDEX(0));
760 /* needed for wait for idle in SURFACE_SYNC */
761 assert(rctx->flags & SI_CONTEXT_FLUSH_AND_INV_CB);
762 }
763 if (rctx->flags & SI_CONTEXT_FLUSH_AND_INV_DB_META) {
764 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
765 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_DB_META) | EVENT_INDEX(0));
766 /* needed for wait for idle in SURFACE_SYNC */
767 assert(rctx->flags & SI_CONTEXT_FLUSH_AND_INV_DB);
768 }
769
770 /* Wait for shader engines to go idle.
771 * VS and PS waits are unnecessary if SURFACE_SYNC is going to wait
772 * for everything including CB/DB cache flushes.
773 */
774 if (!(rctx->flags & (SI_CONTEXT_FLUSH_AND_INV_CB |
775 SI_CONTEXT_FLUSH_AND_INV_DB))) {
776 if (rctx->flags & SI_CONTEXT_PS_PARTIAL_FLUSH) {
777 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
778 radeon_emit(cs, EVENT_TYPE(V_028A90_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
779 /* Only count explicit shader flushes, not implicit ones
780 * done by SURFACE_SYNC.
781 */
782 rctx->num_vs_flushes++;
783 rctx->num_ps_flushes++;
784 } else if (rctx->flags & SI_CONTEXT_VS_PARTIAL_FLUSH) {
785 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
786 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
787 rctx->num_vs_flushes++;
788 }
789 }
790
791 if (rctx->flags & SI_CONTEXT_CS_PARTIAL_FLUSH &&
792 sctx->compute_is_busy) {
793 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
794 radeon_emit(cs, EVENT_TYPE(V_028A90_CS_PARTIAL_FLUSH | EVENT_INDEX(4)));
795 rctx->num_cs_flushes++;
796 sctx->compute_is_busy = false;
797 }
798
799 /* VGT state synchronization. */
800 if (rctx->flags & SI_CONTEXT_VGT_FLUSH) {
801 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
802 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
803 }
804 if (rctx->flags & SI_CONTEXT_VGT_STREAMOUT_SYNC) {
805 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
806 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_STREAMOUT_SYNC) | EVENT_INDEX(0));
807 }
808
809 /* Make sure ME is idle (it executes most packets) before continuing.
810 * This prevents read-after-write hazards between PFP and ME.
811 */
812 if (cp_coher_cntl ||
813 (rctx->flags & (SI_CONTEXT_CS_PARTIAL_FLUSH |
814 SI_CONTEXT_INV_VMEM_L1 |
815 SI_CONTEXT_INV_GLOBAL_L2 |
816 SI_CONTEXT_WRITEBACK_GLOBAL_L2))) {
817 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
818 radeon_emit(cs, 0);
819 }
820
821 /* When one of the CP_COHER_CNTL.DEST_BASE flags is set, SURFACE_SYNC
822 * waits for idle. Therefore, it should be last. SURFACE_SYNC is done
823 * in PFP.
824 *
825 * cp_coher_cntl should contain all necessary flags except TC flags
826 * at this point.
827 *
828 * SI-CIK don't support L2 write-back.
829 */
830 if (rctx->flags & SI_CONTEXT_INV_GLOBAL_L2 ||
831 (rctx->chip_class <= CIK &&
832 (rctx->flags & SI_CONTEXT_WRITEBACK_GLOBAL_L2))) {
833 /* Invalidate L1 & L2. (L1 is always invalidated)
834 * WB must be set on VI+ when TC_ACTION is set.
835 */
836 si_emit_surface_sync(rctx, cp_coher_cntl |
837 S_0085F0_TC_ACTION_ENA(1) |
838 S_0301F0_TC_WB_ACTION_ENA(rctx->chip_class >= VI));
839 cp_coher_cntl = 0;
840 } else {
841 /* L1 invalidation and L2 writeback must be done separately,
842 * because both operations can't be done together.
843 */
844 if (rctx->flags & SI_CONTEXT_WRITEBACK_GLOBAL_L2) {
845 /* WB = write-back
846 * NC = apply to non-coherent MTYPEs
847 * (i.e. MTYPE <= 1, which is what we use everywhere)
848 *
849 * WB doesn't work without NC.
850 */
851 si_emit_surface_sync(rctx, cp_coher_cntl |
852 S_0301F0_TC_WB_ACTION_ENA(1) |
853 S_0301F0_TC_NC_ACTION_ENA(1));
854 cp_coher_cntl = 0;
855 }
856 if (rctx->flags & SI_CONTEXT_INV_VMEM_L1) {
857 /* Invalidate per-CU VMEM L1. */
858 si_emit_surface_sync(rctx, cp_coher_cntl |
859 S_0085F0_TCL1_ACTION_ENA(1));
860 cp_coher_cntl = 0;
861 }
862 }
863
864 /* If TC flushes haven't cleared this... */
865 if (cp_coher_cntl)
866 si_emit_surface_sync(rctx, cp_coher_cntl);
867
868 if (rctx->flags & R600_CONTEXT_START_PIPELINE_STATS) {
869 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
870 radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_START) |
871 EVENT_INDEX(0));
872 } else if (rctx->flags & R600_CONTEXT_STOP_PIPELINE_STATS) {
873 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
874 radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_STOP) |
875 EVENT_INDEX(0));
876 }
877
878 rctx->flags = 0;
879 }
880
881 static void si_get_draw_start_count(struct si_context *sctx,
882 const struct pipe_draw_info *info,
883 unsigned *start, unsigned *count)
884 {
885 if (info->indirect) {
886 struct r600_resource *indirect =
887 (struct r600_resource*)info->indirect;
888 int *data = r600_buffer_map_sync_with_rings(&sctx->b,
889 indirect, PIPE_TRANSFER_READ);
890 data += info->indirect_offset/sizeof(int);
891 *start = data[2];
892 *count = data[0];
893 } else {
894 *start = info->start;
895 *count = info->count;
896 }
897 }
898
899 void si_ce_pre_draw_synchronization(struct si_context *sctx)
900 {
901 if (sctx->ce_need_synchronization) {
902 radeon_emit(sctx->ce_ib, PKT3(PKT3_INCREMENT_CE_COUNTER, 0, 0));
903 radeon_emit(sctx->ce_ib, 1);
904
905 radeon_emit(sctx->b.gfx.cs, PKT3(PKT3_WAIT_ON_CE_COUNTER, 0, 0));
906 radeon_emit(sctx->b.gfx.cs, 1);
907 }
908 }
909
910 void si_ce_post_draw_synchronization(struct si_context *sctx)
911 {
912 if (sctx->ce_need_synchronization) {
913 radeon_emit(sctx->b.gfx.cs, PKT3(PKT3_INCREMENT_DE_COUNTER, 0, 0));
914 radeon_emit(sctx->b.gfx.cs, 0);
915
916 sctx->ce_need_synchronization = false;
917 }
918 }
919
920 void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info)
921 {
922 struct si_context *sctx = (struct si_context *)ctx;
923 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
924 struct pipe_index_buffer ib = {};
925 unsigned mask, dirty_fb_counter, dirty_tex_counter, rast_prim;
926
927 if (likely(!info->indirect)) {
928 /* SI-CI treat instance_count==0 as instance_count==1. There is
929 * no workaround for indirect draws, but we can at least skip
930 * direct draws.
931 */
932 if (unlikely(!info->instance_count))
933 return;
934
935 /* Handle count == 0. */
936 if (unlikely(!info->count &&
937 (info->indexed || !info->count_from_stream_output)))
938 return;
939 }
940
941 if (unlikely(!sctx->vs_shader.cso)) {
942 assert(0);
943 return;
944 }
945 if (unlikely(!sctx->ps_shader.cso && (!rs || !rs->rasterizer_discard))) {
946 assert(0);
947 return;
948 }
949 if (unlikely(!!sctx->tes_shader.cso != (info->mode == PIPE_PRIM_PATCHES))) {
950 assert(0);
951 return;
952 }
953
954 /* Re-emit the framebuffer state if needed. */
955 dirty_fb_counter = p_atomic_read(&sctx->b.screen->dirty_fb_counter);
956 if (unlikely(dirty_fb_counter != sctx->b.last_dirty_fb_counter)) {
957 sctx->b.last_dirty_fb_counter = dirty_fb_counter;
958 sctx->framebuffer.dirty_cbufs |=
959 ((1 << sctx->framebuffer.state.nr_cbufs) - 1);
960 sctx->framebuffer.dirty_zsbuf = true;
961 si_mark_atom_dirty(sctx, &sctx->framebuffer.atom);
962 }
963
964 /* Invalidate & recompute texture descriptors if needed. */
965 dirty_tex_counter = p_atomic_read(&sctx->b.screen->dirty_tex_descriptor_counter);
966 if (unlikely(dirty_tex_counter != sctx->b.last_dirty_tex_descriptor_counter)) {
967 sctx->b.last_dirty_tex_descriptor_counter = dirty_tex_counter;
968 si_update_all_texture_descriptors(sctx);
969 }
970
971 si_decompress_graphics_textures(sctx);
972
973 /* Set the rasterization primitive type.
974 *
975 * This must be done after si_decompress_textures, which can call
976 * draw_vbo recursively, and before si_update_shaders, which uses
977 * current_rast_prim for this draw_vbo call. */
978 if (sctx->gs_shader.cso)
979 rast_prim = sctx->gs_shader.cso->gs_output_prim;
980 else if (sctx->tes_shader.cso)
981 rast_prim = sctx->tes_shader.cso->info.properties[TGSI_PROPERTY_TES_PRIM_MODE];
982 else
983 rast_prim = info->mode;
984
985 if (rast_prim != sctx->current_rast_prim) {
986 sctx->current_rast_prim = rast_prim;
987 sctx->do_update_shaders = true;
988 }
989
990 if (sctx->gs_shader.cso) {
991 /* Determine whether the GS triangle strip adjacency fix should
992 * be applied. Rotate every other triangle if
993 * - triangle strips with adjacency are fed to the GS and
994 * - primitive restart is disabled (the rotation doesn't help
995 * when the restart occurs after an odd number of triangles).
996 */
997 bool gs_tri_strip_adj_fix =
998 !sctx->tes_shader.cso &&
999 info->mode == PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY &&
1000 !info->primitive_restart;
1001
1002 if (gs_tri_strip_adj_fix != sctx->gs_tri_strip_adj_fix) {
1003 sctx->gs_tri_strip_adj_fix = gs_tri_strip_adj_fix;
1004 sctx->do_update_shaders = true;
1005 }
1006 }
1007
1008 if (sctx->do_update_shaders && !si_update_shaders(sctx))
1009 return;
1010
1011 if (!si_upload_graphics_shader_descriptors(sctx))
1012 return;
1013
1014 if (info->indexed) {
1015 /* Initialize the index buffer struct. */
1016 pipe_resource_reference(&ib.buffer, sctx->index_buffer.buffer);
1017 ib.user_buffer = sctx->index_buffer.user_buffer;
1018 ib.index_size = sctx->index_buffer.index_size;
1019 ib.offset = sctx->index_buffer.offset;
1020
1021 /* Translate or upload, if needed. */
1022 /* 8-bit indices are supported on VI. */
1023 if (sctx->b.chip_class <= CIK && ib.index_size == 1) {
1024 struct pipe_resource *out_buffer = NULL;
1025 unsigned out_offset, start, count, start_offset;
1026 void *ptr;
1027
1028 si_get_draw_start_count(sctx, info, &start, &count);
1029 start_offset = start * ib.index_size;
1030
1031 u_upload_alloc(sctx->b.uploader, start_offset, count * 2, 256,
1032 &out_offset, &out_buffer, &ptr);
1033 if (!out_buffer) {
1034 pipe_resource_reference(&ib.buffer, NULL);
1035 return;
1036 }
1037
1038 util_shorten_ubyte_elts_to_userptr(&sctx->b.b, &ib, 0,
1039 ib.offset + start_offset,
1040 count, ptr);
1041
1042 pipe_resource_reference(&ib.buffer, NULL);
1043 ib.user_buffer = NULL;
1044 ib.buffer = out_buffer;
1045 /* info->start will be added by the drawing code */
1046 ib.offset = out_offset - start_offset;
1047 ib.index_size = 2;
1048 } else if (ib.user_buffer && !ib.buffer) {
1049 unsigned start, count, start_offset;
1050
1051 si_get_draw_start_count(sctx, info, &start, &count);
1052 start_offset = start * ib.index_size;
1053
1054 u_upload_data(sctx->b.uploader, start_offset, count * ib.index_size,
1055 256, (char*)ib.user_buffer + start_offset,
1056 &ib.offset, &ib.buffer);
1057 if (!ib.buffer)
1058 return;
1059 /* info->start will be added by the drawing code */
1060 ib.offset -= start_offset;
1061 }
1062 }
1063
1064 /* VI reads index buffers through TC L2. */
1065 if (info->indexed && sctx->b.chip_class <= CIK &&
1066 r600_resource(ib.buffer)->TC_L2_dirty) {
1067 sctx->b.flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
1068 r600_resource(ib.buffer)->TC_L2_dirty = false;
1069 }
1070
1071 if (info->indirect && r600_resource(info->indirect)->TC_L2_dirty) {
1072 sctx->b.flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
1073 r600_resource(info->indirect)->TC_L2_dirty = false;
1074 }
1075
1076 if (info->indirect_params &&
1077 r600_resource(info->indirect_params)->TC_L2_dirty) {
1078 sctx->b.flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
1079 r600_resource(info->indirect_params)->TC_L2_dirty = false;
1080 }
1081
1082 /* Add buffer sizes for memory checking in need_cs_space. */
1083 if (sctx->emit_scratch_reloc && sctx->scratch_buffer)
1084 r600_context_add_resource_size(ctx, &sctx->scratch_buffer->b.b);
1085 if (info->indirect)
1086 r600_context_add_resource_size(ctx, info->indirect);
1087
1088 si_need_cs_space(sctx);
1089
1090 /* Since we've called r600_context_add_resource_size for vertex buffers,
1091 * this must be called after si_need_cs_space, because we must let
1092 * need_cs_space flush before we add buffers to the buffer list.
1093 */
1094 if (!si_upload_vertex_buffer_descriptors(sctx))
1095 return;
1096
1097 /* Flushed caches prior to emitting states. */
1098 if (sctx->b.flags)
1099 si_emit_cache_flush(sctx);
1100
1101 /* Emit states. */
1102 mask = sctx->dirty_atoms;
1103 while (mask) {
1104 struct r600_atom *atom = sctx->atoms.array[u_bit_scan(&mask)];
1105
1106 atom->emit(&sctx->b, atom);
1107 }
1108 sctx->dirty_atoms = 0;
1109
1110 si_pm4_emit_dirty(sctx);
1111 si_emit_scratch_reloc(sctx);
1112 si_emit_rasterizer_prim_state(sctx);
1113 si_emit_draw_registers(sctx, info);
1114
1115 si_ce_pre_draw_synchronization(sctx);
1116
1117 si_emit_draw_packets(sctx, info, &ib);
1118
1119 si_ce_post_draw_synchronization(sctx);
1120
1121 if (sctx->trace_buf)
1122 si_trace_emit(sctx);
1123
1124 /* Workaround for a VGT hang when streamout is enabled.
1125 * It must be done after drawing. */
1126 if ((sctx->b.family == CHIP_HAWAII ||
1127 sctx->b.family == CHIP_TONGA ||
1128 sctx->b.family == CHIP_FIJI) &&
1129 r600_get_strmout_en(&sctx->b)) {
1130 sctx->b.flags |= SI_CONTEXT_VGT_STREAMOUT_SYNC;
1131 }
1132
1133 /* Set the depth buffer as dirty. */
1134 if (sctx->framebuffer.state.zsbuf) {
1135 struct pipe_surface *surf = sctx->framebuffer.state.zsbuf;
1136 struct r600_texture *rtex = (struct r600_texture *)surf->texture;
1137
1138 if (!rtex->tc_compatible_htile)
1139 rtex->dirty_level_mask |= 1 << surf->u.tex.level;
1140
1141 if (rtex->surface.flags & RADEON_SURF_SBUFFER)
1142 rtex->stencil_dirty_level_mask |= 1 << surf->u.tex.level;
1143 }
1144 if (sctx->framebuffer.compressed_cb_mask) {
1145 struct pipe_surface *surf;
1146 struct r600_texture *rtex;
1147 unsigned mask = sctx->framebuffer.compressed_cb_mask;
1148
1149 do {
1150 unsigned i = u_bit_scan(&mask);
1151 surf = sctx->framebuffer.state.cbufs[i];
1152 rtex = (struct r600_texture*)surf->texture;
1153
1154 if (rtex->fmask.size)
1155 rtex->dirty_level_mask |= 1 << surf->u.tex.level;
1156 if (rtex->dcc_gather_statistics)
1157 rtex->separate_dcc_dirty = true;
1158 } while (mask);
1159 }
1160
1161 pipe_resource_reference(&ib.buffer, NULL);
1162 sctx->b.num_draw_calls++;
1163 if (G_0286E8_WAVESIZE(sctx->spi_tmpring_size))
1164 sctx->b.num_spill_draw_calls++;
1165 }
1166
1167 void si_trace_emit(struct si_context *sctx)
1168 {
1169 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
1170
1171 sctx->trace_id++;
1172 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, sctx->trace_buf,
1173 RADEON_USAGE_READWRITE, RADEON_PRIO_TRACE);
1174 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
1175 radeon_emit(cs, S_370_DST_SEL(V_370_MEMORY_SYNC) |
1176 S_370_WR_CONFIRM(1) |
1177 S_370_ENGINE_SEL(V_370_ME));
1178 radeon_emit(cs, sctx->trace_buf->gpu_address);
1179 radeon_emit(cs, sctx->trace_buf->gpu_address >> 32);
1180 radeon_emit(cs, sctx->trace_id);
1181 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1182 radeon_emit(cs, SI_ENCODE_TRACE_POINT(sctx->trace_id));
1183 }