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radeonsi: try to fix IA_MULTI_VGT_PARAM programming
[mesa.git] / src / gallium / drivers / radeonsi / si_state_draw.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Christian König <christian.koenig@amd.com>
25 */
26
27 #include "util/u_memory.h"
28 #include "util/u_framebuffer.h"
29 #include "util/u_blitter.h"
30 #include "tgsi/tgsi_parse.h"
31 #include "radeonsi_pipe.h"
32 #include "radeonsi_shader.h"
33 #include "si_state.h"
34 #include "../radeon/r600_cs.h"
35 #include "sid.h"
36
37 /*
38 * Shaders
39 */
40
41 static void si_pipe_shader_vs(struct pipe_context *ctx, struct si_pipe_shader *shader)
42 {
43 struct r600_context *rctx = (struct r600_context *)ctx;
44 struct si_pm4_state *pm4;
45 unsigned num_sgprs, num_user_sgprs;
46 unsigned nparams, i, vgpr_comp_cnt;
47 uint64_t va;
48
49 si_pm4_delete_state(rctx, vs, shader->pm4);
50 pm4 = shader->pm4 = si_pm4_alloc_state(rctx);
51
52 if (pm4 == NULL)
53 return;
54
55 /* Certain attributes (position, psize, etc.) don't count as params.
56 * VS is required to export at least one param and r600_shader_from_tgsi()
57 * takes care of adding a dummy export.
58 */
59 for (nparams = 0, i = 0 ; i < shader->shader.noutput; i++) {
60 switch (shader->shader.output[i].name) {
61 case TGSI_SEMANTIC_CLIPVERTEX:
62 case TGSI_SEMANTIC_POSITION:
63 case TGSI_SEMANTIC_PSIZE:
64 break;
65 default:
66 nparams++;
67 }
68 }
69 if (nparams < 1)
70 nparams = 1;
71
72 si_pm4_set_reg(pm4, R_0286C4_SPI_VS_OUT_CONFIG,
73 S_0286C4_VS_EXPORT_COUNT(nparams - 1));
74
75 si_pm4_set_reg(pm4, R_02870C_SPI_SHADER_POS_FORMAT,
76 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
77 S_02870C_POS1_EXPORT_FORMAT(shader->shader.nr_pos_exports > 1 ?
78 V_02870C_SPI_SHADER_4COMP :
79 V_02870C_SPI_SHADER_NONE) |
80 S_02870C_POS2_EXPORT_FORMAT(shader->shader.nr_pos_exports > 2 ?
81 V_02870C_SPI_SHADER_4COMP :
82 V_02870C_SPI_SHADER_NONE) |
83 S_02870C_POS3_EXPORT_FORMAT(shader->shader.nr_pos_exports > 3 ?
84 V_02870C_SPI_SHADER_4COMP :
85 V_02870C_SPI_SHADER_NONE));
86
87 va = r600_resource_va(ctx->screen, (void *)shader->bo);
88 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ);
89 si_pm4_set_reg(pm4, R_00B120_SPI_SHADER_PGM_LO_VS, va >> 8);
90 si_pm4_set_reg(pm4, R_00B124_SPI_SHADER_PGM_HI_VS, va >> 40);
91
92 num_user_sgprs = SI_VS_NUM_USER_SGPR;
93 num_sgprs = shader->num_sgprs;
94 if (num_user_sgprs > num_sgprs) {
95 /* Last 2 reserved SGPRs are used for VCC */
96 num_sgprs = num_user_sgprs + 2;
97 }
98 assert(num_sgprs <= 104);
99
100 vgpr_comp_cnt = shader->shader.uses_instanceid ? 3 : 0;
101
102 si_pm4_set_reg(pm4, R_00B128_SPI_SHADER_PGM_RSRC1_VS,
103 S_00B128_VGPRS((shader->num_vgprs - 1) / 4) |
104 S_00B128_SGPRS((num_sgprs - 1) / 8) |
105 S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt));
106 si_pm4_set_reg(pm4, R_00B12C_SPI_SHADER_PGM_RSRC2_VS,
107 S_00B12C_USER_SGPR(num_user_sgprs) |
108 S_00B12C_SO_BASE0_EN(!!shader->selector->so.stride[0]) |
109 S_00B12C_SO_BASE1_EN(!!shader->selector->so.stride[1]) |
110 S_00B12C_SO_BASE2_EN(!!shader->selector->so.stride[2]) |
111 S_00B12C_SO_BASE3_EN(!!shader->selector->so.stride[3]) |
112 S_00B12C_SO_EN(!!shader->selector->so.num_outputs));
113
114 if (rctx->b.chip_class >= CIK) {
115 si_pm4_set_reg(pm4, R_00B118_SPI_SHADER_PGM_RSRC3_VS,
116 S_00B118_CU_EN(0xffff));
117 si_pm4_set_reg(pm4, R_00B11C_SPI_SHADER_LATE_ALLOC_VS,
118 S_00B11C_LIMIT(0));
119 }
120
121 si_pm4_bind_state(rctx, vs, shader->pm4);
122 rctx->b.flags |= R600_CONTEXT_INV_SHADER_CACHE;
123 }
124
125 static void si_pipe_shader_ps(struct pipe_context *ctx, struct si_pipe_shader *shader)
126 {
127 struct r600_context *rctx = (struct r600_context *)ctx;
128 struct si_pm4_state *pm4;
129 unsigned i, exports_ps, num_cout, spi_ps_in_control, db_shader_control;
130 unsigned num_sgprs, num_user_sgprs;
131 unsigned spi_baryc_cntl = 0, spi_ps_input_ena, spi_shader_z_format;
132 uint64_t va;
133
134 si_pm4_delete_state(rctx, ps, shader->pm4);
135 pm4 = shader->pm4 = si_pm4_alloc_state(rctx);
136
137 if (pm4 == NULL)
138 return;
139
140 db_shader_control = S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z) |
141 S_02880C_ALPHA_TO_MASK_DISABLE(rctx->fb_cb0_is_integer);
142
143 for (i = 0; i < shader->shader.ninput; i++) {
144 switch (shader->shader.input[i].name) {
145 case TGSI_SEMANTIC_POSITION:
146 if (shader->shader.input[i].centroid) {
147 /* SPI_BARYC_CNTL.POS_FLOAT_LOCATION
148 * Possible vaules:
149 * 0 -> Position = pixel center (default)
150 * 1 -> Position = pixel centroid
151 * 2 -> Position = iterated sample number XXX:
152 * What does this mean?
153 */
154 spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(1);
155 }
156 /* Fall through */
157 case TGSI_SEMANTIC_FACE:
158 continue;
159 }
160 }
161
162 for (i = 0; i < shader->shader.noutput; i++) {
163 if (shader->shader.output[i].name == TGSI_SEMANTIC_POSITION)
164 db_shader_control |= S_02880C_Z_EXPORT_ENABLE(1);
165 if (shader->shader.output[i].name == TGSI_SEMANTIC_STENCIL)
166 db_shader_control |= S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(1);
167 }
168 if (shader->shader.uses_kill || shader->key.ps.alpha_func != PIPE_FUNC_ALWAYS)
169 db_shader_control |= S_02880C_KILL_ENABLE(1);
170
171 exports_ps = 0;
172 num_cout = 0;
173 for (i = 0; i < shader->shader.noutput; i++) {
174 if (shader->shader.output[i].name == TGSI_SEMANTIC_POSITION ||
175 shader->shader.output[i].name == TGSI_SEMANTIC_STENCIL)
176 exports_ps |= 1;
177 else if (shader->shader.output[i].name == TGSI_SEMANTIC_COLOR) {
178 if (shader->shader.fs_write_all)
179 num_cout = shader->shader.nr_cbufs;
180 else
181 num_cout++;
182 }
183 }
184 if (!exports_ps) {
185 /* always at least export 1 component per pixel */
186 exports_ps = 2;
187 }
188
189 spi_ps_in_control = S_0286D8_NUM_INTERP(shader->shader.ninterp) |
190 S_0286D8_BC_OPTIMIZE_DISABLE(1);
191
192 si_pm4_set_reg(pm4, R_0286E0_SPI_BARYC_CNTL, spi_baryc_cntl);
193 spi_ps_input_ena = shader->spi_ps_input_ena;
194 /* we need to enable at least one of them, otherwise we hang the GPU */
195 assert(G_0286CC_PERSP_SAMPLE_ENA(spi_ps_input_ena) ||
196 G_0286CC_PERSP_CENTER_ENA(spi_ps_input_ena) ||
197 G_0286CC_PERSP_CENTROID_ENA(spi_ps_input_ena) ||
198 G_0286CC_PERSP_PULL_MODEL_ENA(spi_ps_input_ena) ||
199 G_0286CC_LINEAR_SAMPLE_ENA(spi_ps_input_ena) ||
200 G_0286CC_LINEAR_CENTER_ENA(spi_ps_input_ena) ||
201 G_0286CC_LINEAR_CENTROID_ENA(spi_ps_input_ena) ||
202 G_0286CC_LINE_STIPPLE_TEX_ENA(spi_ps_input_ena));
203
204 si_pm4_set_reg(pm4, R_0286CC_SPI_PS_INPUT_ENA, spi_ps_input_ena);
205 si_pm4_set_reg(pm4, R_0286D0_SPI_PS_INPUT_ADDR, spi_ps_input_ena);
206 si_pm4_set_reg(pm4, R_0286D8_SPI_PS_IN_CONTROL, spi_ps_in_control);
207
208 if (G_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(db_shader_control))
209 spi_shader_z_format = V_028710_SPI_SHADER_32_GR;
210 else if (G_02880C_Z_EXPORT_ENABLE(db_shader_control))
211 spi_shader_z_format = V_028710_SPI_SHADER_32_R;
212 else
213 spi_shader_z_format = 0;
214 si_pm4_set_reg(pm4, R_028710_SPI_SHADER_Z_FORMAT, spi_shader_z_format);
215 si_pm4_set_reg(pm4, R_028714_SPI_SHADER_COL_FORMAT,
216 shader->spi_shader_col_format);
217 si_pm4_set_reg(pm4, R_02823C_CB_SHADER_MASK, shader->cb_shader_mask);
218
219 va = r600_resource_va(ctx->screen, (void *)shader->bo);
220 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ);
221 si_pm4_set_reg(pm4, R_00B020_SPI_SHADER_PGM_LO_PS, va >> 8);
222 si_pm4_set_reg(pm4, R_00B024_SPI_SHADER_PGM_HI_PS, va >> 40);
223
224 num_user_sgprs = SI_PS_NUM_USER_SGPR;
225 num_sgprs = shader->num_sgprs;
226 /* One SGPR after user SGPRs is pre-loaded with {prim_mask, lds_offset} */
227 if ((num_user_sgprs + 1) > num_sgprs) {
228 /* Last 2 reserved SGPRs are used for VCC */
229 num_sgprs = num_user_sgprs + 1 + 2;
230 }
231 assert(num_sgprs <= 104);
232
233 si_pm4_set_reg(pm4, R_00B028_SPI_SHADER_PGM_RSRC1_PS,
234 S_00B028_VGPRS((shader->num_vgprs - 1) / 4) |
235 S_00B028_SGPRS((num_sgprs - 1) / 8));
236 si_pm4_set_reg(pm4, R_00B02C_SPI_SHADER_PGM_RSRC2_PS,
237 S_00B02C_EXTRA_LDS_SIZE(shader->lds_size) |
238 S_00B02C_USER_SGPR(num_user_sgprs));
239 if (rctx->b.chip_class >= CIK) {
240 si_pm4_set_reg(pm4, R_00B01C_SPI_SHADER_PGM_RSRC3_PS,
241 S_00B01C_CU_EN(0xffff));
242 }
243
244 si_pm4_set_reg(pm4, R_02880C_DB_SHADER_CONTROL, db_shader_control);
245
246 shader->cb0_is_integer = rctx->fb_cb0_is_integer;
247 shader->sprite_coord_enable = rctx->sprite_coord_enable;
248 si_pm4_bind_state(rctx, ps, shader->pm4);
249 rctx->b.flags |= R600_CONTEXT_INV_SHADER_CACHE;
250 }
251
252 /*
253 * Drawing
254 */
255
256 static unsigned si_conv_pipe_prim(unsigned pprim)
257 {
258 static const unsigned prim_conv[] = {
259 [PIPE_PRIM_POINTS] = V_008958_DI_PT_POINTLIST,
260 [PIPE_PRIM_LINES] = V_008958_DI_PT_LINELIST,
261 [PIPE_PRIM_LINE_LOOP] = V_008958_DI_PT_LINELOOP,
262 [PIPE_PRIM_LINE_STRIP] = V_008958_DI_PT_LINESTRIP,
263 [PIPE_PRIM_TRIANGLES] = V_008958_DI_PT_TRILIST,
264 [PIPE_PRIM_TRIANGLE_STRIP] = V_008958_DI_PT_TRISTRIP,
265 [PIPE_PRIM_TRIANGLE_FAN] = V_008958_DI_PT_TRIFAN,
266 [PIPE_PRIM_QUADS] = V_008958_DI_PT_QUADLIST,
267 [PIPE_PRIM_QUAD_STRIP] = V_008958_DI_PT_QUADSTRIP,
268 [PIPE_PRIM_POLYGON] = V_008958_DI_PT_POLYGON,
269 [PIPE_PRIM_LINES_ADJACENCY] = ~0,
270 [PIPE_PRIM_LINE_STRIP_ADJACENCY] = ~0,
271 [PIPE_PRIM_TRIANGLES_ADJACENCY] = ~0,
272 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY] = ~0
273 };
274 unsigned result = prim_conv[pprim];
275 if (result == ~0) {
276 R600_ERR("unsupported primitive type %d\n", pprim);
277 }
278 return result;
279 }
280
281 static unsigned r600_conv_prim_to_gs_out(unsigned mode)
282 {
283 static const int prim_conv[] = {
284 [PIPE_PRIM_POINTS] = V_028A6C_OUTPRIM_TYPE_POINTLIST,
285 [PIPE_PRIM_LINES] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
286 [PIPE_PRIM_LINE_LOOP] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
287 [PIPE_PRIM_LINE_STRIP] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
288 [PIPE_PRIM_TRIANGLES] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
289 [PIPE_PRIM_TRIANGLE_STRIP] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
290 [PIPE_PRIM_TRIANGLE_FAN] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
291 [PIPE_PRIM_QUADS] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
292 [PIPE_PRIM_QUAD_STRIP] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
293 [PIPE_PRIM_POLYGON] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
294 [PIPE_PRIM_LINES_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
295 [PIPE_PRIM_LINE_STRIP_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
296 [PIPE_PRIM_TRIANGLES_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
297 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
298 };
299 assert(mode < Elements(prim_conv));
300
301 return prim_conv[mode];
302 }
303
304 static bool si_update_draw_info_state(struct r600_context *rctx,
305 const struct pipe_draw_info *info,
306 const struct pipe_index_buffer *ib)
307 {
308 struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx);
309 struct si_shader *vs = &rctx->vs_shader->current->shader;
310 unsigned prim = si_conv_pipe_prim(info->mode);
311 unsigned gs_out_prim = r600_conv_prim_to_gs_out(info->mode);
312 unsigned ls_mask = 0;
313
314 if (pm4 == NULL)
315 return false;
316
317 if (prim == ~0) {
318 FREE(pm4);
319 return false;
320 }
321
322 if (rctx->b.chip_class >= CIK) {
323 struct si_state_rasterizer *rs = rctx->queued.named.rasterizer;
324 bool wd_switch_on_eop = prim == V_008958_DI_PT_POLYGON ||
325 prim == V_008958_DI_PT_LINELOOP ||
326 prim == V_008958_DI_PT_TRIFAN ||
327 prim == V_008958_DI_PT_TRISTRIP_ADJ ||
328 info->primitive_restart ||
329 (rs ? rs->line_stipple_enable : false);
330 /* If the WD switch is false, the IA switch must be false too. */
331 bool ia_switch_on_eop = wd_switch_on_eop;
332
333 si_pm4_set_reg(pm4, R_028AA8_IA_MULTI_VGT_PARAM,
334 S_028AA8_SWITCH_ON_EOP(ia_switch_on_eop) |
335 S_028AA8_PARTIAL_VS_WAVE_ON(1) |
336 S_028AA8_PRIMGROUP_SIZE(63) |
337 S_028AA8_WD_SWITCH_ON_EOP(wd_switch_on_eop));
338 si_pm4_set_reg(pm4, R_028B74_VGT_DISPATCH_DRAW_INDEX,
339 ib->index_size == 4 ? 0xFC000000 : 0xFC00);
340
341 si_pm4_set_reg(pm4, R_030908_VGT_PRIMITIVE_TYPE, prim);
342 } else {
343 si_pm4_set_reg(pm4, R_008958_VGT_PRIMITIVE_TYPE, prim);
344 }
345
346 si_pm4_set_reg(pm4, R_028A6C_VGT_GS_OUT_PRIM_TYPE, gs_out_prim);
347 si_pm4_set_reg(pm4, R_028400_VGT_MAX_VTX_INDX, ~0);
348 si_pm4_set_reg(pm4, R_028404_VGT_MIN_VTX_INDX, 0);
349 si_pm4_set_reg(pm4, R_028408_VGT_INDX_OFFSET,
350 info->indexed ? info->index_bias : info->start);
351 si_pm4_set_reg(pm4, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, info->restart_index);
352 si_pm4_set_reg(pm4, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, info->primitive_restart);
353 si_pm4_set_reg(pm4, R_00B130_SPI_SHADER_USER_DATA_VS_0 + SI_SGPR_START_INSTANCE * 4,
354 info->start_instance);
355
356 if (prim == V_008958_DI_PT_LINELIST)
357 ls_mask = 1;
358 else if (prim == V_008958_DI_PT_LINESTRIP)
359 ls_mask = 2;
360 si_pm4_set_reg(pm4, R_028A0C_PA_SC_LINE_STIPPLE,
361 S_028A0C_AUTO_RESET_CNTL(ls_mask) |
362 rctx->pa_sc_line_stipple);
363
364 if (info->mode == PIPE_PRIM_QUADS || info->mode == PIPE_PRIM_QUAD_STRIP || info->mode == PIPE_PRIM_POLYGON) {
365 si_pm4_set_reg(pm4, R_028814_PA_SU_SC_MODE_CNTL,
366 S_028814_PROVOKING_VTX_LAST(1) | rctx->pa_su_sc_mode_cntl);
367 } else {
368 si_pm4_set_reg(pm4, R_028814_PA_SU_SC_MODE_CNTL, rctx->pa_su_sc_mode_cntl);
369 }
370 si_pm4_set_reg(pm4, R_02881C_PA_CL_VS_OUT_CNTL,
371 S_02881C_USE_VTX_POINT_SIZE(vs->vs_out_point_size) |
372 S_02881C_VS_OUT_CCDIST0_VEC_ENA((vs->clip_dist_write & 0x0F) != 0) |
373 S_02881C_VS_OUT_CCDIST1_VEC_ENA((vs->clip_dist_write & 0xF0) != 0) |
374 S_02881C_VS_OUT_MISC_VEC_ENA(vs->vs_out_misc_write) |
375 (rctx->queued.named.rasterizer->clip_plane_enable &
376 vs->clip_dist_write));
377 si_pm4_set_reg(pm4, R_028810_PA_CL_CLIP_CNTL,
378 rctx->queued.named.rasterizer->pa_cl_clip_cntl |
379 (vs->clip_dist_write ? 0 :
380 rctx->queued.named.rasterizer->clip_plane_enable & 0x3F));
381
382 si_pm4_set_state(rctx, draw_info, pm4);
383 return true;
384 }
385
386 static void si_update_spi_map(struct r600_context *rctx)
387 {
388 struct si_shader *ps = &rctx->ps_shader->current->shader;
389 struct si_shader *vs = &rctx->vs_shader->current->shader;
390 struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx);
391 unsigned i, j, tmp;
392
393 for (i = 0; i < ps->ninput; i++) {
394 unsigned name = ps->input[i].name;
395 unsigned param_offset = ps->input[i].param_offset;
396
397 if (name == TGSI_SEMANTIC_POSITION)
398 /* Read from preloaded VGPRs, not parameters */
399 continue;
400
401 bcolor:
402 tmp = 0;
403
404 if (ps->input[i].interpolate == TGSI_INTERPOLATE_CONSTANT ||
405 (ps->input[i].interpolate == TGSI_INTERPOLATE_COLOR &&
406 rctx->ps_shader->current->key.ps.flatshade)) {
407 tmp |= S_028644_FLAT_SHADE(1);
408 }
409
410 if (name == TGSI_SEMANTIC_GENERIC &&
411 rctx->sprite_coord_enable & (1 << ps->input[i].sid)) {
412 tmp |= S_028644_PT_SPRITE_TEX(1);
413 }
414
415 for (j = 0; j < vs->noutput; j++) {
416 if (name == vs->output[j].name &&
417 ps->input[i].sid == vs->output[j].sid) {
418 tmp |= S_028644_OFFSET(vs->output[j].param_offset);
419 break;
420 }
421 }
422
423 if (j == vs->noutput) {
424 /* No corresponding output found, load defaults into input */
425 tmp |= S_028644_OFFSET(0x20);
426 }
427
428 si_pm4_set_reg(pm4,
429 R_028644_SPI_PS_INPUT_CNTL_0 + param_offset * 4,
430 tmp);
431
432 if (name == TGSI_SEMANTIC_COLOR &&
433 rctx->ps_shader->current->key.ps.color_two_side) {
434 name = TGSI_SEMANTIC_BCOLOR;
435 param_offset++;
436 goto bcolor;
437 }
438 }
439
440 si_pm4_set_state(rctx, spi, pm4);
441 }
442
443 static void si_update_derived_state(struct r600_context *rctx)
444 {
445 struct pipe_context * ctx = (struct pipe_context*)rctx;
446 unsigned vs_dirty = 0, ps_dirty = 0;
447
448 if (!rctx->blitter->running) {
449 /* Flush depth textures which need to be flushed. */
450 for (int i = 0; i < SI_NUM_SHADERS; i++) {
451 if (rctx->samplers[i].depth_texture_mask) {
452 si_flush_depth_textures(rctx, &rctx->samplers[i]);
453 }
454 if (rctx->samplers[i].compressed_colortex_mask) {
455 r600_decompress_color_textures(rctx, &rctx->samplers[i]);
456 }
457 }
458 }
459
460 si_shader_select(ctx, rctx->vs_shader, &vs_dirty);
461
462 if (!rctx->vs_shader->current->pm4) {
463 si_pipe_shader_vs(ctx, rctx->vs_shader->current);
464 vs_dirty = 0;
465 }
466
467 if (vs_dirty) {
468 si_pm4_bind_state(rctx, vs, rctx->vs_shader->current->pm4);
469 }
470
471
472 si_shader_select(ctx, rctx->ps_shader, &ps_dirty);
473
474 if (!rctx->ps_shader->current->pm4) {
475 si_pipe_shader_ps(ctx, rctx->ps_shader->current);
476 ps_dirty = 0;
477 }
478 if (!rctx->ps_shader->current->bo) {
479 if (!rctx->dummy_pixel_shader->pm4)
480 si_pipe_shader_ps(ctx, rctx->dummy_pixel_shader);
481 else
482 si_pm4_bind_state(rctx, vs, rctx->dummy_pixel_shader->pm4);
483
484 ps_dirty = 0;
485 }
486 if (rctx->ps_shader->current->cb0_is_integer != rctx->fb_cb0_is_integer) {
487 si_pipe_shader_ps(ctx, rctx->ps_shader->current);
488 ps_dirty = 1;
489 }
490
491 if (ps_dirty) {
492 si_pm4_bind_state(rctx, ps, rctx->ps_shader->current->pm4);
493 }
494
495 if (si_pm4_state_changed(rctx, ps) || si_pm4_state_changed(rctx, vs)) {
496 /* XXX: Emitting the PS state even when only the VS changed
497 * fixes random failures with piglit glsl-max-varyings.
498 * Not sure why...
499 */
500 rctx->emitted.named.ps = NULL;
501 si_update_spi_map(rctx);
502 }
503 }
504
505 static void si_vertex_buffer_update(struct r600_context *rctx)
506 {
507 struct pipe_context *ctx = &rctx->b.b;
508 struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx);
509 bool bound[PIPE_MAX_ATTRIBS] = {};
510 unsigned i, count;
511 uint64_t va;
512
513 rctx->b.flags |= R600_CONTEXT_INV_TEX_CACHE;
514
515 count = rctx->vertex_elements->count;
516 assert(count <= 256 / 4);
517
518 si_pm4_sh_data_begin(pm4);
519 for (i = 0 ; i < count; i++) {
520 struct pipe_vertex_element *ve = &rctx->vertex_elements->elements[i];
521 struct pipe_vertex_buffer *vb;
522 struct r600_resource *rbuffer;
523 unsigned offset;
524
525 if (ve->vertex_buffer_index >= rctx->nr_vertex_buffers)
526 continue;
527
528 vb = &rctx->vertex_buffer[ve->vertex_buffer_index];
529 rbuffer = (struct r600_resource*)vb->buffer;
530 if (rbuffer == NULL)
531 continue;
532
533 offset = 0;
534 offset += vb->buffer_offset;
535 offset += ve->src_offset;
536
537 va = r600_resource_va(ctx->screen, (void*)rbuffer);
538 va += offset;
539
540 /* Fill in T# buffer resource description */
541 si_pm4_sh_data_add(pm4, va & 0xFFFFFFFF);
542 si_pm4_sh_data_add(pm4, (S_008F04_BASE_ADDRESS_HI(va >> 32) |
543 S_008F04_STRIDE(vb->stride)));
544 if (vb->stride)
545 /* Round up by rounding down and adding 1 */
546 si_pm4_sh_data_add(pm4,
547 (vb->buffer->width0 - offset -
548 util_format_get_blocksize(ve->src_format)) /
549 vb->stride + 1);
550 else
551 si_pm4_sh_data_add(pm4, vb->buffer->width0 - offset);
552 si_pm4_sh_data_add(pm4, rctx->vertex_elements->rsrc_word3[i]);
553
554 if (!bound[ve->vertex_buffer_index]) {
555 si_pm4_add_bo(pm4, rbuffer, RADEON_USAGE_READ);
556 bound[ve->vertex_buffer_index] = true;
557 }
558 }
559 si_pm4_sh_data_end(pm4, R_00B130_SPI_SHADER_USER_DATA_VS_0, SI_SGPR_VERTEX_BUFFER);
560 si_pm4_set_state(rctx, vertex_buffers, pm4);
561 }
562
563 static void si_state_draw(struct r600_context *rctx,
564 const struct pipe_draw_info *info,
565 const struct pipe_index_buffer *ib)
566 {
567 struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx);
568
569 if (pm4 == NULL)
570 return;
571
572 /* queries need some special values
573 * (this is non-zero if any query is active) */
574 if (rctx->num_cs_dw_nontimer_queries_suspend) {
575 struct si_state_dsa *dsa = rctx->queued.named.dsa;
576
577 if (rctx->b.chip_class >= CIK) {
578 si_pm4_set_reg(pm4, R_028004_DB_COUNT_CONTROL,
579 S_028004_PERFECT_ZPASS_COUNTS(1) |
580 S_028004_SAMPLE_RATE(rctx->fb_log_samples) |
581 S_028004_ZPASS_ENABLE(1) |
582 S_028004_SLICE_EVEN_ENABLE(1) |
583 S_028004_SLICE_ODD_ENABLE(1));
584 } else {
585 si_pm4_set_reg(pm4, R_028004_DB_COUNT_CONTROL,
586 S_028004_PERFECT_ZPASS_COUNTS(1) |
587 S_028004_SAMPLE_RATE(rctx->fb_log_samples));
588 }
589 si_pm4_set_reg(pm4, R_02800C_DB_RENDER_OVERRIDE,
590 dsa->db_render_override |
591 S_02800C_NOOP_CULL_DISABLE(1));
592 }
593
594 if (info->count_from_stream_output) {
595 struct r600_so_target *t =
596 (struct r600_so_target*)info->count_from_stream_output;
597 uint64_t va = r600_resource_va(&rctx->screen->b.b,
598 &t->buf_filled_size->b.b);
599 va += t->buf_filled_size_offset;
600
601 si_pm4_set_reg(pm4, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE,
602 t->stride_in_dw);
603
604 si_pm4_cmd_begin(pm4, PKT3_COPY_DATA);
605 si_pm4_cmd_add(pm4,
606 COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
607 COPY_DATA_DST_SEL(COPY_DATA_REG) |
608 COPY_DATA_WR_CONFIRM);
609 si_pm4_cmd_add(pm4, va); /* src address lo */
610 si_pm4_cmd_add(pm4, va >> 32UL); /* src address hi */
611 si_pm4_cmd_add(pm4, R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE >> 2);
612 si_pm4_cmd_add(pm4, 0); /* unused */
613 si_pm4_add_bo(pm4, t->buf_filled_size, RADEON_USAGE_READ);
614 si_pm4_cmd_end(pm4, true);
615 }
616
617 /* draw packet */
618 si_pm4_cmd_begin(pm4, PKT3_INDEX_TYPE);
619 if (ib->index_size == 4) {
620 si_pm4_cmd_add(pm4, V_028A7C_VGT_INDEX_32 | (R600_BIG_ENDIAN ?
621 V_028A7C_VGT_DMA_SWAP_32_BIT : 0));
622 } else {
623 si_pm4_cmd_add(pm4, V_028A7C_VGT_INDEX_16 | (R600_BIG_ENDIAN ?
624 V_028A7C_VGT_DMA_SWAP_16_BIT : 0));
625 }
626 si_pm4_cmd_end(pm4, rctx->predicate_drawing);
627
628 si_pm4_cmd_begin(pm4, PKT3_NUM_INSTANCES);
629 si_pm4_cmd_add(pm4, info->instance_count);
630 si_pm4_cmd_end(pm4, rctx->predicate_drawing);
631
632 if (info->indexed) {
633 uint32_t max_size = (ib->buffer->width0 - ib->offset) /
634 rctx->index_buffer.index_size;
635 uint64_t va;
636 va = r600_resource_va(&rctx->screen->b.b, ib->buffer);
637 va += ib->offset;
638
639 si_pm4_add_bo(pm4, (struct r600_resource *)ib->buffer, RADEON_USAGE_READ);
640 si_cmd_draw_index_2(pm4, max_size, va, info->count,
641 V_0287F0_DI_SRC_SEL_DMA,
642 rctx->predicate_drawing);
643 } else {
644 uint32_t initiator = V_0287F0_DI_SRC_SEL_AUTO_INDEX;
645 initiator |= S_0287F0_USE_OPAQUE(!!info->count_from_stream_output);
646 si_cmd_draw_index_auto(pm4, info->count, initiator, rctx->predicate_drawing);
647 }
648 si_pm4_set_state(rctx, draw, pm4);
649 }
650
651 void si_emit_cache_flush(struct r600_common_context *rctx, struct r600_atom *atom)
652 {
653 struct radeon_winsys_cs *cs = rctx->rings.gfx.cs;
654 uint32_t cp_coher_cntl = 0;
655
656 /* XXX SI flushes both ICACHE and KCACHE if either flag is set.
657 * XXX CIK shouldn't have this issue. Test CIK before separating the flags
658 * XXX to ensure there is no regression. Also find out if there is another
659 * XXX way to flush either ICACHE or KCACHE but not both for SI. */
660 if (rctx->flags & (R600_CONTEXT_INV_SHADER_CACHE |
661 R600_CONTEXT_INV_CONST_CACHE)) {
662 cp_coher_cntl |= S_0085F0_SH_ICACHE_ACTION_ENA(1) |
663 S_0085F0_SH_KCACHE_ACTION_ENA(1);
664 }
665 if (rctx->flags & (R600_CONTEXT_INV_TEX_CACHE |
666 R600_CONTEXT_STREAMOUT_FLUSH)) {
667 cp_coher_cntl |= S_0085F0_TC_ACTION_ENA(1) |
668 S_0085F0_TCL1_ACTION_ENA(1);
669 }
670 if (rctx->flags & R600_CONTEXT_FLUSH_AND_INV_CB) {
671 cp_coher_cntl |= S_0085F0_CB_ACTION_ENA(1) |
672 S_0085F0_CB0_DEST_BASE_ENA(1) |
673 S_0085F0_CB1_DEST_BASE_ENA(1) |
674 S_0085F0_CB2_DEST_BASE_ENA(1) |
675 S_0085F0_CB3_DEST_BASE_ENA(1) |
676 S_0085F0_CB4_DEST_BASE_ENA(1) |
677 S_0085F0_CB5_DEST_BASE_ENA(1) |
678 S_0085F0_CB6_DEST_BASE_ENA(1) |
679 S_0085F0_CB7_DEST_BASE_ENA(1);
680 }
681 if (rctx->flags & R600_CONTEXT_FLUSH_AND_INV_DB) {
682 cp_coher_cntl |= S_0085F0_DB_ACTION_ENA(1) |
683 S_0085F0_DB_DEST_BASE_ENA(1);
684 }
685
686 if (cp_coher_cntl) {
687 if (rctx->chip_class >= CIK) {
688 radeon_emit(cs, PKT3(PKT3_ACQUIRE_MEM, 5, 0));
689 radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */
690 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
691 radeon_emit(cs, 0xff); /* CP_COHER_SIZE_HI */
692 radeon_emit(cs, 0); /* CP_COHER_BASE */
693 radeon_emit(cs, 0); /* CP_COHER_BASE_HI */
694 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
695 } else {
696 radeon_emit(cs, PKT3(PKT3_SURFACE_SYNC, 3, 0));
697 radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */
698 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
699 radeon_emit(cs, 0); /* CP_COHER_BASE */
700 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
701 }
702 }
703
704 if (rctx->flags & R600_CONTEXT_FLUSH_AND_INV_CB_META) {
705 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
706 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_META) | EVENT_INDEX(0));
707 }
708
709 if (rctx->flags & R600_CONTEXT_WAIT_3D_IDLE) {
710 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
711 radeon_emit(cs, EVENT_TYPE(V_028A90_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
712 } else if (rctx->flags & R600_CONTEXT_STREAMOUT_FLUSH) {
713 /* Needed if streamout buffers are going to be used as a source. */
714 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
715 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
716 }
717
718 rctx->flags = 0;
719 }
720
721 const struct r600_atom si_atom_cache_flush = { si_emit_cache_flush, 11 }; /* number of CS dwords */
722
723 void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info)
724 {
725 struct r600_context *rctx = (struct r600_context *)ctx;
726 struct pipe_index_buffer ib = {};
727 uint32_t i;
728
729 if (!info->count && (info->indexed || !info->count_from_stream_output))
730 return;
731
732 if (!rctx->ps_shader || !rctx->vs_shader)
733 return;
734
735 si_update_derived_state(rctx);
736 si_vertex_buffer_update(rctx);
737
738 if (info->indexed) {
739 /* Initialize the index buffer struct. */
740 pipe_resource_reference(&ib.buffer, rctx->index_buffer.buffer);
741 ib.user_buffer = rctx->index_buffer.user_buffer;
742 ib.index_size = rctx->index_buffer.index_size;
743 ib.offset = rctx->index_buffer.offset + info->start * ib.index_size;
744
745 /* Translate or upload, if needed. */
746 r600_translate_index_buffer(rctx, &ib, info->count);
747
748 if (ib.user_buffer && !ib.buffer) {
749 r600_upload_index_buffer(rctx, &ib, info->count);
750 }
751 }
752
753 if (!si_update_draw_info_state(rctx, info, &ib))
754 return;
755
756 si_state_draw(rctx, info, &ib);
757
758 rctx->pm4_dirty_cdwords += si_pm4_dirty_dw(rctx);
759
760 /* Check flush flags. */
761 if (rctx->b.flags)
762 rctx->atoms.cache_flush->dirty = true;
763
764 si_need_cs_space(rctx, 0, TRUE);
765
766 /* Emit states. */
767 for (i = 0; i < SI_NUM_ATOMS(rctx); i++) {
768 if (rctx->atoms.array[i]->dirty) {
769 rctx->atoms.array[i]->emit(&rctx->b, rctx->atoms.array[i]);
770 rctx->atoms.array[i]->dirty = false;
771 }
772 }
773
774 si_pm4_emit_dirty(rctx);
775 rctx->pm4_dirty_cdwords = 0;
776
777 #if R600_TRACE_CS
778 if (rctx->screen->trace_bo) {
779 r600_trace_emit(rctx);
780 }
781 #endif
782
783 /* Set the depth buffer as dirty. */
784 if (rctx->framebuffer.zsbuf) {
785 struct pipe_surface *surf = rctx->framebuffer.zsbuf;
786 struct r600_texture *rtex = (struct r600_texture *)surf->texture;
787
788 rtex->dirty_level_mask |= 1 << surf->u.tex.level;
789 }
790 if (rctx->fb_compressed_cb_mask) {
791 struct pipe_surface *surf;
792 struct r600_texture *rtex;
793 unsigned mask = rctx->fb_compressed_cb_mask;
794
795 do {
796 unsigned i = u_bit_scan(&mask);
797 surf = rctx->framebuffer.cbufs[i];
798 rtex = (struct r600_texture*)surf->texture;
799
800 rtex->dirty_level_mask |= 1 << surf->u.tex.level;
801 } while (mask);
802 }
803
804 pipe_resource_reference(&ib.buffer, NULL);
805 }