projects / mesa.git / blob
? search:


3363d46b68f9f874f92bb7638064e0d366a86b61
[mesa.git] / src / gallium / drivers / radeonsi / si_state_draw.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Christian König <christian.koenig@amd.com>
25 */
26
27 #include "util/u_memory.h"
28 #include "util/u_framebuffer.h"
29 #include "util/u_blitter.h"
30 #include "tgsi/tgsi_parse.h"
31 #include "radeonsi_pipe.h"
32 #include "radeonsi_shader.h"
33 #include "si_state.h"
34 #include "sid.h"
35
36 /*
37 * Shaders
38 */
39
40 static void si_pipe_shader_vs(struct pipe_context *ctx, struct si_pipe_shader *shader)
41 {
42 struct r600_context *rctx = (struct r600_context *)ctx;
43 struct si_pm4_state *pm4;
44 unsigned num_sgprs, num_user_sgprs;
45 unsigned nparams, i, vgpr_comp_cnt;
46 uint64_t va;
47
48 si_pm4_delete_state(rctx, vs, shader->pm4);
49 pm4 = shader->pm4 = si_pm4_alloc_state(rctx);
50
51 if (pm4 == NULL)
52 return;
53
54 si_pm4_inval_shader_cache(pm4);
55
56 /* Certain attributes (position, psize, etc.) don't count as params.
57 * VS is required to export at least one param and r600_shader_from_tgsi()
58 * takes care of adding a dummy export.
59 */
60 for (nparams = 0, i = 0 ; i < shader->shader.noutput; i++) {
61 switch (shader->shader.output[i].name) {
62 case TGSI_SEMANTIC_POSITION:
63 case TGSI_SEMANTIC_PSIZE:
64 break;
65 default:
66 nparams++;
67 }
68 }
69 if (nparams < 1)
70 nparams = 1;
71
72 si_pm4_set_reg(pm4, R_0286C4_SPI_VS_OUT_CONFIG,
73 S_0286C4_VS_EXPORT_COUNT(nparams - 1));
74
75 si_pm4_set_reg(pm4, R_02870C_SPI_SHADER_POS_FORMAT,
76 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
77 S_02870C_POS1_EXPORT_FORMAT(shader->shader.vs_out_misc_write ?
78 V_02870C_SPI_SHADER_4COMP :
79 V_02870C_SPI_SHADER_NONE) |
80 S_02870C_POS2_EXPORT_FORMAT((shader->shader.clip_dist_write & 0x0F) ?
81 V_02870C_SPI_SHADER_4COMP :
82 V_02870C_SPI_SHADER_NONE) |
83 S_02870C_POS3_EXPORT_FORMAT((shader->shader.clip_dist_write & 0xF0) ?
84 V_02870C_SPI_SHADER_4COMP :
85 V_02870C_SPI_SHADER_NONE));
86
87 va = r600_resource_va(ctx->screen, (void *)shader->bo);
88 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ);
89 si_pm4_set_reg(pm4, R_00B120_SPI_SHADER_PGM_LO_VS, va >> 8);
90 si_pm4_set_reg(pm4, R_00B124_SPI_SHADER_PGM_HI_VS, va >> 40);
91
92 num_user_sgprs = SI_VS_NUM_USER_SGPR;
93 num_sgprs = shader->num_sgprs;
94 if (num_user_sgprs > num_sgprs) {
95 /* Last 2 reserved SGPRs are used for VCC */
96 num_sgprs = num_user_sgprs + 2;
97 }
98 assert(num_sgprs <= 104);
99
100 vgpr_comp_cnt = shader->shader.uses_instanceid ? 3 : 0;
101
102 si_pm4_set_reg(pm4, R_00B128_SPI_SHADER_PGM_RSRC1_VS,
103 S_00B128_VGPRS((shader->num_vgprs - 1) / 4) |
104 S_00B128_SGPRS((num_sgprs - 1) / 8) |
105 S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt));
106 si_pm4_set_reg(pm4, R_00B12C_SPI_SHADER_PGM_RSRC2_VS,
107 S_00B12C_USER_SGPR(num_user_sgprs));
108
109 if (rctx->chip_class >= CIK) {
110 si_pm4_set_reg(pm4, R_00B118_SPI_SHADER_PGM_RSRC3_VS,
111 S_00B118_CU_EN(0xffff));
112 si_pm4_set_reg(pm4, R_00B11C_SPI_SHADER_LATE_ALLOC_VS,
113 S_00B11C_LIMIT(0));
114 }
115
116 si_pm4_bind_state(rctx, vs, shader->pm4);
117 }
118
119 static void si_pipe_shader_ps(struct pipe_context *ctx, struct si_pipe_shader *shader)
120 {
121 struct r600_context *rctx = (struct r600_context *)ctx;
122 struct si_pm4_state *pm4;
123 unsigned i, exports_ps, num_cout, spi_ps_in_control, db_shader_control;
124 unsigned num_sgprs, num_user_sgprs;
125 boolean have_linear = FALSE, have_centroid = FALSE, have_perspective = FALSE;
126 unsigned fragcoord_interp_mode = 0;
127 unsigned spi_baryc_cntl, spi_ps_input_ena, spi_shader_z_format;
128 uint64_t va;
129
130 si_pm4_delete_state(rctx, ps, shader->pm4);
131 pm4 = shader->pm4 = si_pm4_alloc_state(rctx);
132
133 if (pm4 == NULL)
134 return;
135
136 si_pm4_inval_shader_cache(pm4);
137
138 db_shader_control = S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
139 for (i = 0; i < shader->shader.ninput; i++) {
140 switch (shader->shader.input[i].name) {
141 case TGSI_SEMANTIC_POSITION:
142 if (shader->shader.input[i].centroid) {
143 /* fragcoord_interp_mode will be written to
144 * SPI_BARYC_CNTL.POS_FLOAT_LOCATION
145 * Possible vaules:
146 * 0 -> Position = pixel center (default)
147 * 1 -> Position = pixel centroid
148 * 2 -> Position = iterated sample number XXX:
149 * What does this mean?
150 */
151 fragcoord_interp_mode = 1;
152 }
153 /* Fall through */
154 case TGSI_SEMANTIC_FACE:
155 continue;
156 }
157
158 if (shader->shader.input[i].interpolate == TGSI_INTERPOLATE_LINEAR)
159 have_linear = TRUE;
160 if (shader->shader.input[i].interpolate == TGSI_INTERPOLATE_PERSPECTIVE)
161 have_perspective = TRUE;
162 if (shader->shader.input[i].centroid)
163 have_centroid = TRUE;
164 }
165
166 for (i = 0; i < shader->shader.noutput; i++) {
167 if (shader->shader.output[i].name == TGSI_SEMANTIC_POSITION)
168 db_shader_control |= S_02880C_Z_EXPORT_ENABLE(1);
169 if (shader->shader.output[i].name == TGSI_SEMANTIC_STENCIL)
170 db_shader_control |= S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(1);
171 }
172 if (shader->shader.uses_kill || shader->key.ps.alpha_func != PIPE_FUNC_ALWAYS)
173 db_shader_control |= S_02880C_KILL_ENABLE(1);
174
175 exports_ps = 0;
176 num_cout = 0;
177 for (i = 0; i < shader->shader.noutput; i++) {
178 if (shader->shader.output[i].name == TGSI_SEMANTIC_POSITION ||
179 shader->shader.output[i].name == TGSI_SEMANTIC_STENCIL)
180 exports_ps |= 1;
181 else if (shader->shader.output[i].name == TGSI_SEMANTIC_COLOR) {
182 if (shader->shader.fs_write_all)
183 num_cout = shader->shader.nr_cbufs;
184 else
185 num_cout++;
186 }
187 }
188 if (!exports_ps) {
189 /* always at least export 1 component per pixel */
190 exports_ps = 2;
191 }
192
193 spi_ps_in_control = S_0286D8_NUM_INTERP(shader->shader.ninterp);
194
195 spi_baryc_cntl = 0;
196 if (have_perspective)
197 spi_baryc_cntl |= have_centroid ?
198 S_0286E0_PERSP_CENTROID_CNTL(1) : S_0286E0_PERSP_CENTER_CNTL(1);
199 if (have_linear)
200 spi_baryc_cntl |= have_centroid ?
201 S_0286E0_LINEAR_CENTROID_CNTL(1) : S_0286E0_LINEAR_CENTER_CNTL(1);
202 spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(fragcoord_interp_mode);
203
204 si_pm4_set_reg(pm4, R_0286E0_SPI_BARYC_CNTL, spi_baryc_cntl);
205 spi_ps_input_ena = shader->spi_ps_input_ena;
206 /* we need to enable at least one of them, otherwise we hang the GPU */
207 assert(G_0286CC_PERSP_SAMPLE_ENA(spi_ps_input_ena) ||
208 G_0286CC_PERSP_CENTER_ENA(spi_ps_input_ena) ||
209 G_0286CC_PERSP_CENTROID_ENA(spi_ps_input_ena) ||
210 G_0286CC_PERSP_PULL_MODEL_ENA(spi_ps_input_ena) ||
211 G_0286CC_LINEAR_SAMPLE_ENA(spi_ps_input_ena) ||
212 G_0286CC_LINEAR_CENTER_ENA(spi_ps_input_ena) ||
213 G_0286CC_LINEAR_CENTROID_ENA(spi_ps_input_ena) ||
214 G_0286CC_LINE_STIPPLE_TEX_ENA(spi_ps_input_ena));
215
216 si_pm4_set_reg(pm4, R_0286CC_SPI_PS_INPUT_ENA, spi_ps_input_ena);
217 si_pm4_set_reg(pm4, R_0286D0_SPI_PS_INPUT_ADDR, spi_ps_input_ena);
218 si_pm4_set_reg(pm4, R_0286D8_SPI_PS_IN_CONTROL, spi_ps_in_control);
219
220 if (G_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(db_shader_control))
221 spi_shader_z_format = V_028710_SPI_SHADER_32_GR;
222 else if (G_02880C_Z_EXPORT_ENABLE(db_shader_control))
223 spi_shader_z_format = V_028710_SPI_SHADER_32_R;
224 else
225 spi_shader_z_format = 0;
226 si_pm4_set_reg(pm4, R_028710_SPI_SHADER_Z_FORMAT, spi_shader_z_format);
227 si_pm4_set_reg(pm4, R_028714_SPI_SHADER_COL_FORMAT,
228 shader->spi_shader_col_format);
229 si_pm4_set_reg(pm4, R_02823C_CB_SHADER_MASK, shader->cb_shader_mask);
230
231 va = r600_resource_va(ctx->screen, (void *)shader->bo);
232 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ);
233 si_pm4_set_reg(pm4, R_00B020_SPI_SHADER_PGM_LO_PS, va >> 8);
234 si_pm4_set_reg(pm4, R_00B024_SPI_SHADER_PGM_HI_PS, va >> 40);
235
236 num_user_sgprs = SI_PS_NUM_USER_SGPR;
237 num_sgprs = shader->num_sgprs;
238 if (num_user_sgprs > num_sgprs) {
239 /* Last 2 reserved SGPRs are used for VCC */
240 num_sgprs = num_user_sgprs + 2;
241 }
242 assert(num_sgprs <= 104);
243
244 si_pm4_set_reg(pm4, R_00B028_SPI_SHADER_PGM_RSRC1_PS,
245 S_00B028_VGPRS((shader->num_vgprs - 1) / 4) |
246 S_00B028_SGPRS((num_sgprs - 1) / 8));
247 si_pm4_set_reg(pm4, R_00B02C_SPI_SHADER_PGM_RSRC2_PS,
248 S_00B02C_EXTRA_LDS_SIZE(shader->lds_size) |
249 S_00B02C_USER_SGPR(num_user_sgprs));
250 if (rctx->chip_class >= CIK) {
251 si_pm4_set_reg(pm4, R_00B01C_SPI_SHADER_PGM_RSRC3_PS,
252 S_00B01C_CU_EN(0xffff));
253 }
254
255 si_pm4_set_reg(pm4, R_02880C_DB_SHADER_CONTROL, db_shader_control);
256
257 shader->sprite_coord_enable = rctx->sprite_coord_enable;
258 si_pm4_bind_state(rctx, ps, shader->pm4);
259 }
260
261 /*
262 * Drawing
263 */
264
265 static unsigned si_conv_pipe_prim(unsigned pprim)
266 {
267 static const unsigned prim_conv[] = {
268 [PIPE_PRIM_POINTS] = V_008958_DI_PT_POINTLIST,
269 [PIPE_PRIM_LINES] = V_008958_DI_PT_LINELIST,
270 [PIPE_PRIM_LINE_LOOP] = V_008958_DI_PT_LINELOOP,
271 [PIPE_PRIM_LINE_STRIP] = V_008958_DI_PT_LINESTRIP,
272 [PIPE_PRIM_TRIANGLES] = V_008958_DI_PT_TRILIST,
273 [PIPE_PRIM_TRIANGLE_STRIP] = V_008958_DI_PT_TRISTRIP,
274 [PIPE_PRIM_TRIANGLE_FAN] = V_008958_DI_PT_TRIFAN,
275 [PIPE_PRIM_QUADS] = V_008958_DI_PT_QUADLIST,
276 [PIPE_PRIM_QUAD_STRIP] = V_008958_DI_PT_QUADSTRIP,
277 [PIPE_PRIM_POLYGON] = V_008958_DI_PT_POLYGON,
278 [PIPE_PRIM_LINES_ADJACENCY] = ~0,
279 [PIPE_PRIM_LINE_STRIP_ADJACENCY] = ~0,
280 [PIPE_PRIM_TRIANGLES_ADJACENCY] = ~0,
281 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY] = ~0
282 };
283 unsigned result = prim_conv[pprim];
284 if (result == ~0) {
285 R600_ERR("unsupported primitive type %d\n", pprim);
286 }
287 return result;
288 }
289
290 static bool si_update_draw_info_state(struct r600_context *rctx,
291 const struct pipe_draw_info *info)
292 {
293 struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx);
294 struct si_shader *vs = &rctx->vs_shader->current->shader;
295 unsigned prim = si_conv_pipe_prim(info->mode);
296 unsigned ls_mask = 0;
297
298 if (pm4 == NULL)
299 return false;
300
301 if (prim == ~0) {
302 FREE(pm4);
303 return false;
304 }
305
306 if (rctx->chip_class >= CIK)
307 si_pm4_set_reg(pm4, R_030908_VGT_PRIMITIVE_TYPE, prim);
308 else
309 si_pm4_set_reg(pm4, R_008958_VGT_PRIMITIVE_TYPE, prim);
310 si_pm4_set_reg(pm4, R_028400_VGT_MAX_VTX_INDX, ~0);
311 si_pm4_set_reg(pm4, R_028404_VGT_MIN_VTX_INDX, 0);
312 si_pm4_set_reg(pm4, R_028408_VGT_INDX_OFFSET,
313 info->indexed ? info->index_bias : info->start);
314 si_pm4_set_reg(pm4, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, info->restart_index);
315 si_pm4_set_reg(pm4, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, info->primitive_restart);
316 si_pm4_set_reg(pm4, R_00B130_SPI_SHADER_USER_DATA_VS_0 + SI_SGPR_START_INSTANCE * 4,
317 info->start_instance);
318
319 if (prim == V_008958_DI_PT_LINELIST)
320 ls_mask = 1;
321 else if (prim == V_008958_DI_PT_LINESTRIP)
322 ls_mask = 2;
323 si_pm4_set_reg(pm4, R_028A0C_PA_SC_LINE_STIPPLE,
324 S_028A0C_AUTO_RESET_CNTL(ls_mask) |
325 rctx->pa_sc_line_stipple);
326
327 if (info->mode == PIPE_PRIM_QUADS || info->mode == PIPE_PRIM_QUAD_STRIP || info->mode == PIPE_PRIM_POLYGON) {
328 si_pm4_set_reg(pm4, R_028814_PA_SU_SC_MODE_CNTL,
329 S_028814_PROVOKING_VTX_LAST(1) | rctx->pa_su_sc_mode_cntl);
330 } else {
331 si_pm4_set_reg(pm4, R_028814_PA_SU_SC_MODE_CNTL, rctx->pa_su_sc_mode_cntl);
332 }
333 si_pm4_set_reg(pm4, R_02881C_PA_CL_VS_OUT_CNTL,
334 S_02881C_USE_VTX_POINT_SIZE(vs->vs_out_point_size) |
335 S_02881C_VS_OUT_CCDIST0_VEC_ENA((vs->clip_dist_write & 0x0F) != 0) |
336 S_02881C_VS_OUT_CCDIST1_VEC_ENA((vs->clip_dist_write & 0xF0) != 0) |
337 S_02881C_VS_OUT_MISC_VEC_ENA(vs->vs_out_misc_write) |
338 (rctx->queued.named.rasterizer->clip_plane_enable &
339 vs->clip_dist_write));
340 si_pm4_set_reg(pm4, R_028810_PA_CL_CLIP_CNTL,
341 rctx->queued.named.rasterizer->pa_cl_clip_cntl |
342 (vs->clip_dist_write ? 0 :
343 rctx->queued.named.rasterizer->clip_plane_enable & 0x3F));
344
345 si_pm4_set_state(rctx, draw_info, pm4);
346 return true;
347 }
348
349 static void si_update_spi_map(struct r600_context *rctx)
350 {
351 struct si_shader *ps = &rctx->ps_shader->current->shader;
352 struct si_shader *vs = &rctx->vs_shader->current->shader;
353 struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx);
354 unsigned i, j, tmp;
355
356 for (i = 0; i < ps->ninput; i++) {
357 unsigned name = ps->input[i].name;
358 unsigned param_offset = ps->input[i].param_offset;
359
360 if (name == TGSI_SEMANTIC_POSITION)
361 /* Read from preloaded VGPRs, not parameters */
362 continue;
363
364 bcolor:
365 tmp = 0;
366
367 if (ps->input[i].interpolate == TGSI_INTERPOLATE_CONSTANT ||
368 (ps->input[i].interpolate == TGSI_INTERPOLATE_COLOR &&
369 rctx->ps_shader->current->key.ps.flatshade)) {
370 tmp |= S_028644_FLAT_SHADE(1);
371 }
372
373 if (name == TGSI_SEMANTIC_GENERIC &&
374 rctx->sprite_coord_enable & (1 << ps->input[i].sid)) {
375 tmp |= S_028644_PT_SPRITE_TEX(1);
376 }
377
378 for (j = 0; j < vs->noutput; j++) {
379 if (name == vs->output[j].name &&
380 ps->input[i].sid == vs->output[j].sid) {
381 tmp |= S_028644_OFFSET(vs->output[j].param_offset);
382 break;
383 }
384 }
385
386 if (j == vs->noutput) {
387 /* No corresponding output found, load defaults into input */
388 tmp |= S_028644_OFFSET(0x20);
389 }
390
391 si_pm4_set_reg(pm4,
392 R_028644_SPI_PS_INPUT_CNTL_0 + param_offset * 4,
393 tmp);
394
395 if (name == TGSI_SEMANTIC_COLOR &&
396 rctx->ps_shader->current->key.ps.color_two_side) {
397 name = TGSI_SEMANTIC_BCOLOR;
398 param_offset++;
399 goto bcolor;
400 }
401 }
402
403 si_pm4_set_state(rctx, spi, pm4);
404 }
405
406 static void si_update_derived_state(struct r600_context *rctx)
407 {
408 struct pipe_context * ctx = (struct pipe_context*)rctx;
409 unsigned vs_dirty = 0, ps_dirty = 0;
410
411 if (!rctx->blitter->running) {
412 /* Flush depth textures which need to be flushed. */
413 if (rctx->vs_samplers.depth_texture_mask) {
414 si_flush_depth_textures(rctx, &rctx->vs_samplers);
415 }
416 if (rctx->ps_samplers.depth_texture_mask) {
417 si_flush_depth_textures(rctx, &rctx->ps_samplers);
418 }
419 }
420
421 si_shader_select(ctx, rctx->vs_shader, &vs_dirty);
422
423 if (!rctx->vs_shader->current->pm4) {
424 si_pipe_shader_vs(ctx, rctx->vs_shader->current);
425 vs_dirty = 0;
426 }
427
428 if (vs_dirty) {
429 si_pm4_bind_state(rctx, vs, rctx->vs_shader->current->pm4);
430 }
431
432
433 si_shader_select(ctx, rctx->ps_shader, &ps_dirty);
434
435 if (!rctx->ps_shader->current->pm4) {
436 si_pipe_shader_ps(ctx, rctx->ps_shader->current);
437 ps_dirty = 0;
438 }
439 if (!rctx->ps_shader->current->bo) {
440 if (!rctx->dummy_pixel_shader->pm4)
441 si_pipe_shader_ps(ctx, rctx->dummy_pixel_shader);
442 else
443 si_pm4_bind_state(rctx, vs, rctx->dummy_pixel_shader->pm4);
444
445 ps_dirty = 0;
446 }
447
448 if (ps_dirty) {
449 si_pm4_bind_state(rctx, ps, rctx->ps_shader->current->pm4);
450 }
451
452 if (si_pm4_state_changed(rctx, ps) || si_pm4_state_changed(rctx, vs)) {
453 /* XXX: Emitting the PS state even when only the VS changed
454 * fixes random failures with piglit glsl-max-varyings.
455 * Not sure why...
456 */
457 rctx->emitted.named.ps = NULL;
458 si_update_spi_map(rctx);
459 }
460 }
461
462 static void si_constant_buffer_update(struct r600_context *rctx)
463 {
464 struct pipe_context *ctx = &rctx->context;
465 struct si_pm4_state *pm4;
466 unsigned shader, i;
467 uint64_t va;
468
469 if (!rctx->constbuf_state[PIPE_SHADER_VERTEX].dirty_mask &&
470 !rctx->constbuf_state[PIPE_SHADER_FRAGMENT].dirty_mask)
471 return;
472
473 for (shader = PIPE_SHADER_VERTEX ; shader <= PIPE_SHADER_FRAGMENT; shader++) {
474 struct r600_constbuf_state *state = &rctx->constbuf_state[shader];
475
476 pm4 = CALLOC_STRUCT(si_pm4_state);
477 if (!pm4)
478 continue;
479
480 si_pm4_inval_shader_cache(pm4);
481 si_pm4_sh_data_begin(pm4);
482
483 for (i = 0; i < 2; i++) {
484 if (state->enabled_mask & (1 << i)) {
485 struct pipe_constant_buffer *cb = &state->cb[i];
486 struct si_resource *rbuffer = si_resource(cb->buffer);
487
488 va = r600_resource_va(ctx->screen, (void*)rbuffer);
489 va += cb->buffer_offset;
490
491 si_pm4_add_bo(pm4, rbuffer, RADEON_USAGE_READ);
492
493 /* Fill in a T# buffer resource description */
494 si_pm4_sh_data_add(pm4, va);
495 si_pm4_sh_data_add(pm4, (S_008F04_BASE_ADDRESS_HI(va >> 32) |
496 S_008F04_STRIDE(0)));
497 si_pm4_sh_data_add(pm4, cb->buffer_size);
498 si_pm4_sh_data_add(pm4, S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
499 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
500 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
501 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
502 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
503 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32));
504 } else {
505 /* Fill in an empty T# buffer resource description */
506 si_pm4_sh_data_add(pm4, 0);
507 si_pm4_sh_data_add(pm4, 0);
508 si_pm4_sh_data_add(pm4, 0);
509 si_pm4_sh_data_add(pm4, 0);
510 }
511 }
512
513 switch (shader) {
514 case PIPE_SHADER_VERTEX:
515 si_pm4_sh_data_end(pm4, R_00B130_SPI_SHADER_USER_DATA_VS_0, SI_SGPR_CONST);
516 si_pm4_set_state(rctx, vs_const, pm4);
517 break;
518
519 case PIPE_SHADER_FRAGMENT:
520 si_pm4_sh_data_end(pm4, R_00B030_SPI_SHADER_USER_DATA_PS_0, SI_SGPR_CONST);
521 si_pm4_set_state(rctx, ps_const, pm4);
522 break;
523
524 default:
525 R600_ERR("unsupported %d\n", shader);
526 FREE(pm4);
527 return;
528 }
529
530 state->dirty_mask = 0;
531 }
532 }
533
534 static void si_vertex_buffer_update(struct r600_context *rctx)
535 {
536 struct pipe_context *ctx = &rctx->context;
537 struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx);
538 bool bound[PIPE_MAX_ATTRIBS] = {};
539 unsigned i, count;
540 uint64_t va;
541
542 si_pm4_inval_texture_cache(pm4);
543
544 /* bind vertex buffer once */
545 count = rctx->vertex_elements->count;
546 assert(count <= 256 / 4);
547
548 si_pm4_sh_data_begin(pm4);
549 for (i = 0 ; i < count; i++) {
550 struct pipe_vertex_element *ve = &rctx->vertex_elements->elements[i];
551 struct pipe_vertex_buffer *vb;
552 struct si_resource *rbuffer;
553 unsigned offset;
554
555 if (ve->vertex_buffer_index >= rctx->nr_vertex_buffers)
556 continue;
557
558 vb = &rctx->vertex_buffer[ve->vertex_buffer_index];
559 rbuffer = (struct si_resource*)vb->buffer;
560 if (rbuffer == NULL)
561 continue;
562
563 offset = 0;
564 offset += vb->buffer_offset;
565 offset += ve->src_offset;
566
567 va = r600_resource_va(ctx->screen, (void*)rbuffer);
568 va += offset;
569
570 /* Fill in T# buffer resource description */
571 si_pm4_sh_data_add(pm4, va & 0xFFFFFFFF);
572 si_pm4_sh_data_add(pm4, (S_008F04_BASE_ADDRESS_HI(va >> 32) |
573 S_008F04_STRIDE(vb->stride)));
574 if (vb->stride)
575 /* Round up by rounding down and adding 1 */
576 si_pm4_sh_data_add(pm4,
577 (vb->buffer->width0 - offset -
578 util_format_get_blocksize(ve->src_format)) /
579 vb->stride + 1);
580 else
581 si_pm4_sh_data_add(pm4, vb->buffer->width0 - offset);
582 si_pm4_sh_data_add(pm4, rctx->vertex_elements->rsrc_word3[i]);
583
584 if (!bound[ve->vertex_buffer_index]) {
585 si_pm4_add_bo(pm4, rbuffer, RADEON_USAGE_READ);
586 bound[ve->vertex_buffer_index] = true;
587 }
588 }
589 si_pm4_sh_data_end(pm4, R_00B130_SPI_SHADER_USER_DATA_VS_0, SI_SGPR_VERTEX_BUFFER);
590 si_pm4_set_state(rctx, vertex_buffers, pm4);
591 }
592
593 static void si_state_draw(struct r600_context *rctx,
594 const struct pipe_draw_info *info,
595 const struct pipe_index_buffer *ib)
596 {
597 struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx);
598
599 if (pm4 == NULL)
600 return;
601
602 /* queries need some special values
603 * (this is non-zero if any query is active) */
604 if (rctx->num_cs_dw_queries_suspend) {
605 struct si_state_dsa *dsa = rctx->queued.named.dsa;
606
607 si_pm4_set_reg(pm4, R_028004_DB_COUNT_CONTROL,
608 S_028004_PERFECT_ZPASS_COUNTS(1));
609 si_pm4_set_reg(pm4, R_02800C_DB_RENDER_OVERRIDE,
610 dsa->db_render_override |
611 S_02800C_NOOP_CULL_DISABLE(1));
612 }
613
614 /* draw packet */
615 si_pm4_cmd_begin(pm4, PKT3_INDEX_TYPE);
616 if (ib->index_size == 4) {
617 si_pm4_cmd_add(pm4, V_028A7C_VGT_INDEX_32 | (R600_BIG_ENDIAN ?
618 V_028A7C_VGT_DMA_SWAP_32_BIT : 0));
619 } else {
620 si_pm4_cmd_add(pm4, V_028A7C_VGT_INDEX_16 | (R600_BIG_ENDIAN ?
621 V_028A7C_VGT_DMA_SWAP_16_BIT : 0));
622 }
623 si_pm4_cmd_end(pm4, rctx->predicate_drawing);
624
625 si_pm4_cmd_begin(pm4, PKT3_NUM_INSTANCES);
626 si_pm4_cmd_add(pm4, info->instance_count);
627 si_pm4_cmd_end(pm4, rctx->predicate_drawing);
628
629 if (info->indexed) {
630 uint32_t max_size = (ib->buffer->width0 - ib->offset) /
631 rctx->index_buffer.index_size;
632 uint64_t va;
633 va = r600_resource_va(&rctx->screen->screen, ib->buffer);
634 va += ib->offset;
635
636 si_pm4_add_bo(pm4, (struct si_resource *)ib->buffer, RADEON_USAGE_READ);
637 si_cmd_draw_index_2(pm4, max_size, va, info->count,
638 V_0287F0_DI_SRC_SEL_DMA,
639 rctx->predicate_drawing);
640 } else {
641 uint32_t initiator = V_0287F0_DI_SRC_SEL_AUTO_INDEX;
642 initiator |= S_0287F0_USE_OPAQUE(!!info->count_from_stream_output);
643 si_cmd_draw_index_auto(pm4, info->count, initiator, rctx->predicate_drawing);
644 }
645 si_pm4_set_state(rctx, draw, pm4);
646 }
647
648 void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info)
649 {
650 struct r600_context *rctx = (struct r600_context *)ctx;
651 struct pipe_index_buffer ib = {};
652 uint32_t cp_coher_cntl;
653
654 if (!info->count && (info->indexed || !info->count_from_stream_output))
655 return;
656
657 if (!rctx->ps_shader || !rctx->vs_shader)
658 return;
659
660 si_update_derived_state(rctx);
661 si_constant_buffer_update(rctx);
662 si_vertex_buffer_update(rctx);
663
664 if (info->indexed) {
665 /* Initialize the index buffer struct. */
666 pipe_resource_reference(&ib.buffer, rctx->index_buffer.buffer);
667 ib.user_buffer = rctx->index_buffer.user_buffer;
668 ib.index_size = rctx->index_buffer.index_size;
669 ib.offset = rctx->index_buffer.offset + info->start * ib.index_size;
670
671 /* Translate or upload, if needed. */
672 r600_translate_index_buffer(rctx, &ib, info->count);
673
674 if (ib.user_buffer && !ib.buffer) {
675 r600_upload_index_buffer(rctx, &ib, info->count);
676 }
677
678 } else if (info->count_from_stream_output) {
679 r600_context_draw_opaque_count(rctx, (struct r600_so_target*)info->count_from_stream_output);
680 }
681
682 rctx->vs_shader_so_strides = rctx->vs_shader->current->so_strides;
683
684 if (!si_update_draw_info_state(rctx, info))
685 return;
686
687 si_state_draw(rctx, info, &ib);
688
689 cp_coher_cntl = si_pm4_sync_flags(rctx);
690 if (cp_coher_cntl) {
691 struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx);
692
693 if (pm4 == NULL)
694 return;
695
696 si_cmd_surface_sync(pm4, cp_coher_cntl);
697 si_pm4_set_state(rctx, sync, pm4);
698 }
699
700 /* Emit states. */
701 rctx->pm4_dirty_cdwords += si_pm4_dirty_dw(rctx);
702
703 si_need_cs_space(rctx, 0, TRUE);
704
705 si_pm4_emit_dirty(rctx);
706 rctx->pm4_dirty_cdwords = 0;
707
708 #if R600_TRACE_CS
709 if (rctx->screen->trace_bo) {
710 r600_trace_emit(rctx);
711 }
712 #endif
713
714 #if 0
715 /* Enable stream out if needed. */
716 if (rctx->streamout_start) {
717 r600_context_streamout_begin(rctx);
718 rctx->streamout_start = FALSE;
719 }
720 #endif
721
722 rctx->flags |= R600_CONTEXT_DST_CACHES_DIRTY;
723
724 /* Set the depth buffer as dirty. */
725 if (rctx->framebuffer.zsbuf) {
726 struct pipe_surface *surf = rctx->framebuffer.zsbuf;
727 struct r600_texture *rtex = (struct r600_texture *)surf->texture;
728
729 rtex->dirty_level_mask |= 1 << surf->u.tex.level;
730 }
731
732 pipe_resource_reference(&ib.buffer, NULL);
733 }