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radeonsi: get InstanceID from VGPR1 (or VGPR2 for tess) instead of VGPR3
[mesa.git] / src / gallium / drivers / radeonsi / si_state_draw.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Christian König <christian.koenig@amd.com>
25 */
26
27 #include "si_pipe.h"
28 #include "radeon/r600_cs.h"
29 #include "sid.h"
30 #include "gfx9d.h"
31
32 #include "util/u_index_modify.h"
33 #include "util/u_upload_mgr.h"
34 #include "util/u_prim.h"
35
36 #include "ac_debug.h"
37
38 static unsigned si_conv_pipe_prim(unsigned mode)
39 {
40 static const unsigned prim_conv[] = {
41 [PIPE_PRIM_POINTS] = V_008958_DI_PT_POINTLIST,
42 [PIPE_PRIM_LINES] = V_008958_DI_PT_LINELIST,
43 [PIPE_PRIM_LINE_LOOP] = V_008958_DI_PT_LINELOOP,
44 [PIPE_PRIM_LINE_STRIP] = V_008958_DI_PT_LINESTRIP,
45 [PIPE_PRIM_TRIANGLES] = V_008958_DI_PT_TRILIST,
46 [PIPE_PRIM_TRIANGLE_STRIP] = V_008958_DI_PT_TRISTRIP,
47 [PIPE_PRIM_TRIANGLE_FAN] = V_008958_DI_PT_TRIFAN,
48 [PIPE_PRIM_QUADS] = V_008958_DI_PT_QUADLIST,
49 [PIPE_PRIM_QUAD_STRIP] = V_008958_DI_PT_QUADSTRIP,
50 [PIPE_PRIM_POLYGON] = V_008958_DI_PT_POLYGON,
51 [PIPE_PRIM_LINES_ADJACENCY] = V_008958_DI_PT_LINELIST_ADJ,
52 [PIPE_PRIM_LINE_STRIP_ADJACENCY] = V_008958_DI_PT_LINESTRIP_ADJ,
53 [PIPE_PRIM_TRIANGLES_ADJACENCY] = V_008958_DI_PT_TRILIST_ADJ,
54 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY] = V_008958_DI_PT_TRISTRIP_ADJ,
55 [PIPE_PRIM_PATCHES] = V_008958_DI_PT_PATCH,
56 [R600_PRIM_RECTANGLE_LIST] = V_008958_DI_PT_RECTLIST
57 };
58 assert(mode < ARRAY_SIZE(prim_conv));
59 return prim_conv[mode];
60 }
61
62 static unsigned si_conv_prim_to_gs_out(unsigned mode)
63 {
64 static const int prim_conv[] = {
65 [PIPE_PRIM_POINTS] = V_028A6C_OUTPRIM_TYPE_POINTLIST,
66 [PIPE_PRIM_LINES] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
67 [PIPE_PRIM_LINE_LOOP] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
68 [PIPE_PRIM_LINE_STRIP] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
69 [PIPE_PRIM_TRIANGLES] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
70 [PIPE_PRIM_TRIANGLE_STRIP] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
71 [PIPE_PRIM_TRIANGLE_FAN] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
72 [PIPE_PRIM_QUADS] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
73 [PIPE_PRIM_QUAD_STRIP] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
74 [PIPE_PRIM_POLYGON] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
75 [PIPE_PRIM_LINES_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
76 [PIPE_PRIM_LINE_STRIP_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
77 [PIPE_PRIM_TRIANGLES_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
78 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
79 [PIPE_PRIM_PATCHES] = V_028A6C_OUTPRIM_TYPE_POINTLIST,
80 [R600_PRIM_RECTANGLE_LIST] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
81 };
82 assert(mode < ARRAY_SIZE(prim_conv));
83
84 return prim_conv[mode];
85 }
86
87 /**
88 * This calculates the LDS size for tessellation shaders (VS, TCS, TES).
89 * LS.LDS_SIZE is shared by all 3 shader stages.
90 *
91 * The information about LDS and other non-compile-time parameters is then
92 * written to userdata SGPRs.
93 */
94 static void si_emit_derived_tess_state(struct si_context *sctx,
95 const struct pipe_draw_info *info,
96 unsigned *num_patches)
97 {
98 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
99 struct si_shader *ls_current;
100 struct si_shader_selector *ls;
101 /* The TES pointer will only be used for sctx->last_tcs.
102 * It would be wrong to think that TCS = TES. */
103 struct si_shader_selector *tcs =
104 sctx->tcs_shader.cso ? sctx->tcs_shader.cso : sctx->tes_shader.cso;
105 unsigned tes_sh_base = sctx->shader_userdata.sh_base[PIPE_SHADER_TESS_EVAL];
106 unsigned num_tcs_input_cp = info->vertices_per_patch;
107 unsigned num_tcs_output_cp, num_tcs_inputs, num_tcs_outputs;
108 unsigned num_tcs_patch_outputs;
109 unsigned input_vertex_size, output_vertex_size, pervertex_output_patch_size;
110 unsigned input_patch_size, output_patch_size, output_patch0_offset;
111 unsigned perpatch_output_offset, lds_size;
112 unsigned tcs_in_layout, tcs_out_layout, tcs_out_offsets;
113 unsigned offchip_layout, hardware_lds_size, ls_hs_config;
114
115 /* Since GFX9 has merged LS-HS in the TCS state, set LS = TCS. */
116 if (sctx->b.chip_class >= GFX9) {
117 if (sctx->tcs_shader.cso)
118 ls_current = sctx->tcs_shader.current;
119 else
120 ls_current = sctx->fixed_func_tcs_shader.current;
121
122 ls = ls_current->key.part.tcs.ls;
123 } else {
124 ls_current = sctx->vs_shader.current;
125 ls = sctx->vs_shader.cso;
126 }
127
128 if (sctx->last_ls == ls_current &&
129 sctx->last_tcs == tcs &&
130 sctx->last_tes_sh_base == tes_sh_base &&
131 sctx->last_num_tcs_input_cp == num_tcs_input_cp) {
132 *num_patches = sctx->last_num_patches;
133 return;
134 }
135
136 sctx->last_ls = ls_current;
137 sctx->last_tcs = tcs;
138 sctx->last_tes_sh_base = tes_sh_base;
139 sctx->last_num_tcs_input_cp = num_tcs_input_cp;
140
141 /* This calculates how shader inputs and outputs among VS, TCS, and TES
142 * are laid out in LDS. */
143 num_tcs_inputs = util_last_bit64(ls->outputs_written);
144
145 if (sctx->tcs_shader.cso) {
146 num_tcs_outputs = util_last_bit64(tcs->outputs_written);
147 num_tcs_output_cp = tcs->info.properties[TGSI_PROPERTY_TCS_VERTICES_OUT];
148 num_tcs_patch_outputs = util_last_bit64(tcs->patch_outputs_written);
149 } else {
150 /* No TCS. Route varyings from LS to TES. */
151 num_tcs_outputs = num_tcs_inputs;
152 num_tcs_output_cp = num_tcs_input_cp;
153 num_tcs_patch_outputs = 2; /* TESSINNER + TESSOUTER */
154 }
155
156 input_vertex_size = num_tcs_inputs * 16;
157 output_vertex_size = num_tcs_outputs * 16;
158
159 input_patch_size = num_tcs_input_cp * input_vertex_size;
160
161 pervertex_output_patch_size = num_tcs_output_cp * output_vertex_size;
162 output_patch_size = pervertex_output_patch_size + num_tcs_patch_outputs * 16;
163
164 /* Ensure that we only need one wave per SIMD so we don't need to check
165 * resource usage. Also ensures that the number of tcs in and out
166 * vertices per threadgroup are at most 256.
167 */
168 *num_patches = 64 / MAX2(num_tcs_input_cp, num_tcs_output_cp) * 4;
169
170 /* Make sure that the data fits in LDS. This assumes the shaders only
171 * use LDS for the inputs and outputs.
172 */
173 hardware_lds_size = sctx->b.chip_class >= CIK ? 65536 : 32768;
174 *num_patches = MIN2(*num_patches, hardware_lds_size / (input_patch_size +
175 output_patch_size));
176
177 /* Make sure the output data fits in the offchip buffer */
178 *num_patches = MIN2(*num_patches,
179 (sctx->screen->tess_offchip_block_dw_size * 4) /
180 output_patch_size);
181
182 /* Not necessary for correctness, but improves performance. The
183 * specific value is taken from the proprietary driver.
184 */
185 *num_patches = MIN2(*num_patches, 40);
186
187 /* SI bug workaround - limit LS-HS threadgroups to only one wave. */
188 if (sctx->b.chip_class == SI) {
189 unsigned one_wave = 64 / MAX2(num_tcs_input_cp, num_tcs_output_cp);
190 *num_patches = MIN2(*num_patches, one_wave);
191 }
192
193 sctx->last_num_patches = *num_patches;
194
195 output_patch0_offset = input_patch_size * *num_patches;
196 perpatch_output_offset = output_patch0_offset + pervertex_output_patch_size;
197
198 /* Compute userdata SGPRs. */
199 assert(((input_vertex_size / 4) & ~0xff) == 0);
200 assert(((output_vertex_size / 4) & ~0xff) == 0);
201 assert(((input_patch_size / 4) & ~0x1fff) == 0);
202 assert(((output_patch_size / 4) & ~0x1fff) == 0);
203 assert(((output_patch0_offset / 16) & ~0xffff) == 0);
204 assert(((perpatch_output_offset / 16) & ~0xffff) == 0);
205 assert(num_tcs_input_cp <= 32);
206 assert(num_tcs_output_cp <= 32);
207
208 tcs_in_layout = S_VS_STATE_LS_OUT_PATCH_SIZE(input_patch_size / 4) |
209 S_VS_STATE_LS_OUT_VERTEX_SIZE(input_vertex_size / 4);
210 tcs_out_layout = (output_patch_size / 4) |
211 ((output_vertex_size / 4) << 13);
212 tcs_out_offsets = (output_patch0_offset / 16) |
213 ((perpatch_output_offset / 16) << 16);
214 offchip_layout = (pervertex_output_patch_size * *num_patches << 16) |
215 (num_tcs_output_cp << 9) | *num_patches;
216
217 /* Compute the LDS size. */
218 lds_size = output_patch0_offset + output_patch_size * *num_patches;
219
220 if (sctx->b.chip_class >= CIK) {
221 assert(lds_size <= 65536);
222 lds_size = align(lds_size, 512) / 512;
223 } else {
224 assert(lds_size <= 32768);
225 lds_size = align(lds_size, 256) / 256;
226 }
227
228 /* Set SI_SGPR_VS_STATE_BITS. */
229 sctx->current_vs_state &= C_VS_STATE_LS_OUT_PATCH_SIZE &
230 C_VS_STATE_LS_OUT_VERTEX_SIZE;
231 sctx->current_vs_state |= tcs_in_layout;
232
233 if (sctx->b.chip_class >= GFX9) {
234 unsigned hs_rsrc2 = ls_current->config.rsrc2 |
235 S_00B42C_LDS_SIZE(lds_size);
236
237 radeon_set_sh_reg(cs, R_00B42C_SPI_SHADER_PGM_RSRC2_HS, hs_rsrc2);
238
239 /* Set userdata SGPRs for merged LS-HS. */
240 radeon_set_sh_reg_seq(cs,
241 R_00B430_SPI_SHADER_USER_DATA_LS_0 +
242 GFX9_SGPR_TCS_OFFCHIP_LAYOUT * 4, 3);
243 radeon_emit(cs, offchip_layout);
244 radeon_emit(cs, tcs_out_offsets);
245 radeon_emit(cs, tcs_out_layout | (num_tcs_input_cp << 26));
246 } else {
247 unsigned ls_rsrc2 = ls_current->config.rsrc2;
248
249 si_multiwave_lds_size_workaround(sctx->screen, &lds_size);
250 ls_rsrc2 |= S_00B52C_LDS_SIZE(lds_size);
251
252 /* Due to a hw bug, RSRC2_LS must be written twice with another
253 * LS register written in between. */
254 if (sctx->b.chip_class == CIK && sctx->b.family != CHIP_HAWAII)
255 radeon_set_sh_reg(cs, R_00B52C_SPI_SHADER_PGM_RSRC2_LS, ls_rsrc2);
256 radeon_set_sh_reg_seq(cs, R_00B528_SPI_SHADER_PGM_RSRC1_LS, 2);
257 radeon_emit(cs, ls_current->config.rsrc1);
258 radeon_emit(cs, ls_rsrc2);
259
260 /* Set userdata SGPRs for TCS. */
261 radeon_set_sh_reg_seq(cs,
262 R_00B430_SPI_SHADER_USER_DATA_HS_0 + GFX6_SGPR_TCS_OFFCHIP_LAYOUT * 4, 4);
263 radeon_emit(cs, offchip_layout);
264 radeon_emit(cs, tcs_out_offsets);
265 radeon_emit(cs, tcs_out_layout | (num_tcs_input_cp << 26));
266 radeon_emit(cs, tcs_in_layout);
267 }
268
269 /* Set userdata SGPRs for TES. */
270 radeon_set_sh_reg_seq(cs, tes_sh_base + SI_SGPR_TES_OFFCHIP_LAYOUT * 4, 1);
271 radeon_emit(cs, offchip_layout);
272
273 ls_hs_config = S_028B58_NUM_PATCHES(*num_patches) |
274 S_028B58_HS_NUM_INPUT_CP(num_tcs_input_cp) |
275 S_028B58_HS_NUM_OUTPUT_CP(num_tcs_output_cp);
276
277 if (sctx->b.chip_class >= CIK)
278 radeon_set_context_reg_idx(cs, R_028B58_VGT_LS_HS_CONFIG, 2,
279 ls_hs_config);
280 else
281 radeon_set_context_reg(cs, R_028B58_VGT_LS_HS_CONFIG,
282 ls_hs_config);
283 }
284
285 static unsigned si_num_prims_for_vertices(const struct pipe_draw_info *info)
286 {
287 switch (info->mode) {
288 case PIPE_PRIM_PATCHES:
289 return info->count / info->vertices_per_patch;
290 case R600_PRIM_RECTANGLE_LIST:
291 return info->count / 3;
292 default:
293 return u_prims_for_vertices(info->mode, info->count);
294 }
295 }
296
297 static unsigned
298 si_get_init_multi_vgt_param(struct si_screen *sscreen,
299 union si_vgt_param_key *key)
300 {
301 STATIC_ASSERT(sizeof(union si_vgt_param_key) == 4);
302 unsigned max_primgroup_in_wave = 2;
303
304 /* SWITCH_ON_EOP(0) is always preferable. */
305 bool wd_switch_on_eop = false;
306 bool ia_switch_on_eop = false;
307 bool ia_switch_on_eoi = false;
308 bool partial_vs_wave = false;
309 bool partial_es_wave = false;
310
311 if (key->u.uses_tess) {
312 /* SWITCH_ON_EOI must be set if PrimID is used. */
313 if (key->u.tcs_tes_uses_prim_id)
314 ia_switch_on_eoi = true;
315
316 /* Bug with tessellation and GS on Bonaire and older 2 SE chips. */
317 if ((sscreen->b.family == CHIP_TAHITI ||
318 sscreen->b.family == CHIP_PITCAIRN ||
319 sscreen->b.family == CHIP_BONAIRE) &&
320 key->u.uses_gs)
321 partial_vs_wave = true;
322
323 /* Needed for 028B6C_DISTRIBUTION_MODE != 0 */
324 if (sscreen->has_distributed_tess) {
325 if (key->u.uses_gs) {
326 if (sscreen->b.chip_class <= VI)
327 partial_es_wave = true;
328
329 /* GPU hang workaround. */
330 if (sscreen->b.family == CHIP_TONGA ||
331 sscreen->b.family == CHIP_FIJI ||
332 sscreen->b.family == CHIP_POLARIS10 ||
333 sscreen->b.family == CHIP_POLARIS11)
334 partial_vs_wave = true;
335 } else {
336 partial_vs_wave = true;
337 }
338 }
339 }
340
341 /* This is a hardware requirement. */
342 if (key->u.line_stipple_enabled ||
343 (sscreen->b.debug_flags & DBG_SWITCH_ON_EOP)) {
344 ia_switch_on_eop = true;
345 wd_switch_on_eop = true;
346 }
347
348 if (sscreen->b.chip_class >= CIK) {
349 /* WD_SWITCH_ON_EOP has no effect on GPUs with less than
350 * 4 shader engines. Set 1 to pass the assertion below.
351 * The other cases are hardware requirements.
352 *
353 * Polaris supports primitive restart with WD_SWITCH_ON_EOP=0
354 * for points, line strips, and tri strips.
355 */
356 if (sscreen->b.info.max_se < 4 ||
357 key->u.prim == PIPE_PRIM_POLYGON ||
358 key->u.prim == PIPE_PRIM_LINE_LOOP ||
359 key->u.prim == PIPE_PRIM_TRIANGLE_FAN ||
360 key->u.prim == PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY ||
361 (key->u.primitive_restart &&
362 (sscreen->b.family < CHIP_POLARIS10 ||
363 (key->u.prim != PIPE_PRIM_POINTS &&
364 key->u.prim != PIPE_PRIM_LINE_STRIP &&
365 key->u.prim != PIPE_PRIM_TRIANGLE_STRIP))) ||
366 key->u.count_from_stream_output)
367 wd_switch_on_eop = true;
368
369 /* Hawaii hangs if instancing is enabled and WD_SWITCH_ON_EOP is 0.
370 * We don't know that for indirect drawing, so treat it as
371 * always problematic. */
372 if (sscreen->b.family == CHIP_HAWAII &&
373 key->u.uses_instancing)
374 wd_switch_on_eop = true;
375
376 /* Performance recommendation for 4 SE Gfx7-8 parts if
377 * instances are smaller than a primgroup.
378 * Assume indirect draws always use small instances.
379 * This is needed for good VS wave utilization.
380 */
381 if (sscreen->b.chip_class <= VI &&
382 sscreen->b.info.max_se == 4 &&
383 key->u.multi_instances_smaller_than_primgroup)
384 wd_switch_on_eop = true;
385
386 /* Required on CIK and later. */
387 if (sscreen->b.info.max_se > 2 && !wd_switch_on_eop)
388 ia_switch_on_eoi = true;
389
390 /* Required by Hawaii and, for some special cases, by VI. */
391 if (ia_switch_on_eoi &&
392 (sscreen->b.family == CHIP_HAWAII ||
393 (sscreen->b.chip_class == VI &&
394 (key->u.uses_gs || max_primgroup_in_wave != 2))))
395 partial_vs_wave = true;
396
397 /* Instancing bug on Bonaire. */
398 if (sscreen->b.family == CHIP_BONAIRE && ia_switch_on_eoi &&
399 key->u.uses_instancing)
400 partial_vs_wave = true;
401
402 /* If the WD switch is false, the IA switch must be false too. */
403 assert(wd_switch_on_eop || !ia_switch_on_eop);
404 }
405
406 /* If SWITCH_ON_EOI is set, PARTIAL_ES_WAVE must be set too. */
407 if (sscreen->b.chip_class <= VI && ia_switch_on_eoi)
408 partial_es_wave = true;
409
410 return S_028AA8_SWITCH_ON_EOP(ia_switch_on_eop) |
411 S_028AA8_SWITCH_ON_EOI(ia_switch_on_eoi) |
412 S_028AA8_PARTIAL_VS_WAVE_ON(partial_vs_wave) |
413 S_028AA8_PARTIAL_ES_WAVE_ON(partial_es_wave) |
414 S_028AA8_WD_SWITCH_ON_EOP(sscreen->b.chip_class >= CIK ? wd_switch_on_eop : 0) |
415 /* The following field was moved to VGT_SHADER_STAGES_EN in GFX9. */
416 S_028AA8_MAX_PRIMGRP_IN_WAVE(sscreen->b.chip_class == VI ?
417 max_primgroup_in_wave : 0) |
418 S_030960_EN_INST_OPT_BASIC(sscreen->b.chip_class >= GFX9) |
419 S_030960_EN_INST_OPT_ADV(sscreen->b.chip_class >= GFX9);
420 }
421
422 void si_init_ia_multi_vgt_param_table(struct si_context *sctx)
423 {
424 for (int prim = 0; prim <= R600_PRIM_RECTANGLE_LIST; prim++)
425 for (int uses_instancing = 0; uses_instancing < 2; uses_instancing++)
426 for (int multi_instances = 0; multi_instances < 2; multi_instances++)
427 for (int primitive_restart = 0; primitive_restart < 2; primitive_restart++)
428 for (int count_from_so = 0; count_from_so < 2; count_from_so++)
429 for (int line_stipple = 0; line_stipple < 2; line_stipple++)
430 for (int uses_tess = 0; uses_tess < 2; uses_tess++)
431 for (int tess_uses_primid = 0; tess_uses_primid < 2; tess_uses_primid++)
432 for (int uses_gs = 0; uses_gs < 2; uses_gs++) {
433 union si_vgt_param_key key;
434
435 key.index = 0;
436 key.u.prim = prim;
437 key.u.uses_instancing = uses_instancing;
438 key.u.multi_instances_smaller_than_primgroup = multi_instances;
439 key.u.primitive_restart = primitive_restart;
440 key.u.count_from_stream_output = count_from_so;
441 key.u.line_stipple_enabled = line_stipple;
442 key.u.uses_tess = uses_tess;
443 key.u.tcs_tes_uses_prim_id = tess_uses_primid;
444 key.u.uses_gs = uses_gs;
445
446 sctx->ia_multi_vgt_param[key.index] =
447 si_get_init_multi_vgt_param(sctx->screen, &key);
448 }
449 }
450
451 static unsigned si_get_ia_multi_vgt_param(struct si_context *sctx,
452 const struct pipe_draw_info *info,
453 unsigned num_patches)
454 {
455 union si_vgt_param_key key = sctx->ia_multi_vgt_param_key;
456 unsigned primgroup_size;
457 unsigned ia_multi_vgt_param;
458
459 if (sctx->tes_shader.cso) {
460 primgroup_size = num_patches; /* must be a multiple of NUM_PATCHES */
461 } else if (sctx->gs_shader.cso) {
462 primgroup_size = 64; /* recommended with a GS */
463 } else {
464 primgroup_size = 128; /* recommended without a GS and tess */
465 }
466
467 key.u.prim = info->mode;
468 key.u.uses_instancing = info->indirect || info->instance_count > 1;
469 key.u.multi_instances_smaller_than_primgroup =
470 info->indirect ||
471 (info->instance_count > 1 &&
472 (info->count_from_stream_output ||
473 si_num_prims_for_vertices(info) < primgroup_size));
474 key.u.primitive_restart = info->primitive_restart;
475 key.u.count_from_stream_output = info->count_from_stream_output != NULL;
476
477 ia_multi_vgt_param = sctx->ia_multi_vgt_param[key.index] |
478 S_028AA8_PRIMGROUP_SIZE(primgroup_size - 1);
479
480 if (sctx->gs_shader.cso) {
481 /* GS requirement. */
482 if (sctx->b.chip_class <= VI &&
483 SI_GS_PER_ES / primgroup_size >= sctx->screen->gs_table_depth - 3)
484 ia_multi_vgt_param |= S_028AA8_PARTIAL_ES_WAVE_ON(1);
485
486 /* GS hw bug with single-primitive instances and SWITCH_ON_EOI.
487 * The hw doc says all multi-SE chips are affected, but Vulkan
488 * only applies it to Hawaii. Do what Vulkan does.
489 */
490 if (sctx->b.family == CHIP_HAWAII &&
491 G_028AA8_SWITCH_ON_EOI(ia_multi_vgt_param) &&
492 (info->indirect ||
493 (info->instance_count > 1 &&
494 (info->count_from_stream_output ||
495 si_num_prims_for_vertices(info) <= 1))))
496 sctx->b.flags |= SI_CONTEXT_VGT_FLUSH;
497 }
498
499 return ia_multi_vgt_param;
500 }
501
502 /* rast_prim is the primitive type after GS. */
503 static void si_emit_rasterizer_prim_state(struct si_context *sctx)
504 {
505 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
506 enum pipe_prim_type rast_prim = sctx->current_rast_prim;
507 struct si_state_rasterizer *rs = sctx->emitted.named.rasterizer;
508
509 /* Skip this if not rendering lines. */
510 if (rast_prim != PIPE_PRIM_LINES &&
511 rast_prim != PIPE_PRIM_LINE_LOOP &&
512 rast_prim != PIPE_PRIM_LINE_STRIP &&
513 rast_prim != PIPE_PRIM_LINES_ADJACENCY &&
514 rast_prim != PIPE_PRIM_LINE_STRIP_ADJACENCY)
515 return;
516
517 if (rast_prim == sctx->last_rast_prim &&
518 rs->pa_sc_line_stipple == sctx->last_sc_line_stipple)
519 return;
520
521 /* For lines, reset the stipple pattern at each primitive. Otherwise,
522 * reset the stipple pattern at each packet (line strips, line loops).
523 */
524 radeon_set_context_reg(cs, R_028A0C_PA_SC_LINE_STIPPLE,
525 rs->pa_sc_line_stipple |
526 S_028A0C_AUTO_RESET_CNTL(rast_prim == PIPE_PRIM_LINES ? 1 : 2));
527
528 sctx->last_rast_prim = rast_prim;
529 sctx->last_sc_line_stipple = rs->pa_sc_line_stipple;
530 }
531
532 static void si_emit_vs_state(struct si_context *sctx,
533 const struct pipe_draw_info *info)
534 {
535 sctx->current_vs_state &= C_VS_STATE_INDEXED;
536 sctx->current_vs_state |= S_VS_STATE_INDEXED(!!info->indexed);
537
538 if (sctx->current_vs_state != sctx->last_vs_state) {
539 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
540
541 radeon_set_sh_reg(cs,
542 sctx->shader_userdata.sh_base[PIPE_SHADER_VERTEX] +
543 SI_SGPR_VS_STATE_BITS * 4,
544 sctx->current_vs_state);
545
546 sctx->last_vs_state = sctx->current_vs_state;
547 }
548 }
549
550 static void si_emit_draw_registers(struct si_context *sctx,
551 const struct pipe_draw_info *info,
552 unsigned num_patches)
553 {
554 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
555 unsigned prim = si_conv_pipe_prim(info->mode);
556 unsigned gs_out_prim = si_conv_prim_to_gs_out(sctx->current_rast_prim);
557 unsigned ia_multi_vgt_param;
558
559 ia_multi_vgt_param = si_get_ia_multi_vgt_param(sctx, info, num_patches);
560
561 /* Draw state. */
562 if (ia_multi_vgt_param != sctx->last_multi_vgt_param) {
563 if (sctx->b.chip_class >= GFX9)
564 radeon_set_uconfig_reg_idx(cs, R_030960_IA_MULTI_VGT_PARAM, 4, ia_multi_vgt_param);
565 else if (sctx->b.chip_class >= CIK)
566 radeon_set_context_reg_idx(cs, R_028AA8_IA_MULTI_VGT_PARAM, 1, ia_multi_vgt_param);
567 else
568 radeon_set_context_reg(cs, R_028AA8_IA_MULTI_VGT_PARAM, ia_multi_vgt_param);
569
570 sctx->last_multi_vgt_param = ia_multi_vgt_param;
571 }
572 if (prim != sctx->last_prim) {
573 if (sctx->b.chip_class >= CIK)
574 radeon_set_uconfig_reg_idx(cs, R_030908_VGT_PRIMITIVE_TYPE, 1, prim);
575 else
576 radeon_set_config_reg(cs, R_008958_VGT_PRIMITIVE_TYPE, prim);
577
578 sctx->last_prim = prim;
579 }
580
581 if (gs_out_prim != sctx->last_gs_out_prim) {
582 radeon_set_context_reg(cs, R_028A6C_VGT_GS_OUT_PRIM_TYPE, gs_out_prim);
583 sctx->last_gs_out_prim = gs_out_prim;
584 }
585
586 /* Primitive restart. */
587 if (info->primitive_restart != sctx->last_primitive_restart_en) {
588 if (sctx->b.chip_class >= GFX9)
589 radeon_set_uconfig_reg(cs, R_03092C_VGT_MULTI_PRIM_IB_RESET_EN,
590 info->primitive_restart);
591 else
592 radeon_set_context_reg(cs, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN,
593 info->primitive_restart);
594
595 sctx->last_primitive_restart_en = info->primitive_restart;
596
597 }
598 if (info->primitive_restart &&
599 (info->restart_index != sctx->last_restart_index ||
600 sctx->last_restart_index == SI_RESTART_INDEX_UNKNOWN)) {
601 radeon_set_context_reg(cs, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
602 info->restart_index);
603 sctx->last_restart_index = info->restart_index;
604 }
605 }
606
607 static void si_emit_draw_packets(struct si_context *sctx,
608 const struct pipe_draw_info *info,
609 const struct pipe_index_buffer *ib)
610 {
611 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
612 unsigned sh_base_reg = sctx->shader_userdata.sh_base[PIPE_SHADER_VERTEX];
613 bool render_cond_bit = sctx->b.render_cond && !sctx->b.render_cond_force_off;
614 uint32_t index_max_size = 0;
615 uint64_t index_va = 0;
616
617 if (info->count_from_stream_output) {
618 struct r600_so_target *t =
619 (struct r600_so_target*)info->count_from_stream_output;
620 uint64_t va = t->buf_filled_size->gpu_address +
621 t->buf_filled_size_offset;
622
623 radeon_set_context_reg(cs, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE,
624 t->stride_in_dw);
625
626 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
627 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
628 COPY_DATA_DST_SEL(COPY_DATA_REG) |
629 COPY_DATA_WR_CONFIRM);
630 radeon_emit(cs, va); /* src address lo */
631 radeon_emit(cs, va >> 32); /* src address hi */
632 radeon_emit(cs, R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE >> 2);
633 radeon_emit(cs, 0); /* unused */
634
635 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
636 t->buf_filled_size, RADEON_USAGE_READ,
637 RADEON_PRIO_SO_FILLED_SIZE);
638 }
639
640 /* draw packet */
641 if (info->indexed) {
642 if (ib->index_size != sctx->last_index_size) {
643 unsigned index_type;
644
645 /* index type */
646 switch (ib->index_size) {
647 case 1:
648 index_type = V_028A7C_VGT_INDEX_8;
649 break;
650 case 2:
651 index_type = V_028A7C_VGT_INDEX_16 |
652 (SI_BIG_ENDIAN && sctx->b.chip_class <= CIK ?
653 V_028A7C_VGT_DMA_SWAP_16_BIT : 0);
654 break;
655 case 4:
656 index_type = V_028A7C_VGT_INDEX_32 |
657 (SI_BIG_ENDIAN && sctx->b.chip_class <= CIK ?
658 V_028A7C_VGT_DMA_SWAP_32_BIT : 0);
659 break;
660 default:
661 assert(!"unreachable");
662 return;
663 }
664
665 if (sctx->b.chip_class >= GFX9) {
666 radeon_set_uconfig_reg_idx(cs, R_03090C_VGT_INDEX_TYPE,
667 2, index_type);
668 } else {
669 radeon_emit(cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
670 radeon_emit(cs, index_type);
671 }
672
673 sctx->last_index_size = ib->index_size;
674 }
675
676 index_max_size = (ib->buffer->width0 - ib->offset) /
677 ib->index_size;
678 index_va = r600_resource(ib->buffer)->gpu_address + ib->offset;
679
680 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
681 (struct r600_resource *)ib->buffer,
682 RADEON_USAGE_READ, RADEON_PRIO_INDEX_BUFFER);
683 } else {
684 /* On CI and later, non-indexed draws overwrite VGT_INDEX_TYPE,
685 * so the state must be re-emitted before the next indexed draw.
686 */
687 if (sctx->b.chip_class >= CIK)
688 sctx->last_index_size = -1;
689 }
690
691 if (info->indirect) {
692 uint64_t indirect_va = r600_resource(info->indirect)->gpu_address;
693
694 assert(indirect_va % 8 == 0);
695
696 si_invalidate_draw_sh_constants(sctx);
697
698 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
699 radeon_emit(cs, 1);
700 radeon_emit(cs, indirect_va);
701 radeon_emit(cs, indirect_va >> 32);
702
703 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
704 (struct r600_resource *)info->indirect,
705 RADEON_USAGE_READ, RADEON_PRIO_DRAW_INDIRECT);
706
707 unsigned di_src_sel = info->indexed ? V_0287F0_DI_SRC_SEL_DMA
708 : V_0287F0_DI_SRC_SEL_AUTO_INDEX;
709
710 assert(info->indirect_offset % 4 == 0);
711
712 if (info->indexed) {
713 radeon_emit(cs, PKT3(PKT3_INDEX_BASE, 1, 0));
714 radeon_emit(cs, index_va);
715 radeon_emit(cs, index_va >> 32);
716
717 radeon_emit(cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
718 radeon_emit(cs, index_max_size);
719 }
720
721 if (!sctx->screen->has_draw_indirect_multi) {
722 radeon_emit(cs, PKT3(info->indexed ? PKT3_DRAW_INDEX_INDIRECT
723 : PKT3_DRAW_INDIRECT,
724 3, render_cond_bit));
725 radeon_emit(cs, info->indirect_offset);
726 radeon_emit(cs, (sh_base_reg + SI_SGPR_BASE_VERTEX * 4 - SI_SH_REG_OFFSET) >> 2);
727 radeon_emit(cs, (sh_base_reg + SI_SGPR_START_INSTANCE * 4 - SI_SH_REG_OFFSET) >> 2);
728 radeon_emit(cs, di_src_sel);
729 } else {
730 uint64_t count_va = 0;
731
732 if (info->indirect_params) {
733 struct r600_resource *params_buf =
734 (struct r600_resource *)info->indirect_params;
735
736 radeon_add_to_buffer_list(
737 &sctx->b, &sctx->b.gfx, params_buf,
738 RADEON_USAGE_READ, RADEON_PRIO_DRAW_INDIRECT);
739
740 count_va = params_buf->gpu_address + info->indirect_params_offset;
741 }
742
743 radeon_emit(cs, PKT3(info->indexed ? PKT3_DRAW_INDEX_INDIRECT_MULTI :
744 PKT3_DRAW_INDIRECT_MULTI,
745 8, render_cond_bit));
746 radeon_emit(cs, info->indirect_offset);
747 radeon_emit(cs, (sh_base_reg + SI_SGPR_BASE_VERTEX * 4 - SI_SH_REG_OFFSET) >> 2);
748 radeon_emit(cs, (sh_base_reg + SI_SGPR_START_INSTANCE * 4 - SI_SH_REG_OFFSET) >> 2);
749 radeon_emit(cs, ((sh_base_reg + SI_SGPR_DRAWID * 4 - SI_SH_REG_OFFSET) >> 2) |
750 S_2C3_DRAW_INDEX_ENABLE(1) |
751 S_2C3_COUNT_INDIRECT_ENABLE(!!info->indirect_params));
752 radeon_emit(cs, info->indirect_count);
753 radeon_emit(cs, count_va);
754 radeon_emit(cs, count_va >> 32);
755 radeon_emit(cs, info->indirect_stride);
756 radeon_emit(cs, di_src_sel);
757 }
758 } else {
759 int base_vertex;
760
761 radeon_emit(cs, PKT3(PKT3_NUM_INSTANCES, 0, 0));
762 radeon_emit(cs, info->instance_count);
763
764 /* Base vertex and start instance. */
765 base_vertex = info->indexed ? info->index_bias : info->start;
766
767 if (base_vertex != sctx->last_base_vertex ||
768 sctx->last_base_vertex == SI_BASE_VERTEX_UNKNOWN ||
769 info->start_instance != sctx->last_start_instance ||
770 info->drawid != sctx->last_drawid ||
771 sh_base_reg != sctx->last_sh_base_reg) {
772 radeon_set_sh_reg_seq(cs, sh_base_reg + SI_SGPR_BASE_VERTEX * 4, 3);
773 radeon_emit(cs, base_vertex);
774 radeon_emit(cs, info->start_instance);
775 radeon_emit(cs, info->drawid);
776
777 sctx->last_base_vertex = base_vertex;
778 sctx->last_start_instance = info->start_instance;
779 sctx->last_drawid = info->drawid;
780 sctx->last_sh_base_reg = sh_base_reg;
781 }
782
783 if (info->indexed) {
784 index_va += info->start * ib->index_size;
785
786 radeon_emit(cs, PKT3(PKT3_DRAW_INDEX_2, 4, render_cond_bit));
787 radeon_emit(cs, index_max_size);
788 radeon_emit(cs, index_va);
789 radeon_emit(cs, index_va >> 32);
790 radeon_emit(cs, info->count);
791 radeon_emit(cs, V_0287F0_DI_SRC_SEL_DMA);
792 } else {
793 radeon_emit(cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, render_cond_bit));
794 radeon_emit(cs, info->count);
795 radeon_emit(cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
796 S_0287F0_USE_OPAQUE(!!info->count_from_stream_output));
797 }
798 }
799 }
800
801 static void si_emit_surface_sync(struct r600_common_context *rctx,
802 unsigned cp_coher_cntl)
803 {
804 struct radeon_winsys_cs *cs = rctx->gfx.cs;
805
806 if (rctx->chip_class >= GFX9) {
807 /* Flush caches and wait for the caches to assert idle. */
808 radeon_emit(cs, PKT3(PKT3_ACQUIRE_MEM, 5, 0));
809 radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */
810 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
811 radeon_emit(cs, 0xffffff); /* CP_COHER_SIZE_HI */
812 radeon_emit(cs, 0); /* CP_COHER_BASE */
813 radeon_emit(cs, 0); /* CP_COHER_BASE_HI */
814 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
815 } else {
816 /* ACQUIRE_MEM is only required on a compute ring. */
817 radeon_emit(cs, PKT3(PKT3_SURFACE_SYNC, 3, 0));
818 radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */
819 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
820 radeon_emit(cs, 0); /* CP_COHER_BASE */
821 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
822 }
823 }
824
825 void si_emit_cache_flush(struct si_context *sctx)
826 {
827 struct r600_common_context *rctx = &sctx->b;
828 struct radeon_winsys_cs *cs = rctx->gfx.cs;
829 uint32_t cp_coher_cntl = 0;
830 uint32_t flush_cb_db = rctx->flags & (SI_CONTEXT_FLUSH_AND_INV_CB |
831 SI_CONTEXT_FLUSH_AND_INV_DB);
832
833 if (rctx->flags & (SI_CONTEXT_FLUSH_AND_INV_CB |
834 SI_CONTEXT_FLUSH_AND_INV_DB))
835 sctx->b.num_fb_cache_flushes++;
836
837 /* SI has a bug that it always flushes ICACHE and KCACHE if either
838 * bit is set. An alternative way is to write SQC_CACHES, but that
839 * doesn't seem to work reliably. Since the bug doesn't affect
840 * correctness (it only does more work than necessary) and
841 * the performance impact is likely negligible, there is no plan
842 * to add a workaround for it.
843 */
844
845 if (rctx->flags & SI_CONTEXT_INV_ICACHE)
846 cp_coher_cntl |= S_0085F0_SH_ICACHE_ACTION_ENA(1);
847 if (rctx->flags & SI_CONTEXT_INV_SMEM_L1)
848 cp_coher_cntl |= S_0085F0_SH_KCACHE_ACTION_ENA(1);
849
850 if (rctx->chip_class <= VI) {
851 if (rctx->flags & SI_CONTEXT_FLUSH_AND_INV_CB) {
852 cp_coher_cntl |= S_0085F0_CB_ACTION_ENA(1) |
853 S_0085F0_CB0_DEST_BASE_ENA(1) |
854 S_0085F0_CB1_DEST_BASE_ENA(1) |
855 S_0085F0_CB2_DEST_BASE_ENA(1) |
856 S_0085F0_CB3_DEST_BASE_ENA(1) |
857 S_0085F0_CB4_DEST_BASE_ENA(1) |
858 S_0085F0_CB5_DEST_BASE_ENA(1) |
859 S_0085F0_CB6_DEST_BASE_ENA(1) |
860 S_0085F0_CB7_DEST_BASE_ENA(1);
861
862 /* Necessary for DCC */
863 if (rctx->chip_class == VI)
864 r600_gfx_write_event_eop(rctx, V_028A90_FLUSH_AND_INV_CB_DATA_TS,
865 0, 0, NULL, 0, 0, 0);
866 }
867 if (rctx->flags & SI_CONTEXT_FLUSH_AND_INV_DB)
868 cp_coher_cntl |= S_0085F0_DB_ACTION_ENA(1) |
869 S_0085F0_DB_DEST_BASE_ENA(1);
870 }
871
872 if (rctx->flags & SI_CONTEXT_FLUSH_AND_INV_CB) {
873 /* Flush CMASK/FMASK/DCC. SURFACE_SYNC will wait for idle. */
874 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
875 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_META) | EVENT_INDEX(0));
876 }
877 if (rctx->flags & SI_CONTEXT_FLUSH_AND_INV_DB) {
878 /* Flush HTILE. SURFACE_SYNC will wait for idle. */
879 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
880 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_DB_META) | EVENT_INDEX(0));
881 }
882
883 /* Wait for shader engines to go idle.
884 * VS and PS waits are unnecessary if SURFACE_SYNC is going to wait
885 * for everything including CB/DB cache flushes.
886 */
887 if (!flush_cb_db) {
888 if (rctx->flags & SI_CONTEXT_PS_PARTIAL_FLUSH) {
889 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
890 radeon_emit(cs, EVENT_TYPE(V_028A90_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
891 /* Only count explicit shader flushes, not implicit ones
892 * done by SURFACE_SYNC.
893 */
894 rctx->num_vs_flushes++;
895 rctx->num_ps_flushes++;
896 } else if (rctx->flags & SI_CONTEXT_VS_PARTIAL_FLUSH) {
897 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
898 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
899 rctx->num_vs_flushes++;
900 }
901 }
902
903 if (rctx->flags & SI_CONTEXT_CS_PARTIAL_FLUSH &&
904 sctx->compute_is_busy) {
905 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
906 radeon_emit(cs, EVENT_TYPE(V_028A90_CS_PARTIAL_FLUSH | EVENT_INDEX(4)));
907 rctx->num_cs_flushes++;
908 sctx->compute_is_busy = false;
909 }
910
911 /* VGT state synchronization. */
912 if (rctx->flags & SI_CONTEXT_VGT_FLUSH) {
913 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
914 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
915 }
916 if (rctx->flags & SI_CONTEXT_VGT_STREAMOUT_SYNC) {
917 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
918 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_STREAMOUT_SYNC) | EVENT_INDEX(0));
919 }
920
921 /* GFX9: Wait for idle if we're flushing CB or DB. ACQUIRE_MEM doesn't
922 * wait for idle on GFX9. We have to use a TS event.
923 */
924 if (sctx->b.chip_class >= GFX9 && flush_cb_db) {
925 struct r600_resource *rbuf = NULL;
926 uint64_t va;
927 unsigned offset = 0, tc_flags, cb_db_event;
928
929 /* Set the CB/DB flush event. */
930 switch (flush_cb_db) {
931 case SI_CONTEXT_FLUSH_AND_INV_CB:
932 cb_db_event = V_028A90_FLUSH_AND_INV_CB_DATA_TS;
933 break;
934 case SI_CONTEXT_FLUSH_AND_INV_DB:
935 cb_db_event = V_028A90_FLUSH_AND_INV_DB_DATA_TS;
936 break;
937 default:
938 /* both CB & DB */
939 cb_db_event = V_028A90_CACHE_FLUSH_AND_INV_TS_EVENT;
940 }
941
942 /* TC | TC_WB = invalidate L2 data
943 * TC_MD | TC_WB = invalidate L2 metadata
944 * TC | TC_WB | TC_MD = invalidate L2 data & metadata
945 *
946 * The metadata cache must always be invalidated for coherency
947 * between CB/DB and shaders. (metadata = HTILE, CMASK, DCC)
948 *
949 * TC must be invalidated on GFX9 only if the CB/DB surface is
950 * not pipe-aligned. If the surface is RB-aligned, it might not
951 * strictly be pipe-aligned since RB alignment takes precendence.
952 */
953 tc_flags = EVENT_TC_WB_ACTION_ENA |
954 EVENT_TC_MD_ACTION_ENA;
955
956 /* Ideally flush TC together with CB/DB. */
957 if (rctx->flags & SI_CONTEXT_INV_GLOBAL_L2) {
958 tc_flags |= EVENT_TC_ACTION_ENA |
959 EVENT_TCL1_ACTION_ENA;
960
961 /* Clear the flags. */
962 rctx->flags &= ~(SI_CONTEXT_INV_GLOBAL_L2 |
963 SI_CONTEXT_WRITEBACK_GLOBAL_L2 |
964 SI_CONTEXT_INV_VMEM_L1);
965 }
966
967 /* Allocate memory for the fence. */
968 u_suballocator_alloc(rctx->allocator_zeroed_memory, 4, 4,
969 &offset, (struct pipe_resource**)&rbuf);
970 va = rbuf->gpu_address + offset;
971
972 r600_gfx_write_event_eop(rctx, cb_db_event, tc_flags, 1,
973 rbuf, va, 0, 1);
974 r600_gfx_wait_fence(rctx, va, 1, 0xffffffff);
975 }
976
977 /* Make sure ME is idle (it executes most packets) before continuing.
978 * This prevents read-after-write hazards between PFP and ME.
979 */
980 if (cp_coher_cntl ||
981 (rctx->flags & (SI_CONTEXT_CS_PARTIAL_FLUSH |
982 SI_CONTEXT_INV_VMEM_L1 |
983 SI_CONTEXT_INV_GLOBAL_L2 |
984 SI_CONTEXT_WRITEBACK_GLOBAL_L2))) {
985 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
986 radeon_emit(cs, 0);
987 }
988
989 /* SI-CI-VI only:
990 * When one of the CP_COHER_CNTL.DEST_BASE flags is set, SURFACE_SYNC
991 * waits for idle, so it should be last. SURFACE_SYNC is done in PFP.
992 *
993 * cp_coher_cntl should contain all necessary flags except TC flags
994 * at this point.
995 *
996 * SI-CIK don't support L2 write-back.
997 */
998 if (rctx->flags & SI_CONTEXT_INV_GLOBAL_L2 ||
999 (rctx->chip_class <= CIK &&
1000 (rctx->flags & SI_CONTEXT_WRITEBACK_GLOBAL_L2))) {
1001 /* Invalidate L1 & L2. (L1 is always invalidated on SI)
1002 * WB must be set on VI+ when TC_ACTION is set.
1003 */
1004 si_emit_surface_sync(rctx, cp_coher_cntl |
1005 S_0085F0_TC_ACTION_ENA(1) |
1006 S_0085F0_TCL1_ACTION_ENA(1) |
1007 S_0301F0_TC_WB_ACTION_ENA(rctx->chip_class >= VI));
1008 cp_coher_cntl = 0;
1009 sctx->b.num_L2_invalidates++;
1010 } else {
1011 /* L1 invalidation and L2 writeback must be done separately,
1012 * because both operations can't be done together.
1013 */
1014 if (rctx->flags & SI_CONTEXT_WRITEBACK_GLOBAL_L2) {
1015 /* WB = write-back
1016 * NC = apply to non-coherent MTYPEs
1017 * (i.e. MTYPE <= 1, which is what we use everywhere)
1018 *
1019 * WB doesn't work without NC.
1020 */
1021 si_emit_surface_sync(rctx, cp_coher_cntl |
1022 S_0301F0_TC_WB_ACTION_ENA(1) |
1023 S_0301F0_TC_NC_ACTION_ENA(1));
1024 cp_coher_cntl = 0;
1025 sctx->b.num_L2_writebacks++;
1026 }
1027 if (rctx->flags & SI_CONTEXT_INV_VMEM_L1) {
1028 /* Invalidate per-CU VMEM L1. */
1029 si_emit_surface_sync(rctx, cp_coher_cntl |
1030 S_0085F0_TCL1_ACTION_ENA(1));
1031 cp_coher_cntl = 0;
1032 }
1033 }
1034
1035 /* If TC flushes haven't cleared this... */
1036 if (cp_coher_cntl)
1037 si_emit_surface_sync(rctx, cp_coher_cntl);
1038
1039 if (rctx->flags & R600_CONTEXT_START_PIPELINE_STATS) {
1040 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1041 radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_START) |
1042 EVENT_INDEX(0));
1043 } else if (rctx->flags & R600_CONTEXT_STOP_PIPELINE_STATS) {
1044 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1045 radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_STOP) |
1046 EVENT_INDEX(0));
1047 }
1048
1049 rctx->flags = 0;
1050 }
1051
1052 static void si_get_draw_start_count(struct si_context *sctx,
1053 const struct pipe_draw_info *info,
1054 unsigned *start, unsigned *count)
1055 {
1056 if (info->indirect) {
1057 unsigned indirect_count;
1058 struct pipe_transfer *transfer;
1059 unsigned begin, end;
1060 unsigned map_size;
1061 unsigned *data;
1062
1063 if (info->indirect_params) {
1064 data = pipe_buffer_map_range(&sctx->b.b,
1065 info->indirect_params,
1066 info->indirect_params_offset,
1067 sizeof(unsigned),
1068 PIPE_TRANSFER_READ, &transfer);
1069
1070 indirect_count = *data;
1071
1072 pipe_buffer_unmap(&sctx->b.b, transfer);
1073 } else {
1074 indirect_count = info->indirect_count;
1075 }
1076
1077 if (!indirect_count) {
1078 *start = *count = 0;
1079 return;
1080 }
1081
1082 map_size = (indirect_count - 1) * info->indirect_stride + 3 * sizeof(unsigned);
1083 data = pipe_buffer_map_range(&sctx->b.b, info->indirect,
1084 info->indirect_offset, map_size,
1085 PIPE_TRANSFER_READ, &transfer);
1086
1087 begin = UINT_MAX;
1088 end = 0;
1089
1090 for (unsigned i = 0; i < indirect_count; ++i) {
1091 unsigned count = data[0];
1092 unsigned start = data[2];
1093
1094 if (count > 0) {
1095 begin = MIN2(begin, start);
1096 end = MAX2(end, start + count);
1097 }
1098
1099 data += info->indirect_stride / sizeof(unsigned);
1100 }
1101
1102 pipe_buffer_unmap(&sctx->b.b, transfer);
1103
1104 if (begin < end) {
1105 *start = begin;
1106 *count = end - begin;
1107 } else {
1108 *start = *count = 0;
1109 }
1110 } else {
1111 *start = info->start;
1112 *count = info->count;
1113 }
1114 }
1115
1116 void si_ce_pre_draw_synchronization(struct si_context *sctx)
1117 {
1118 if (sctx->ce_need_synchronization) {
1119 radeon_emit(sctx->ce_ib, PKT3(PKT3_INCREMENT_CE_COUNTER, 0, 0));
1120 radeon_emit(sctx->ce_ib, 1);
1121
1122 radeon_emit(sctx->b.gfx.cs, PKT3(PKT3_WAIT_ON_CE_COUNTER, 0, 0));
1123 radeon_emit(sctx->b.gfx.cs, 1);
1124 }
1125 }
1126
1127 void si_ce_post_draw_synchronization(struct si_context *sctx)
1128 {
1129 if (sctx->ce_need_synchronization) {
1130 radeon_emit(sctx->b.gfx.cs, PKT3(PKT3_INCREMENT_DE_COUNTER, 0, 0));
1131 radeon_emit(sctx->b.gfx.cs, 0);
1132
1133 sctx->ce_need_synchronization = false;
1134 }
1135 }
1136
1137 void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info)
1138 {
1139 struct si_context *sctx = (struct si_context *)ctx;
1140 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
1141 const struct pipe_index_buffer *ib = &sctx->index_buffer;
1142 struct pipe_index_buffer ib_tmp; /* for index buffer uploads only */
1143 unsigned mask, dirty_tex_counter;
1144 enum pipe_prim_type rast_prim;
1145 unsigned num_patches = 0;
1146
1147 if (likely(!info->indirect)) {
1148 /* SI-CI treat instance_count==0 as instance_count==1. There is
1149 * no workaround for indirect draws, but we can at least skip
1150 * direct draws.
1151 */
1152 if (unlikely(!info->instance_count))
1153 return;
1154
1155 /* Handle count == 0. */
1156 if (unlikely(!info->count &&
1157 (info->indexed || !info->count_from_stream_output)))
1158 return;
1159 }
1160
1161 if (unlikely(!sctx->vs_shader.cso)) {
1162 assert(0);
1163 return;
1164 }
1165 if (unlikely(!sctx->ps_shader.cso && (!rs || !rs->rasterizer_discard))) {
1166 assert(0);
1167 return;
1168 }
1169 if (unlikely(!!sctx->tes_shader.cso != (info->mode == PIPE_PRIM_PATCHES))) {
1170 assert(0);
1171 return;
1172 }
1173
1174 /* Recompute and re-emit the texture resource states if needed. */
1175 dirty_tex_counter = p_atomic_read(&sctx->b.screen->dirty_tex_counter);
1176 if (unlikely(dirty_tex_counter != sctx->b.last_dirty_tex_counter)) {
1177 sctx->b.last_dirty_tex_counter = dirty_tex_counter;
1178 sctx->framebuffer.dirty_cbufs |=
1179 ((1 << sctx->framebuffer.state.nr_cbufs) - 1);
1180 sctx->framebuffer.dirty_zsbuf = true;
1181 sctx->framebuffer.do_update_surf_dirtiness = true;
1182 si_mark_atom_dirty(sctx, &sctx->framebuffer.atom);
1183 si_update_all_texture_descriptors(sctx);
1184 }
1185
1186 si_decompress_graphics_textures(sctx);
1187
1188 /* Set the rasterization primitive type.
1189 *
1190 * This must be done after si_decompress_textures, which can call
1191 * draw_vbo recursively, and before si_update_shaders, which uses
1192 * current_rast_prim for this draw_vbo call. */
1193 if (sctx->gs_shader.cso)
1194 rast_prim = sctx->gs_shader.cso->gs_output_prim;
1195 else if (sctx->tes_shader.cso)
1196 rast_prim = sctx->tes_shader.cso->info.properties[TGSI_PROPERTY_TES_PRIM_MODE];
1197 else
1198 rast_prim = info->mode;
1199
1200 if (rast_prim != sctx->current_rast_prim) {
1201 sctx->current_rast_prim = rast_prim;
1202 sctx->do_update_shaders = true;
1203 }
1204
1205 if (sctx->gs_shader.cso) {
1206 /* Determine whether the GS triangle strip adjacency fix should
1207 * be applied. Rotate every other triangle if
1208 * - triangle strips with adjacency are fed to the GS and
1209 * - primitive restart is disabled (the rotation doesn't help
1210 * when the restart occurs after an odd number of triangles).
1211 */
1212 bool gs_tri_strip_adj_fix =
1213 !sctx->tes_shader.cso &&
1214 info->mode == PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY &&
1215 !info->primitive_restart;
1216
1217 if (gs_tri_strip_adj_fix != sctx->gs_tri_strip_adj_fix) {
1218 sctx->gs_tri_strip_adj_fix = gs_tri_strip_adj_fix;
1219 sctx->do_update_shaders = true;
1220 }
1221 }
1222
1223 if (sctx->do_update_shaders && !si_update_shaders(sctx))
1224 return;
1225
1226 if (!si_upload_graphics_shader_descriptors(sctx))
1227 return;
1228
1229 ib_tmp.buffer = NULL;
1230
1231 if (info->indexed) {
1232 /* Translate or upload, if needed. */
1233 /* 8-bit indices are supported on VI. */
1234 if (sctx->b.chip_class <= CIK && ib->index_size == 1) {
1235 unsigned start, count, start_offset, size;
1236 void *ptr;
1237
1238 si_get_draw_start_count(sctx, info, &start, &count);
1239 start_offset = start * 2;
1240 size = count * 2;
1241
1242 u_upload_alloc(ctx->stream_uploader, start_offset,
1243 size,
1244 si_optimal_tcc_alignment(sctx, size),
1245 &ib_tmp.offset, &ib_tmp.buffer, &ptr);
1246 if (!ib_tmp.buffer)
1247 return;
1248
1249 util_shorten_ubyte_elts_to_userptr(&sctx->b.b, ib, 0, 0,
1250 ib->offset + start,
1251 count, ptr);
1252
1253 /* info->start will be added by the drawing code */
1254 ib_tmp.offset -= start_offset;
1255 ib_tmp.index_size = 2;
1256 ib = &ib_tmp;
1257 } else if (ib->user_buffer && !ib->buffer) {
1258 unsigned start_offset;
1259
1260 assert(!info->indirect);
1261 start_offset = info->start * ib->index_size;
1262
1263 u_upload_data(ctx->stream_uploader, start_offset,
1264 info->count * ib->index_size,
1265 sctx->screen->b.info.tcc_cache_line_size,
1266 (char*)ib->user_buffer + start_offset,
1267 &ib_tmp.offset, &ib_tmp.buffer);
1268 if (!ib_tmp.buffer)
1269 return;
1270
1271 /* info->start will be added by the drawing code */
1272 ib_tmp.offset -= start_offset;
1273 ib_tmp.index_size = ib->index_size;
1274 ib = &ib_tmp;
1275 } else if (sctx->b.chip_class <= CIK &&
1276 r600_resource(ib->buffer)->TC_L2_dirty) {
1277 /* VI reads index buffers through TC L2, so it doesn't
1278 * need this. */
1279 sctx->b.flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
1280 r600_resource(ib->buffer)->TC_L2_dirty = false;
1281 }
1282 }
1283
1284 if (info->indirect) {
1285 /* Add the buffer size for memory checking in need_cs_space. */
1286 r600_context_add_resource_size(ctx, info->indirect);
1287
1288 if (r600_resource(info->indirect)->TC_L2_dirty) {
1289 sctx->b.flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
1290 r600_resource(info->indirect)->TC_L2_dirty = false;
1291 }
1292
1293 if (info->indirect_params &&
1294 r600_resource(info->indirect_params)->TC_L2_dirty) {
1295 sctx->b.flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
1296 r600_resource(info->indirect_params)->TC_L2_dirty = false;
1297 }
1298 }
1299
1300 si_need_cs_space(sctx);
1301
1302 /* Since we've called r600_context_add_resource_size for vertex buffers,
1303 * this must be called after si_need_cs_space, because we must let
1304 * need_cs_space flush before we add buffers to the buffer list.
1305 */
1306 if (!si_upload_vertex_buffer_descriptors(sctx))
1307 return;
1308
1309 /* GFX9 scissor bug workaround. There is also a more efficient but
1310 * more involved alternative workaround. */
1311 if (sctx->b.chip_class == GFX9 &&
1312 si_is_atom_dirty(sctx, &sctx->b.scissors.atom))
1313 sctx->b.flags |= SI_CONTEXT_PS_PARTIAL_FLUSH;
1314
1315 /* Flush caches before the first state atom, which does L2 prefetches. */
1316 if (sctx->b.flags)
1317 si_emit_cache_flush(sctx);
1318
1319 /* Emit state atoms. */
1320 mask = sctx->dirty_atoms;
1321 while (mask) {
1322 struct r600_atom *atom = sctx->atoms.array[u_bit_scan(&mask)];
1323
1324 atom->emit(&sctx->b, atom);
1325 }
1326 sctx->dirty_atoms = 0;
1327
1328 /* Emit states. */
1329 mask = sctx->dirty_states;
1330 while (mask) {
1331 unsigned i = u_bit_scan(&mask);
1332 struct si_pm4_state *state = sctx->queued.array[i];
1333
1334 if (!state || sctx->emitted.array[i] == state)
1335 continue;
1336
1337 si_pm4_emit(sctx, state);
1338 sctx->emitted.array[i] = state;
1339 }
1340 sctx->dirty_states = 0;
1341
1342 si_emit_rasterizer_prim_state(sctx);
1343 if (sctx->tes_shader.cso)
1344 si_emit_derived_tess_state(sctx, info, &num_patches);
1345 si_emit_vs_state(sctx, info);
1346 si_emit_draw_registers(sctx, info, num_patches);
1347
1348 si_ce_pre_draw_synchronization(sctx);
1349 si_emit_draw_packets(sctx, info, ib);
1350 si_ce_post_draw_synchronization(sctx);
1351
1352 if (sctx->trace_buf)
1353 si_trace_emit(sctx);
1354
1355 /* Workaround for a VGT hang when streamout is enabled.
1356 * It must be done after drawing. */
1357 if ((sctx->b.family == CHIP_HAWAII ||
1358 sctx->b.family == CHIP_TONGA ||
1359 sctx->b.family == CHIP_FIJI) &&
1360 r600_get_strmout_en(&sctx->b)) {
1361 sctx->b.flags |= SI_CONTEXT_VGT_STREAMOUT_SYNC;
1362 }
1363
1364 if (sctx->framebuffer.do_update_surf_dirtiness) {
1365 /* Set the depth buffer as dirty. */
1366 if (sctx->framebuffer.state.zsbuf) {
1367 struct pipe_surface *surf = sctx->framebuffer.state.zsbuf;
1368 struct r600_texture *rtex = (struct r600_texture *)surf->texture;
1369
1370 if (!rtex->tc_compatible_htile)
1371 rtex->dirty_level_mask |= 1 << surf->u.tex.level;
1372
1373 if (rtex->surface.flags & RADEON_SURF_SBUFFER)
1374 rtex->stencil_dirty_level_mask |= 1 << surf->u.tex.level;
1375 }
1376 if (sctx->framebuffer.compressed_cb_mask) {
1377 struct pipe_surface *surf;
1378 struct r600_texture *rtex;
1379 unsigned mask = sctx->framebuffer.compressed_cb_mask;
1380
1381 do {
1382 unsigned i = u_bit_scan(&mask);
1383 surf = sctx->framebuffer.state.cbufs[i];
1384 rtex = (struct r600_texture*)surf->texture;
1385
1386 if (rtex->fmask.size)
1387 rtex->dirty_level_mask |= 1 << surf->u.tex.level;
1388 if (rtex->dcc_gather_statistics)
1389 rtex->separate_dcc_dirty = true;
1390 } while (mask);
1391 }
1392 sctx->framebuffer.do_update_surf_dirtiness = false;
1393 }
1394
1395 pipe_resource_reference(&ib_tmp.buffer, NULL);
1396 sctx->b.num_draw_calls++;
1397 if (G_0286E8_WAVESIZE(sctx->spi_tmpring_size))
1398 sctx->b.num_spill_draw_calls++;
1399 }
1400
1401 void si_trace_emit(struct si_context *sctx)
1402 {
1403 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
1404
1405 sctx->trace_id++;
1406 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, sctx->trace_buf,
1407 RADEON_USAGE_READWRITE, RADEON_PRIO_TRACE);
1408 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
1409 radeon_emit(cs, S_370_DST_SEL(V_370_MEMORY_SYNC) |
1410 S_370_WR_CONFIRM(1) |
1411 S_370_ENGINE_SEL(V_370_ME));
1412 radeon_emit(cs, sctx->trace_buf->gpu_address);
1413 radeon_emit(cs, sctx->trace_buf->gpu_address >> 32);
1414 radeon_emit(cs, sctx->trace_id);
1415 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1416 radeon_emit(cs, AC_ENCODE_TRACE_POINT(sctx->trace_id));
1417 }