2 * Copyright 2012 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 * Christian König <christian.koenig@amd.com>
27 #include "util/u_memory.h"
28 #include "util/u_framebuffer.h"
29 #include "util/u_blitter.h"
30 #include "tgsi/tgsi_parse.h"
31 #include "radeonsi_pipe.h"
32 #include "radeonsi_shader.h"
40 static void si_pipe_shader_vs(struct pipe_context
*ctx
, struct si_pipe_shader
*shader
)
42 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
43 struct si_pm4_state
*pm4
;
44 unsigned num_sgprs
, num_user_sgprs
;
48 if (si_pipe_shader_create(ctx
, shader
))
51 si_pm4_delete_state(rctx
, vs
, shader
->pm4
);
52 pm4
= shader
->pm4
= CALLOC_STRUCT(si_pm4_state
);
54 si_pm4_inval_shader_cache(pm4
);
56 /* Certain attributes (position, psize, etc.) don't count as params.
57 * VS is required to export at least one param and r600_shader_from_tgsi()
58 * takes care of adding a dummy export.
60 for (nparams
= 0, i
= 0 ; i
< shader
->shader
.noutput
; i
++) {
61 if (shader
->shader
.output
[i
].name
!= TGSI_SEMANTIC_POSITION
)
67 si_pm4_set_reg(pm4
, R_0286C4_SPI_VS_OUT_CONFIG
,
68 S_0286C4_VS_EXPORT_COUNT(nparams
- 1));
70 si_pm4_set_reg(pm4
, R_02870C_SPI_SHADER_POS_FORMAT
,
71 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP
) |
72 S_02870C_POS1_EXPORT_FORMAT(V_02870C_SPI_SHADER_NONE
) |
73 S_02870C_POS2_EXPORT_FORMAT(V_02870C_SPI_SHADER_NONE
) |
74 S_02870C_POS3_EXPORT_FORMAT(V_02870C_SPI_SHADER_NONE
));
76 va
= r600_resource_va(ctx
->screen
, (void *)shader
->bo
);
77 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
);
78 si_pm4_set_reg(pm4
, R_00B120_SPI_SHADER_PGM_LO_VS
, va
>> 8);
79 si_pm4_set_reg(pm4
, R_00B124_SPI_SHADER_PGM_HI_VS
, va
>> 40);
82 num_sgprs
= shader
->num_sgprs
;
83 if (num_user_sgprs
> num_sgprs
)
84 num_sgprs
= num_user_sgprs
;
85 /* Last 2 reserved SGPRs are used for VCC */
87 assert(num_sgprs
<= 104);
89 si_pm4_set_reg(pm4
, R_00B128_SPI_SHADER_PGM_RSRC1_VS
,
90 S_00B128_VGPRS((shader
->num_vgprs
- 1) / 4) |
91 S_00B128_SGPRS((num_sgprs
- 1) / 8));
92 si_pm4_set_reg(pm4
, R_00B12C_SPI_SHADER_PGM_RSRC2_VS
,
93 S_00B12C_USER_SGPR(num_user_sgprs
));
95 si_pm4_bind_state(rctx
, vs
, shader
->pm4
);
98 static void si_pipe_shader_ps(struct pipe_context
*ctx
, struct si_pipe_shader
*shader
)
100 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
101 struct si_pm4_state
*pm4
;
102 unsigned i
, exports_ps
, num_cout
, spi_ps_in_control
, db_shader_control
;
103 unsigned num_sgprs
, num_user_sgprs
;
105 boolean have_linear
= FALSE
, have_centroid
= FALSE
, have_perspective
= FALSE
;
106 unsigned spi_baryc_cntl
;
109 if (si_pipe_shader_create(ctx
, shader
))
112 si_pm4_delete_state(rctx
, ps
, shader
->pm4
);
113 pm4
= shader
->pm4
= CALLOC_STRUCT(si_pm4_state
);
115 si_pm4_inval_shader_cache(pm4
);
117 db_shader_control
= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z
);
118 for (i
= 0; i
< shader
->shader
.ninput
; i
++) {
120 /* XXX: Flat shading hangs the GPU */
121 if (shader
->shader
.input
[i
].interpolate
== TGSI_INTERPOLATE_CONSTANT
||
122 (shader
->shader
.input
[i
].interpolate
== TGSI_INTERPOLATE_COLOR
&&
123 rctx
->queued
.named
.rasterizer
->flatshade
))
125 if (shader
->shader
.input
[i
].interpolate
== TGSI_INTERPOLATE_LINEAR
)
127 if (shader
->shader
.input
[i
].interpolate
== TGSI_INTERPOLATE_PERSPECTIVE
)
128 have_perspective
= TRUE
;
129 if (shader
->shader
.input
[i
].centroid
)
130 have_centroid
= TRUE
;
133 for (i
= 0; i
< shader
->shader
.noutput
; i
++) {
134 if (shader
->shader
.output
[i
].name
== TGSI_SEMANTIC_POSITION
)
135 db_shader_control
|= S_02880C_Z_EXPORT_ENABLE(1);
136 if (shader
->shader
.output
[i
].name
== TGSI_SEMANTIC_STENCIL
)
137 db_shader_control
|= 0; // XXX OP_VAL or TEST_VAL?
139 if (shader
->shader
.uses_kill
)
140 db_shader_control
|= S_02880C_KILL_ENABLE(1);
144 for (i
= 0; i
< shader
->shader
.noutput
; i
++) {
145 if (shader
->shader
.output
[i
].name
== TGSI_SEMANTIC_POSITION
||
146 shader
->shader
.output
[i
].name
== TGSI_SEMANTIC_STENCIL
)
148 else if (shader
->shader
.output
[i
].name
== TGSI_SEMANTIC_COLOR
) {
149 if (shader
->shader
.fs_write_all
)
150 num_cout
= shader
->shader
.nr_cbufs
;
156 /* always at least export 1 component per pixel */
160 spi_ps_in_control
= S_0286D8_NUM_INTERP(ninterp
);
163 if (have_perspective
)
164 spi_baryc_cntl
|= have_centroid
?
165 S_0286E0_PERSP_CENTROID_CNTL(1) : S_0286E0_PERSP_CENTER_CNTL(1);
167 spi_baryc_cntl
|= have_centroid
?
168 S_0286E0_LINEAR_CENTROID_CNTL(1) : S_0286E0_LINEAR_CENTER_CNTL(1);
170 si_pm4_set_reg(pm4
, R_0286E0_SPI_BARYC_CNTL
, spi_baryc_cntl
);
171 si_pm4_set_reg(pm4
, R_0286CC_SPI_PS_INPUT_ENA
, shader
->spi_ps_input_ena
);
172 si_pm4_set_reg(pm4
, R_0286D0_SPI_PS_INPUT_ADDR
, shader
->spi_ps_input_ena
);
173 si_pm4_set_reg(pm4
, R_0286D8_SPI_PS_IN_CONTROL
, spi_ps_in_control
);
175 /* XXX: Depends on Z buffer format? */
176 si_pm4_set_reg(pm4
, R_028710_SPI_SHADER_Z_FORMAT
, 0);
178 /* XXX: Depends on color buffer format? */
179 si_pm4_set_reg(pm4
, R_028714_SPI_SHADER_COL_FORMAT
,
180 S_028714_COL0_EXPORT_FORMAT(V_028714_SPI_SHADER_32_ABGR
));
182 va
= r600_resource_va(ctx
->screen
, (void *)shader
->bo
);
183 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
);
184 si_pm4_set_reg(pm4
, R_00B020_SPI_SHADER_PGM_LO_PS
, va
>> 8);
185 si_pm4_set_reg(pm4
, R_00B024_SPI_SHADER_PGM_HI_PS
, va
>> 40);
188 num_sgprs
= shader
->num_sgprs
;
189 if (num_user_sgprs
> num_sgprs
)
190 num_sgprs
= num_user_sgprs
;
191 /* Last 2 reserved SGPRs are used for VCC */
193 assert(num_sgprs
<= 104);
195 si_pm4_set_reg(pm4
, R_00B028_SPI_SHADER_PGM_RSRC1_PS
,
196 S_00B028_VGPRS((shader
->num_vgprs
- 1) / 4) |
197 S_00B028_SGPRS((num_sgprs
- 1) / 8));
198 si_pm4_set_reg(pm4
, R_00B02C_SPI_SHADER_PGM_RSRC2_PS
,
199 S_00B02C_USER_SGPR(num_user_sgprs
));
201 si_pm4_set_reg(pm4
, R_02880C_DB_SHADER_CONTROL
, db_shader_control
);
203 shader
->sprite_coord_enable
= rctx
->sprite_coord_enable
;
204 si_pm4_bind_state(rctx
, ps
, shader
->pm4
);
211 static unsigned si_conv_pipe_prim(unsigned pprim
)
213 static const unsigned prim_conv
[] = {
214 [PIPE_PRIM_POINTS
] = V_008958_DI_PT_POINTLIST
,
215 [PIPE_PRIM_LINES
] = V_008958_DI_PT_LINELIST
,
216 [PIPE_PRIM_LINE_LOOP
] = V_008958_DI_PT_LINELOOP
,
217 [PIPE_PRIM_LINE_STRIP
] = V_008958_DI_PT_LINESTRIP
,
218 [PIPE_PRIM_TRIANGLES
] = V_008958_DI_PT_TRILIST
,
219 [PIPE_PRIM_TRIANGLE_STRIP
] = V_008958_DI_PT_TRISTRIP
,
220 [PIPE_PRIM_TRIANGLE_FAN
] = V_008958_DI_PT_TRIFAN
,
221 [PIPE_PRIM_QUADS
] = V_008958_DI_PT_QUADLIST
,
222 [PIPE_PRIM_QUAD_STRIP
] = V_008958_DI_PT_QUADSTRIP
,
223 [PIPE_PRIM_POLYGON
] = V_008958_DI_PT_POLYGON
,
224 [PIPE_PRIM_LINES_ADJACENCY
] = ~0,
225 [PIPE_PRIM_LINE_STRIP_ADJACENCY
] = ~0,
226 [PIPE_PRIM_TRIANGLES_ADJACENCY
] = ~0,
227 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY
] = ~0
229 unsigned result
= prim_conv
[pprim
];
231 R600_ERR("unsupported primitive type %d\n", pprim
);
236 static bool si_update_draw_info_state(struct r600_context
*rctx
,
237 const struct pipe_draw_info
*info
)
239 struct si_pm4_state
*pm4
= CALLOC_STRUCT(si_pm4_state
);
240 unsigned prim
= si_conv_pipe_prim(info
->mode
);
241 unsigned ls_mask
= 0;
251 si_pm4_set_reg(pm4
, R_008958_VGT_PRIMITIVE_TYPE
, prim
);
252 si_pm4_set_reg(pm4
, R_028400_VGT_MAX_VTX_INDX
, ~0);
253 si_pm4_set_reg(pm4
, R_028404_VGT_MIN_VTX_INDX
, 0);
254 si_pm4_set_reg(pm4
, R_028408_VGT_INDX_OFFSET
,
255 info
->indexed
? info
->index_bias
: info
->start
);
256 si_pm4_set_reg(pm4
, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX
, info
->restart_index
);
257 si_pm4_set_reg(pm4
, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN
, info
->primitive_restart
);
259 si_pm4_set_reg(pm4
, R_03CFF0_SQ_VTX_BASE_VTX_LOC
, 0);
260 si_pm4_set_reg(pm4
, R_03CFF4_SQ_VTX_START_INST_LOC
, info
->start_instance
);
263 if (prim
== V_008958_DI_PT_LINELIST
)
265 else if (prim
== V_008958_DI_PT_LINESTRIP
)
267 si_pm4_set_reg(pm4
, R_028A0C_PA_SC_LINE_STIPPLE
,
268 S_028A0C_AUTO_RESET_CNTL(ls_mask
) |
269 rctx
->pa_sc_line_stipple
);
271 if (info
->mode
== PIPE_PRIM_QUADS
|| info
->mode
== PIPE_PRIM_QUAD_STRIP
|| info
->mode
== PIPE_PRIM_POLYGON
) {
272 si_pm4_set_reg(pm4
, R_028814_PA_SU_SC_MODE_CNTL
,
273 S_028814_PROVOKING_VTX_LAST(1) | rctx
->pa_su_sc_mode_cntl
);
275 si_pm4_set_reg(pm4
, R_028814_PA_SU_SC_MODE_CNTL
, rctx
->pa_su_sc_mode_cntl
);
277 si_pm4_set_reg(pm4
, R_02881C_PA_CL_VS_OUT_CNTL
,
278 prim
== PIPE_PRIM_POINTS
? rctx
->pa_cl_vs_out_cntl
: 0
279 /*| (rctx->rasterizer->clip_plane_enable &
280 rctx->vs_shader->shader.clip_dist_write)*/);
281 si_pm4_set_reg(pm4
, R_028810_PA_CL_CLIP_CNTL
, rctx
->pa_cl_clip_cntl
282 /*| (rctx->vs_shader->shader.clip_dist_write ||
283 rctx->vs_shader->shader.vs_prohibit_ucps ?
284 0 : rctx->rasterizer->clip_plane_enable & 0x3F)*/);
286 si_pm4_set_state(rctx
, draw_info
, pm4
);
290 static void si_update_alpha_ref(struct r600_context
*rctx
)
294 struct r600_pipe_state rstate
;
296 alpha_ref
= rctx
->alpha_ref
;
298 if (rctx
->export_16bpc
)
299 alpha_ref
&= ~0x1FFF;
300 si_pm4_set_reg(&rstate
, R_028438_SX_ALPHA_REF
, alpha_ref
);
302 si_pm4_set_state(rctx
, TODO
, pm4
);
303 rctx
->alpha_ref_dirty
= false;
307 static void si_update_spi_map(struct r600_context
*rctx
)
309 struct si_shader
*ps
= &rctx
->ps_shader
->shader
;
310 struct si_shader
*vs
= &rctx
->vs_shader
->shader
;
311 struct si_pm4_state
*pm4
= CALLOC_STRUCT(si_pm4_state
);
314 for (i
= 0; i
< ps
->ninput
; i
++) {
318 /* XXX: Flat shading hangs the GPU */
319 if (ps
->input
[i
].name
== TGSI_SEMANTIC_POSITION
||
320 ps
->input
[i
].interpolate
== TGSI_INTERPOLATE_CONSTANT
||
321 (ps
->input
[i
].interpolate
== TGSI_INTERPOLATE_COLOR
&&
322 rctx
->rasterizer
&& rctx
->rasterizer
->flatshade
)) {
323 tmp
|= S_028644_FLAT_SHADE(1);
327 if (ps
->input
[i
].name
== TGSI_SEMANTIC_GENERIC
&&
328 rctx
->sprite_coord_enable
& (1 << ps
->input
[i
].sid
)) {
329 tmp
|= S_028644_PT_SPRITE_TEX(1);
332 for (j
= 0; j
< vs
->noutput
; j
++) {
333 if (ps
->input
[i
].name
== vs
->output
[j
].name
&&
334 ps
->input
[i
].sid
== vs
->output
[j
].sid
) {
335 tmp
|= S_028644_OFFSET(vs
->output
[j
].param_offset
);
340 if (j
== vs
->noutput
) {
341 /* No corresponding output found, load defaults into input */
342 tmp
|= S_028644_OFFSET(0x20);
345 si_pm4_set_reg(pm4
, R_028644_SPI_PS_INPUT_CNTL_0
+ i
* 4, tmp
);
348 si_pm4_set_state(rctx
, spi
, pm4
);
351 static void si_update_derived_state(struct r600_context
*rctx
)
353 struct pipe_context
* ctx
= (struct pipe_context
*)rctx
;
355 if (!rctx
->blitter
->running
) {
356 if (rctx
->have_depth_fb
|| rctx
->have_depth_texture
)
357 r600_flush_depth_textures(rctx
);
360 if ((rctx
->ps_shader
->shader
.fs_write_all
&&
361 (rctx
->ps_shader
->shader
.nr_cbufs
!= rctx
->framebuffer
.nr_cbufs
)) ||
362 (rctx
->sprite_coord_enable
&&
363 (rctx
->ps_shader
->sprite_coord_enable
!= rctx
->sprite_coord_enable
))) {
364 si_pipe_shader_destroy(&rctx
->context
, rctx
->ps_shader
);
367 if (rctx
->alpha_ref_dirty
) {
368 si_update_alpha_ref(rctx
);
371 if (!rctx
->vs_shader
->bo
) {
372 si_pipe_shader_vs(ctx
, rctx
->vs_shader
);
375 if (!rctx
->ps_shader
->bo
) {
376 si_pipe_shader_ps(ctx
, rctx
->ps_shader
);
378 if (!rctx
->ps_shader
->bo
) {
379 if (!rctx
->dummy_pixel_shader
->bo
)
380 si_pipe_shader_ps(ctx
, rctx
->dummy_pixel_shader
);
382 if (rctx
->dummy_pixel_shader
->pm4
)
383 si_pm4_bind_state(rctx
, vs
, rctx
->dummy_pixel_shader
->pm4
);
386 if (rctx
->shader_dirty
) {
387 si_update_spi_map(rctx
);
388 rctx
->shader_dirty
= false;
392 static void si_vertex_buffer_update(struct r600_context
*rctx
)
394 struct pipe_context
*ctx
= &rctx
->context
;
395 struct si_pm4_state
*pm4
= CALLOC_STRUCT(si_pm4_state
);
396 bool bound
[PIPE_MAX_ATTRIBS
] = {};
397 struct si_resource
*t_list_buffer
;
402 si_pm4_inval_vertex_cache(pm4
);
404 /* bind vertex buffer once */
405 count
= rctx
->vertex_elements
->count
;
406 assert(count
<= 256 / 4);
408 t_list_buffer
= si_resource_create_custom(ctx
->screen
, PIPE_USAGE_IMMUTABLE
,
410 if (t_list_buffer
== NULL
) {
414 si_pm4_add_bo(pm4
, t_list_buffer
, RADEON_USAGE_READ
);
416 ptr
= (uint32_t*)rctx
->ws
->buffer_map(t_list_buffer
->cs_buf
,
418 PIPE_TRANSFER_WRITE
);
420 for (i
= 0 ; i
< count
; i
++, ptr
+= 4) {
421 struct pipe_vertex_element
*ve
= &rctx
->vertex_elements
->elements
[i
];
422 struct pipe_vertex_buffer
*vb
;
423 struct si_resource
*rbuffer
;
426 if (ve
->vertex_buffer_index
>= rctx
->nr_vertex_buffers
)
429 vb
= &rctx
->vertex_buffer
[ve
->vertex_buffer_index
];
430 rbuffer
= (struct si_resource
*)vb
->buffer
;
435 offset
+= vb
->buffer_offset
;
436 offset
+= ve
->src_offset
;
438 va
= r600_resource_va(ctx
->screen
, (void*)rbuffer
);
441 /* Fill in T# buffer resource description */
442 ptr
[0] = va
& 0xFFFFFFFF;
443 ptr
[1] = (S_008F04_BASE_ADDRESS_HI(va
>> 32) |
444 S_008F04_STRIDE(vb
->stride
));
446 ptr
[2] = (vb
->buffer
->width0
- offset
) / vb
->stride
;
448 ptr
[2] = vb
->buffer
->width0
- offset
;
449 ptr
[3] = rctx
->vertex_elements
->rsrc_word3
[i
];
451 if (!bound
[ve
->vertex_buffer_index
]) {
452 si_pm4_add_bo(pm4
, rbuffer
, RADEON_USAGE_READ
);
453 bound
[ve
->vertex_buffer_index
] = true;
457 va
= r600_resource_va(ctx
->screen
, (void*)t_list_buffer
);
458 si_pm4_set_reg(pm4
, R_00B148_SPI_SHADER_USER_DATA_VS_6
, va
);
459 si_pm4_set_reg(pm4
, R_00B14C_SPI_SHADER_USER_DATA_VS_7
, va
>> 32);
460 si_pm4_set_state(rctx
, vertex_buffers
, pm4
);
463 static void si_state_draw(struct r600_context
*rctx
,
464 const struct pipe_draw_info
*info
,
465 const struct pipe_index_buffer
*ib
)
467 struct si_pm4_state
*pm4
= CALLOC_STRUCT(si_pm4_state
);
469 /* queries need some special values
470 * (this is non-zero if any query is active) */
471 if (rctx
->num_cs_dw_queries_suspend
) {
472 struct si_state_dsa
*dsa
= rctx
->queued
.named
.dsa
;
474 si_pm4_set_reg(pm4
, R_028004_DB_COUNT_CONTROL
,
475 S_028004_PERFECT_ZPASS_COUNTS(1));
476 si_pm4_set_reg(pm4
, R_02800C_DB_RENDER_OVERRIDE
,
477 dsa
->db_render_override
|
478 S_02800C_NOOP_CULL_DISABLE(1));
482 si_pm4_cmd_begin(pm4
, PKT3_INDEX_TYPE
);
483 if (ib
->index_size
== 4) {
484 si_pm4_cmd_add(pm4
, V_028A7C_VGT_INDEX_32
| (R600_BIG_ENDIAN
?
485 V_028A7C_VGT_DMA_SWAP_32_BIT
: 0));
487 si_pm4_cmd_add(pm4
, V_028A7C_VGT_INDEX_16
| (R600_BIG_ENDIAN
?
488 V_028A7C_VGT_DMA_SWAP_16_BIT
: 0));
490 si_pm4_cmd_end(pm4
, rctx
->predicate_drawing
);
492 si_pm4_cmd_begin(pm4
, PKT3_NUM_INSTANCES
);
493 si_pm4_cmd_add(pm4
, info
->instance_count
);
494 si_pm4_cmd_end(pm4
, rctx
->predicate_drawing
);
498 va
= r600_resource_va(&rctx
->screen
->screen
, ib
->buffer
);
501 si_pm4_add_bo(pm4
, (struct si_resource
*)ib
->buffer
, RADEON_USAGE_READ
);
502 si_pm4_cmd_begin(pm4
, PKT3_DRAW_INDEX_2
);
503 si_pm4_cmd_add(pm4
, (ib
->buffer
->width0
- ib
->offset
) /
504 rctx
->index_buffer
.index_size
);
505 si_pm4_cmd_add(pm4
, va
);
506 si_pm4_cmd_add(pm4
, (va
>> 32UL) & 0xFF);
507 si_pm4_cmd_add(pm4
, info
->count
);
508 si_pm4_cmd_add(pm4
, V_0287F0_DI_SRC_SEL_DMA
);
509 si_pm4_cmd_end(pm4
, rctx
->predicate_drawing
);
511 si_pm4_cmd_begin(pm4
, PKT3_DRAW_INDEX_AUTO
);
512 si_pm4_cmd_add(pm4
, info
->count
);
513 si_pm4_cmd_add(pm4
, V_0287F0_DI_SRC_SEL_AUTO_INDEX
|
514 (info
->count_from_stream_output
?
515 S_0287F0_USE_OPAQUE(1) : 0));
516 si_pm4_cmd_end(pm4
, rctx
->predicate_drawing
);
518 si_pm4_set_state(rctx
, draw
, pm4
);
521 void si_draw_vbo(struct pipe_context
*ctx
, const struct pipe_draw_info
*info
)
523 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
524 struct pipe_index_buffer ib
= {};
525 uint32_t cp_coher_cntl
;
527 if ((!info
->count
&& (info
->indexed
|| !info
->count_from_stream_output
)) ||
528 (info
->indexed
&& !rctx
->index_buffer
.buffer
)) {
532 if (!rctx
->ps_shader
|| !rctx
->vs_shader
)
535 si_update_derived_state(rctx
);
536 si_vertex_buffer_update(rctx
);
539 /* Initialize the index buffer struct. */
540 pipe_resource_reference(&ib
.buffer
, rctx
->index_buffer
.buffer
);
541 ib
.index_size
= rctx
->index_buffer
.index_size
;
542 ib
.offset
= rctx
->index_buffer
.offset
+ info
->start
* ib
.index_size
;
544 /* Translate or upload, if needed. */
545 r600_translate_index_buffer(rctx
, &ib
, info
->count
);
547 if (ib
.user_buffer
) {
548 r600_upload_index_buffer(rctx
, &ib
, info
->count
);
551 } else if (info
->count_from_stream_output
) {
552 r600_context_draw_opaque_count(rctx
, (struct r600_so_target
*)info
->count_from_stream_output
);
555 rctx
->vs_shader_so_strides
= rctx
->vs_shader
->so_strides
;
557 if (!si_update_draw_info_state(rctx
, info
))
560 si_state_draw(rctx
, info
, &ib
);
562 cp_coher_cntl
= si_pm4_sync_flags(rctx
);
564 struct si_pm4_state
*pm4
= CALLOC_STRUCT(si_pm4_state
);
565 si_cmd_surface_sync(pm4
, cp_coher_cntl
);
566 si_pm4_set_state(rctx
, sync
, pm4
);
570 rctx
->pm4_dirty_cdwords
+= si_pm4_dirty_dw(rctx
);
572 r600_need_cs_space(rctx
, 0, TRUE
);
574 si_pm4_emit_dirty(rctx
);
575 rctx
->pm4_dirty_cdwords
= 0;
578 /* Enable stream out if needed. */
579 if (rctx
->streamout_start
) {
580 r600_context_streamout_begin(rctx
);
581 rctx
->streamout_start
= FALSE
;
586 rctx
->flags
|= R600_CONTEXT_DST_CACHES_DIRTY
;
588 if (rctx
->framebuffer
.zsbuf
)
590 struct pipe_resource
*tex
= rctx
->framebuffer
.zsbuf
->texture
;
591 ((struct r600_resource_texture
*)tex
)->dirty_db
= TRUE
;
594 pipe_resource_reference(&ib
.buffer
, NULL
);