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[mesa.git] / src / gallium / drivers / radeonsi / si_state_draw.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Christian König <christian.koenig@amd.com>
25 */
26
27 #include "util/u_memory.h"
28 #include "util/u_framebuffer.h"
29 #include "util/u_blitter.h"
30 #include "tgsi/tgsi_parse.h"
31 #include "radeonsi_pipe.h"
32 #include "radeonsi_shader.h"
33 #include "si_state.h"
34 #include "sid.h"
35
36 /*
37 * Shaders
38 */
39
40 static void si_pipe_shader_vs(struct pipe_context *ctx, struct si_pipe_shader *shader)
41 {
42 struct r600_context *rctx = (struct r600_context *)ctx;
43 struct si_pm4_state *pm4;
44 unsigned num_sgprs, num_user_sgprs;
45 unsigned nparams, i, vgpr_comp_cnt;
46 uint64_t va;
47
48 si_pm4_delete_state(rctx, vs, shader->pm4);
49 pm4 = shader->pm4 = si_pm4_alloc_state(rctx);
50
51 if (pm4 == NULL)
52 return;
53
54 si_pm4_inval_shader_cache(pm4);
55
56 /* Certain attributes (position, psize, etc.) don't count as params.
57 * VS is required to export at least one param and r600_shader_from_tgsi()
58 * takes care of adding a dummy export.
59 */
60 for (nparams = 0, i = 0 ; i < shader->shader.noutput; i++) {
61 switch (shader->shader.output[i].name) {
62 case TGSI_SEMANTIC_CLIPVERTEX:
63 case TGSI_SEMANTIC_POSITION:
64 case TGSI_SEMANTIC_PSIZE:
65 break;
66 default:
67 nparams++;
68 }
69 }
70 if (nparams < 1)
71 nparams = 1;
72
73 si_pm4_set_reg(pm4, R_0286C4_SPI_VS_OUT_CONFIG,
74 S_0286C4_VS_EXPORT_COUNT(nparams - 1));
75
76 si_pm4_set_reg(pm4, R_02870C_SPI_SHADER_POS_FORMAT,
77 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
78 S_02870C_POS1_EXPORT_FORMAT(shader->shader.nr_pos_exports > 1 ?
79 V_02870C_SPI_SHADER_4COMP :
80 V_02870C_SPI_SHADER_NONE) |
81 S_02870C_POS2_EXPORT_FORMAT(shader->shader.nr_pos_exports > 2 ?
82 V_02870C_SPI_SHADER_4COMP :
83 V_02870C_SPI_SHADER_NONE) |
84 S_02870C_POS3_EXPORT_FORMAT(shader->shader.nr_pos_exports > 3 ?
85 V_02870C_SPI_SHADER_4COMP :
86 V_02870C_SPI_SHADER_NONE));
87
88 va = r600_resource_va(ctx->screen, (void *)shader->bo);
89 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ);
90 si_pm4_set_reg(pm4, R_00B120_SPI_SHADER_PGM_LO_VS, va >> 8);
91 si_pm4_set_reg(pm4, R_00B124_SPI_SHADER_PGM_HI_VS, va >> 40);
92
93 num_user_sgprs = SI_VS_NUM_USER_SGPR;
94 num_sgprs = shader->num_sgprs;
95 if (num_user_sgprs > num_sgprs) {
96 /* Last 2 reserved SGPRs are used for VCC */
97 num_sgprs = num_user_sgprs + 2;
98 }
99 assert(num_sgprs <= 104);
100
101 vgpr_comp_cnt = shader->shader.uses_instanceid ? 3 : 0;
102
103 si_pm4_set_reg(pm4, R_00B128_SPI_SHADER_PGM_RSRC1_VS,
104 S_00B128_VGPRS((shader->num_vgprs - 1) / 4) |
105 S_00B128_SGPRS((num_sgprs - 1) / 8) |
106 S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt));
107 si_pm4_set_reg(pm4, R_00B12C_SPI_SHADER_PGM_RSRC2_VS,
108 S_00B12C_USER_SGPR(num_user_sgprs));
109
110 if (rctx->chip_class >= CIK) {
111 si_pm4_set_reg(pm4, R_00B118_SPI_SHADER_PGM_RSRC3_VS,
112 S_00B118_CU_EN(0xffff));
113 si_pm4_set_reg(pm4, R_00B11C_SPI_SHADER_LATE_ALLOC_VS,
114 S_00B11C_LIMIT(0));
115 }
116
117 si_pm4_bind_state(rctx, vs, shader->pm4);
118 }
119
120 static void si_pipe_shader_ps(struct pipe_context *ctx, struct si_pipe_shader *shader)
121 {
122 struct r600_context *rctx = (struct r600_context *)ctx;
123 struct si_pm4_state *pm4;
124 unsigned i, exports_ps, num_cout, spi_ps_in_control, db_shader_control;
125 unsigned num_sgprs, num_user_sgprs;
126 unsigned spi_baryc_cntl = 0, spi_ps_input_ena, spi_shader_z_format;
127 uint64_t va;
128
129 si_pm4_delete_state(rctx, ps, shader->pm4);
130 pm4 = shader->pm4 = si_pm4_alloc_state(rctx);
131
132 if (pm4 == NULL)
133 return;
134
135 si_pm4_inval_shader_cache(pm4);
136
137 db_shader_control = S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z) |
138 S_02880C_ALPHA_TO_MASK_DISABLE(rctx->fb_cb0_is_integer);
139
140 for (i = 0; i < shader->shader.ninput; i++) {
141 switch (shader->shader.input[i].name) {
142 case TGSI_SEMANTIC_POSITION:
143 if (shader->shader.input[i].centroid) {
144 /* SPI_BARYC_CNTL.POS_FLOAT_LOCATION
145 * Possible vaules:
146 * 0 -> Position = pixel center (default)
147 * 1 -> Position = pixel centroid
148 * 2 -> Position = iterated sample number XXX:
149 * What does this mean?
150 */
151 spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(1);
152 }
153 /* Fall through */
154 case TGSI_SEMANTIC_FACE:
155 continue;
156 }
157 }
158
159 for (i = 0; i < shader->shader.noutput; i++) {
160 if (shader->shader.output[i].name == TGSI_SEMANTIC_POSITION)
161 db_shader_control |= S_02880C_Z_EXPORT_ENABLE(1);
162 if (shader->shader.output[i].name == TGSI_SEMANTIC_STENCIL)
163 db_shader_control |= S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(1);
164 }
165 if (shader->shader.uses_kill || shader->key.ps.alpha_func != PIPE_FUNC_ALWAYS)
166 db_shader_control |= S_02880C_KILL_ENABLE(1);
167
168 exports_ps = 0;
169 num_cout = 0;
170 for (i = 0; i < shader->shader.noutput; i++) {
171 if (shader->shader.output[i].name == TGSI_SEMANTIC_POSITION ||
172 shader->shader.output[i].name == TGSI_SEMANTIC_STENCIL)
173 exports_ps |= 1;
174 else if (shader->shader.output[i].name == TGSI_SEMANTIC_COLOR) {
175 if (shader->shader.fs_write_all)
176 num_cout = shader->shader.nr_cbufs;
177 else
178 num_cout++;
179 }
180 }
181 if (!exports_ps) {
182 /* always at least export 1 component per pixel */
183 exports_ps = 2;
184 }
185
186 spi_ps_in_control = S_0286D8_NUM_INTERP(shader->shader.ninterp) |
187 S_0286D8_BC_OPTIMIZE_DISABLE(1);
188
189 si_pm4_set_reg(pm4, R_0286E0_SPI_BARYC_CNTL, spi_baryc_cntl);
190 spi_ps_input_ena = shader->spi_ps_input_ena;
191 /* we need to enable at least one of them, otherwise we hang the GPU */
192 assert(G_0286CC_PERSP_SAMPLE_ENA(spi_ps_input_ena) ||
193 G_0286CC_PERSP_CENTER_ENA(spi_ps_input_ena) ||
194 G_0286CC_PERSP_CENTROID_ENA(spi_ps_input_ena) ||
195 G_0286CC_PERSP_PULL_MODEL_ENA(spi_ps_input_ena) ||
196 G_0286CC_LINEAR_SAMPLE_ENA(spi_ps_input_ena) ||
197 G_0286CC_LINEAR_CENTER_ENA(spi_ps_input_ena) ||
198 G_0286CC_LINEAR_CENTROID_ENA(spi_ps_input_ena) ||
199 G_0286CC_LINE_STIPPLE_TEX_ENA(spi_ps_input_ena));
200
201 si_pm4_set_reg(pm4, R_0286CC_SPI_PS_INPUT_ENA, spi_ps_input_ena);
202 si_pm4_set_reg(pm4, R_0286D0_SPI_PS_INPUT_ADDR, spi_ps_input_ena);
203 si_pm4_set_reg(pm4, R_0286D8_SPI_PS_IN_CONTROL, spi_ps_in_control);
204
205 if (G_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(db_shader_control))
206 spi_shader_z_format = V_028710_SPI_SHADER_32_GR;
207 else if (G_02880C_Z_EXPORT_ENABLE(db_shader_control))
208 spi_shader_z_format = V_028710_SPI_SHADER_32_R;
209 else
210 spi_shader_z_format = 0;
211 si_pm4_set_reg(pm4, R_028710_SPI_SHADER_Z_FORMAT, spi_shader_z_format);
212 si_pm4_set_reg(pm4, R_028714_SPI_SHADER_COL_FORMAT,
213 shader->spi_shader_col_format);
214 si_pm4_set_reg(pm4, R_02823C_CB_SHADER_MASK, shader->cb_shader_mask);
215
216 va = r600_resource_va(ctx->screen, (void *)shader->bo);
217 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ);
218 si_pm4_set_reg(pm4, R_00B020_SPI_SHADER_PGM_LO_PS, va >> 8);
219 si_pm4_set_reg(pm4, R_00B024_SPI_SHADER_PGM_HI_PS, va >> 40);
220
221 num_user_sgprs = SI_PS_NUM_USER_SGPR;
222 num_sgprs = shader->num_sgprs;
223 /* One SGPR after user SGPRs is pre-loaded with {prim_mask, lds_offset} */
224 if ((num_user_sgprs + 1) > num_sgprs) {
225 /* Last 2 reserved SGPRs are used for VCC */
226 num_sgprs = num_user_sgprs + 1 + 2;
227 }
228 assert(num_sgprs <= 104);
229
230 si_pm4_set_reg(pm4, R_00B028_SPI_SHADER_PGM_RSRC1_PS,
231 S_00B028_VGPRS((shader->num_vgprs - 1) / 4) |
232 S_00B028_SGPRS((num_sgprs - 1) / 8));
233 si_pm4_set_reg(pm4, R_00B02C_SPI_SHADER_PGM_RSRC2_PS,
234 S_00B02C_EXTRA_LDS_SIZE(shader->lds_size) |
235 S_00B02C_USER_SGPR(num_user_sgprs));
236 if (rctx->chip_class >= CIK) {
237 si_pm4_set_reg(pm4, R_00B01C_SPI_SHADER_PGM_RSRC3_PS,
238 S_00B01C_CU_EN(0xffff));
239 }
240
241 si_pm4_set_reg(pm4, R_02880C_DB_SHADER_CONTROL, db_shader_control);
242
243 shader->cb0_is_integer = rctx->fb_cb0_is_integer;
244 shader->sprite_coord_enable = rctx->sprite_coord_enable;
245 si_pm4_bind_state(rctx, ps, shader->pm4);
246 }
247
248 /*
249 * Drawing
250 */
251
252 static unsigned si_conv_pipe_prim(unsigned pprim)
253 {
254 static const unsigned prim_conv[] = {
255 [PIPE_PRIM_POINTS] = V_008958_DI_PT_POINTLIST,
256 [PIPE_PRIM_LINES] = V_008958_DI_PT_LINELIST,
257 [PIPE_PRIM_LINE_LOOP] = V_008958_DI_PT_LINELOOP,
258 [PIPE_PRIM_LINE_STRIP] = V_008958_DI_PT_LINESTRIP,
259 [PIPE_PRIM_TRIANGLES] = V_008958_DI_PT_TRILIST,
260 [PIPE_PRIM_TRIANGLE_STRIP] = V_008958_DI_PT_TRISTRIP,
261 [PIPE_PRIM_TRIANGLE_FAN] = V_008958_DI_PT_TRIFAN,
262 [PIPE_PRIM_QUADS] = V_008958_DI_PT_QUADLIST,
263 [PIPE_PRIM_QUAD_STRIP] = V_008958_DI_PT_QUADSTRIP,
264 [PIPE_PRIM_POLYGON] = V_008958_DI_PT_POLYGON,
265 [PIPE_PRIM_LINES_ADJACENCY] = ~0,
266 [PIPE_PRIM_LINE_STRIP_ADJACENCY] = ~0,
267 [PIPE_PRIM_TRIANGLES_ADJACENCY] = ~0,
268 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY] = ~0
269 };
270 unsigned result = prim_conv[pprim];
271 if (result == ~0) {
272 R600_ERR("unsupported primitive type %d\n", pprim);
273 }
274 return result;
275 }
276
277 static bool si_update_draw_info_state(struct r600_context *rctx,
278 const struct pipe_draw_info *info)
279 {
280 struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx);
281 struct si_shader *vs = &rctx->vs_shader->current->shader;
282 unsigned prim = si_conv_pipe_prim(info->mode);
283 unsigned ls_mask = 0;
284
285 if (pm4 == NULL)
286 return false;
287
288 if (prim == ~0) {
289 FREE(pm4);
290 return false;
291 }
292
293 if (rctx->chip_class >= CIK)
294 si_pm4_set_reg(pm4, R_030908_VGT_PRIMITIVE_TYPE, prim);
295 else
296 si_pm4_set_reg(pm4, R_008958_VGT_PRIMITIVE_TYPE, prim);
297 si_pm4_set_reg(pm4, R_028400_VGT_MAX_VTX_INDX, ~0);
298 si_pm4_set_reg(pm4, R_028404_VGT_MIN_VTX_INDX, 0);
299 si_pm4_set_reg(pm4, R_028408_VGT_INDX_OFFSET,
300 info->indexed ? info->index_bias : info->start);
301 si_pm4_set_reg(pm4, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, info->restart_index);
302 si_pm4_set_reg(pm4, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, info->primitive_restart);
303 si_pm4_set_reg(pm4, R_00B130_SPI_SHADER_USER_DATA_VS_0 + SI_SGPR_START_INSTANCE * 4,
304 info->start_instance);
305
306 if (prim == V_008958_DI_PT_LINELIST)
307 ls_mask = 1;
308 else if (prim == V_008958_DI_PT_LINESTRIP)
309 ls_mask = 2;
310 si_pm4_set_reg(pm4, R_028A0C_PA_SC_LINE_STIPPLE,
311 S_028A0C_AUTO_RESET_CNTL(ls_mask) |
312 rctx->pa_sc_line_stipple);
313
314 if (info->mode == PIPE_PRIM_QUADS || info->mode == PIPE_PRIM_QUAD_STRIP || info->mode == PIPE_PRIM_POLYGON) {
315 si_pm4_set_reg(pm4, R_028814_PA_SU_SC_MODE_CNTL,
316 S_028814_PROVOKING_VTX_LAST(1) | rctx->pa_su_sc_mode_cntl);
317 } else {
318 si_pm4_set_reg(pm4, R_028814_PA_SU_SC_MODE_CNTL, rctx->pa_su_sc_mode_cntl);
319 }
320 si_pm4_set_reg(pm4, R_02881C_PA_CL_VS_OUT_CNTL,
321 S_02881C_USE_VTX_POINT_SIZE(vs->vs_out_point_size) |
322 S_02881C_VS_OUT_CCDIST0_VEC_ENA((vs->clip_dist_write & 0x0F) != 0) |
323 S_02881C_VS_OUT_CCDIST1_VEC_ENA((vs->clip_dist_write & 0xF0) != 0) |
324 S_02881C_VS_OUT_MISC_VEC_ENA(vs->vs_out_misc_write) |
325 (rctx->queued.named.rasterizer->clip_plane_enable &
326 vs->clip_dist_write));
327 si_pm4_set_reg(pm4, R_028810_PA_CL_CLIP_CNTL,
328 rctx->queued.named.rasterizer->pa_cl_clip_cntl |
329 (vs->clip_dist_write ? 0 :
330 rctx->queued.named.rasterizer->clip_plane_enable & 0x3F));
331
332 si_pm4_set_state(rctx, draw_info, pm4);
333 return true;
334 }
335
336 static void si_update_spi_map(struct r600_context *rctx)
337 {
338 struct si_shader *ps = &rctx->ps_shader->current->shader;
339 struct si_shader *vs = &rctx->vs_shader->current->shader;
340 struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx);
341 unsigned i, j, tmp;
342
343 for (i = 0; i < ps->ninput; i++) {
344 unsigned name = ps->input[i].name;
345 unsigned param_offset = ps->input[i].param_offset;
346
347 if (name == TGSI_SEMANTIC_POSITION)
348 /* Read from preloaded VGPRs, not parameters */
349 continue;
350
351 bcolor:
352 tmp = 0;
353
354 if (ps->input[i].interpolate == TGSI_INTERPOLATE_CONSTANT ||
355 (ps->input[i].interpolate == TGSI_INTERPOLATE_COLOR &&
356 rctx->ps_shader->current->key.ps.flatshade)) {
357 tmp |= S_028644_FLAT_SHADE(1);
358 }
359
360 if (name == TGSI_SEMANTIC_GENERIC &&
361 rctx->sprite_coord_enable & (1 << ps->input[i].sid)) {
362 tmp |= S_028644_PT_SPRITE_TEX(1);
363 }
364
365 for (j = 0; j < vs->noutput; j++) {
366 if (name == vs->output[j].name &&
367 ps->input[i].sid == vs->output[j].sid) {
368 tmp |= S_028644_OFFSET(vs->output[j].param_offset);
369 break;
370 }
371 }
372
373 if (j == vs->noutput) {
374 /* No corresponding output found, load defaults into input */
375 tmp |= S_028644_OFFSET(0x20);
376 }
377
378 si_pm4_set_reg(pm4,
379 R_028644_SPI_PS_INPUT_CNTL_0 + param_offset * 4,
380 tmp);
381
382 if (name == TGSI_SEMANTIC_COLOR &&
383 rctx->ps_shader->current->key.ps.color_two_side) {
384 name = TGSI_SEMANTIC_BCOLOR;
385 param_offset++;
386 goto bcolor;
387 }
388 }
389
390 si_pm4_set_state(rctx, spi, pm4);
391 }
392
393 static void si_update_derived_state(struct r600_context *rctx)
394 {
395 struct pipe_context * ctx = (struct pipe_context*)rctx;
396 unsigned vs_dirty = 0, ps_dirty = 0;
397
398 if (!rctx->blitter->running) {
399 /* Flush depth textures which need to be flushed. */
400 for (int i = 0; i < SI_NUM_SHADERS; i++) {
401 if (rctx->samplers[i].depth_texture_mask) {
402 si_flush_depth_textures(rctx, &rctx->samplers[i]);
403 }
404 if (rctx->samplers[i].compressed_colortex_mask) {
405 r600_decompress_color_textures(rctx, &rctx->samplers[i]);
406 }
407 }
408 }
409
410 si_shader_select(ctx, rctx->vs_shader, &vs_dirty);
411
412 if (!rctx->vs_shader->current->pm4) {
413 si_pipe_shader_vs(ctx, rctx->vs_shader->current);
414 vs_dirty = 0;
415 }
416
417 if (vs_dirty) {
418 si_pm4_bind_state(rctx, vs, rctx->vs_shader->current->pm4);
419 }
420
421
422 si_shader_select(ctx, rctx->ps_shader, &ps_dirty);
423
424 if (!rctx->ps_shader->current->pm4) {
425 si_pipe_shader_ps(ctx, rctx->ps_shader->current);
426 ps_dirty = 0;
427 }
428 if (!rctx->ps_shader->current->bo) {
429 if (!rctx->dummy_pixel_shader->pm4)
430 si_pipe_shader_ps(ctx, rctx->dummy_pixel_shader);
431 else
432 si_pm4_bind_state(rctx, vs, rctx->dummy_pixel_shader->pm4);
433
434 ps_dirty = 0;
435 }
436 if (rctx->ps_shader->current->cb0_is_integer != rctx->fb_cb0_is_integer) {
437 si_pipe_shader_ps(ctx, rctx->ps_shader->current);
438 ps_dirty = 1;
439 }
440
441 if (ps_dirty) {
442 si_pm4_bind_state(rctx, ps, rctx->ps_shader->current->pm4);
443 }
444
445 if (si_pm4_state_changed(rctx, ps) || si_pm4_state_changed(rctx, vs)) {
446 /* XXX: Emitting the PS state even when only the VS changed
447 * fixes random failures with piglit glsl-max-varyings.
448 * Not sure why...
449 */
450 rctx->emitted.named.ps = NULL;
451 si_update_spi_map(rctx);
452 }
453 }
454
455 static void si_constant_buffer_update(struct r600_context *rctx)
456 {
457 struct pipe_context *ctx = &rctx->context;
458 struct si_pm4_state *pm4;
459 unsigned shader, i;
460 uint64_t va;
461
462 if (!rctx->constbuf_state[PIPE_SHADER_VERTEX].dirty_mask &&
463 !rctx->constbuf_state[PIPE_SHADER_FRAGMENT].dirty_mask)
464 return;
465
466 for (shader = PIPE_SHADER_VERTEX ; shader <= PIPE_SHADER_FRAGMENT; shader++) {
467 struct r600_constbuf_state *state = &rctx->constbuf_state[shader];
468
469 pm4 = CALLOC_STRUCT(si_pm4_state);
470 if (!pm4)
471 continue;
472
473 si_pm4_inval_shader_cache(pm4);
474 si_pm4_sh_data_begin(pm4);
475
476 for (i = 0; i < 2; i++) {
477 if (state->enabled_mask & (1 << i)) {
478 struct pipe_constant_buffer *cb = &state->cb[i];
479 struct si_resource *rbuffer = si_resource(cb->buffer);
480
481 va = r600_resource_va(ctx->screen, (void*)rbuffer);
482 va += cb->buffer_offset;
483
484 si_pm4_add_bo(pm4, rbuffer, RADEON_USAGE_READ);
485
486 /* Fill in a T# buffer resource description */
487 si_pm4_sh_data_add(pm4, va);
488 si_pm4_sh_data_add(pm4, (S_008F04_BASE_ADDRESS_HI(va >> 32) |
489 S_008F04_STRIDE(0)));
490 si_pm4_sh_data_add(pm4, cb->buffer_size);
491 si_pm4_sh_data_add(pm4, S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
492 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
493 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
494 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
495 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
496 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32));
497 } else {
498 /* Fill in an empty T# buffer resource description */
499 si_pm4_sh_data_add(pm4, 0);
500 si_pm4_sh_data_add(pm4, 0);
501 si_pm4_sh_data_add(pm4, 0);
502 si_pm4_sh_data_add(pm4, 0);
503 }
504 }
505
506 switch (shader) {
507 case PIPE_SHADER_VERTEX:
508 si_pm4_sh_data_end(pm4, R_00B130_SPI_SHADER_USER_DATA_VS_0, SI_SGPR_CONST);
509 si_pm4_set_state(rctx, vs_const, pm4);
510 break;
511
512 case PIPE_SHADER_FRAGMENT:
513 si_pm4_sh_data_end(pm4, R_00B030_SPI_SHADER_USER_DATA_PS_0, SI_SGPR_CONST);
514 si_pm4_set_state(rctx, ps_const, pm4);
515 break;
516
517 default:
518 R600_ERR("unsupported %d\n", shader);
519 FREE(pm4);
520 return;
521 }
522
523 state->dirty_mask = 0;
524 }
525 }
526
527 static void si_vertex_buffer_update(struct r600_context *rctx)
528 {
529 struct pipe_context *ctx = &rctx->context;
530 struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx);
531 bool bound[PIPE_MAX_ATTRIBS] = {};
532 unsigned i, count;
533 uint64_t va;
534
535 si_pm4_inval_texture_cache(pm4);
536
537 /* bind vertex buffer once */
538 count = rctx->vertex_elements->count;
539 assert(count <= 256 / 4);
540
541 si_pm4_sh_data_begin(pm4);
542 for (i = 0 ; i < count; i++) {
543 struct pipe_vertex_element *ve = &rctx->vertex_elements->elements[i];
544 struct pipe_vertex_buffer *vb;
545 struct si_resource *rbuffer;
546 unsigned offset;
547
548 if (ve->vertex_buffer_index >= rctx->nr_vertex_buffers)
549 continue;
550
551 vb = &rctx->vertex_buffer[ve->vertex_buffer_index];
552 rbuffer = (struct si_resource*)vb->buffer;
553 if (rbuffer == NULL)
554 continue;
555
556 offset = 0;
557 offset += vb->buffer_offset;
558 offset += ve->src_offset;
559
560 va = r600_resource_va(ctx->screen, (void*)rbuffer);
561 va += offset;
562
563 /* Fill in T# buffer resource description */
564 si_pm4_sh_data_add(pm4, va & 0xFFFFFFFF);
565 si_pm4_sh_data_add(pm4, (S_008F04_BASE_ADDRESS_HI(va >> 32) |
566 S_008F04_STRIDE(vb->stride)));
567 if (vb->stride)
568 /* Round up by rounding down and adding 1 */
569 si_pm4_sh_data_add(pm4,
570 (vb->buffer->width0 - offset -
571 util_format_get_blocksize(ve->src_format)) /
572 vb->stride + 1);
573 else
574 si_pm4_sh_data_add(pm4, vb->buffer->width0 - offset);
575 si_pm4_sh_data_add(pm4, rctx->vertex_elements->rsrc_word3[i]);
576
577 if (!bound[ve->vertex_buffer_index]) {
578 si_pm4_add_bo(pm4, rbuffer, RADEON_USAGE_READ);
579 bound[ve->vertex_buffer_index] = true;
580 }
581 }
582 si_pm4_sh_data_end(pm4, R_00B130_SPI_SHADER_USER_DATA_VS_0, SI_SGPR_VERTEX_BUFFER);
583 si_pm4_set_state(rctx, vertex_buffers, pm4);
584 }
585
586 static void si_state_draw(struct r600_context *rctx,
587 const struct pipe_draw_info *info,
588 const struct pipe_index_buffer *ib)
589 {
590 struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx);
591
592 if (pm4 == NULL)
593 return;
594
595 /* queries need some special values
596 * (this is non-zero if any query is active) */
597 if (rctx->num_cs_dw_nontimer_queries_suspend) {
598 struct si_state_dsa *dsa = rctx->queued.named.dsa;
599
600 si_pm4_set_reg(pm4, R_028004_DB_COUNT_CONTROL,
601 S_028004_PERFECT_ZPASS_COUNTS(1) |
602 S_028004_SAMPLE_RATE(rctx->fb_log_samples));
603 si_pm4_set_reg(pm4, R_02800C_DB_RENDER_OVERRIDE,
604 dsa->db_render_override |
605 S_02800C_NOOP_CULL_DISABLE(1));
606 }
607
608 /* draw packet */
609 si_pm4_cmd_begin(pm4, PKT3_INDEX_TYPE);
610 if (ib->index_size == 4) {
611 si_pm4_cmd_add(pm4, V_028A7C_VGT_INDEX_32 | (R600_BIG_ENDIAN ?
612 V_028A7C_VGT_DMA_SWAP_32_BIT : 0));
613 } else {
614 si_pm4_cmd_add(pm4, V_028A7C_VGT_INDEX_16 | (R600_BIG_ENDIAN ?
615 V_028A7C_VGT_DMA_SWAP_16_BIT : 0));
616 }
617 si_pm4_cmd_end(pm4, rctx->predicate_drawing);
618
619 si_pm4_cmd_begin(pm4, PKT3_NUM_INSTANCES);
620 si_pm4_cmd_add(pm4, info->instance_count);
621 si_pm4_cmd_end(pm4, rctx->predicate_drawing);
622
623 if (info->indexed) {
624 uint32_t max_size = (ib->buffer->width0 - ib->offset) /
625 rctx->index_buffer.index_size;
626 uint64_t va;
627 va = r600_resource_va(&rctx->screen->screen, ib->buffer);
628 va += ib->offset;
629
630 si_pm4_add_bo(pm4, (struct si_resource *)ib->buffer, RADEON_USAGE_READ);
631 si_cmd_draw_index_2(pm4, max_size, va, info->count,
632 V_0287F0_DI_SRC_SEL_DMA,
633 rctx->predicate_drawing);
634 } else {
635 uint32_t initiator = V_0287F0_DI_SRC_SEL_AUTO_INDEX;
636 initiator |= S_0287F0_USE_OPAQUE(!!info->count_from_stream_output);
637 si_cmd_draw_index_auto(pm4, info->count, initiator, rctx->predicate_drawing);
638 }
639 si_pm4_set_state(rctx, draw, pm4);
640 }
641
642 void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info)
643 {
644 struct r600_context *rctx = (struct r600_context *)ctx;
645 struct pipe_index_buffer ib = {};
646 uint32_t cp_coher_cntl, i;
647
648 if (!info->count && (info->indexed || !info->count_from_stream_output))
649 return;
650
651 if (!rctx->ps_shader || !rctx->vs_shader)
652 return;
653
654 si_update_derived_state(rctx);
655 si_constant_buffer_update(rctx);
656 si_vertex_buffer_update(rctx);
657
658 if (info->indexed) {
659 /* Initialize the index buffer struct. */
660 pipe_resource_reference(&ib.buffer, rctx->index_buffer.buffer);
661 ib.user_buffer = rctx->index_buffer.user_buffer;
662 ib.index_size = rctx->index_buffer.index_size;
663 ib.offset = rctx->index_buffer.offset + info->start * ib.index_size;
664
665 /* Translate or upload, if needed. */
666 r600_translate_index_buffer(rctx, &ib, info->count);
667
668 if (ib.user_buffer && !ib.buffer) {
669 r600_upload_index_buffer(rctx, &ib, info->count);
670 }
671
672 } else if (info->count_from_stream_output) {
673 r600_context_draw_opaque_count(rctx, (struct r600_so_target*)info->count_from_stream_output);
674 }
675
676 rctx->vs_shader_so_strides = rctx->vs_shader->current->so_strides;
677
678 if (!si_update_draw_info_state(rctx, info))
679 return;
680
681 si_state_draw(rctx, info, &ib);
682
683 cp_coher_cntl = si_pm4_sync_flags(rctx);
684 if (cp_coher_cntl) {
685 struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx);
686
687 if (pm4 == NULL)
688 return;
689
690 si_cmd_surface_sync(pm4, cp_coher_cntl);
691 si_pm4_set_state(rctx, sync, pm4);
692 }
693
694 if (rctx->flush_and_inv_cb_meta) {
695 struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx);
696
697 if (pm4 == NULL)
698 return;
699
700 si_cmd_flush_and_inv_cb_meta(pm4);
701 si_pm4_set_state(rctx, flush_and_inv_cb_meta, pm4);
702 rctx->flush_and_inv_cb_meta = false;
703 }
704
705 /* Emit states. */
706 rctx->pm4_dirty_cdwords += si_pm4_dirty_dw(rctx);
707
708 si_need_cs_space(rctx, 0, TRUE);
709
710 for (i = 0; i < SI_NUM_ATOMS(rctx); i++) {
711 if (rctx->atoms.array[i]->dirty) {
712 rctx->atoms.array[i]->emit(rctx, rctx->atoms.array[i]);
713 rctx->atoms.array[i]->dirty = false;
714 }
715 }
716
717 si_pm4_emit_dirty(rctx);
718 rctx->pm4_dirty_cdwords = 0;
719
720 #if R600_TRACE_CS
721 if (rctx->screen->trace_bo) {
722 r600_trace_emit(rctx);
723 }
724 #endif
725
726 #if 0
727 /* Enable stream out if needed. */
728 if (rctx->streamout_start) {
729 r600_context_streamout_begin(rctx);
730 rctx->streamout_start = FALSE;
731 }
732 #endif
733
734 rctx->flags |= R600_CONTEXT_DST_CACHES_DIRTY;
735
736 /* Set the depth buffer as dirty. */
737 if (rctx->framebuffer.zsbuf) {
738 struct pipe_surface *surf = rctx->framebuffer.zsbuf;
739 struct r600_texture *rtex = (struct r600_texture *)surf->texture;
740
741 rtex->dirty_level_mask |= 1 << surf->u.tex.level;
742 }
743 if (rctx->fb_compressed_cb_mask) {
744 struct pipe_surface *surf;
745 struct r600_texture *rtex;
746 unsigned mask = rctx->fb_compressed_cb_mask;
747
748 do {
749 unsigned i = u_bit_scan(&mask);
750 surf = rctx->framebuffer.cbufs[i];
751 rtex = (struct r600_texture*)surf->texture;
752
753 rtex->dirty_level_mask |= 1 << surf->u.tex.level;
754 } while (mask);
755 }
756
757 pipe_resource_reference(&ib.buffer, NULL);
758 }