2 * Copyright 2012 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 * Christian König <christian.koenig@amd.com>
28 #include "si_shader.h"
29 #include "radeon/r600_cs.h"
32 #include "util/u_format.h"
33 #include "util/u_index_modify.h"
34 #include "util/u_memory.h"
35 #include "util/u_prim.h"
36 #include "util/u_upload_mgr.h"
42 static void si_pipe_shader_es(struct pipe_context
*ctx
, struct si_pipe_shader
*shader
)
44 struct si_context
*sctx
= (struct si_context
*)ctx
;
45 struct si_pm4_state
*pm4
;
46 unsigned num_sgprs
, num_user_sgprs
;
47 unsigned vgpr_comp_cnt
;
50 si_pm4_delete_state(sctx
, es
, shader
->pm4
);
51 pm4
= shader
->pm4
= si_pm4_alloc_state(sctx
);
56 va
= shader
->bo
->gpu_address
;
57 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_SHADER_DATA
);
59 vgpr_comp_cnt
= shader
->shader
.uses_instanceid
? 3 : 0;
61 num_user_sgprs
= SI_VS_NUM_USER_SGPR
;
62 num_sgprs
= shader
->num_sgprs
;
63 /* One SGPR after user SGPRs is pre-loaded with es2gs_offset */
64 if ((num_user_sgprs
+ 1) > num_sgprs
) {
65 /* Last 2 reserved SGPRs are used for VCC */
66 num_sgprs
= num_user_sgprs
+ 1 + 2;
68 assert(num_sgprs
<= 104);
70 si_pm4_set_reg(pm4
, R_00B320_SPI_SHADER_PGM_LO_ES
, va
>> 8);
71 si_pm4_set_reg(pm4
, R_00B324_SPI_SHADER_PGM_HI_ES
, va
>> 40);
72 si_pm4_set_reg(pm4
, R_00B328_SPI_SHADER_PGM_RSRC1_ES
,
73 S_00B328_VGPRS((shader
->num_vgprs
- 1) / 4) |
74 S_00B328_SGPRS((num_sgprs
- 1) / 8) |
75 S_00B328_VGPR_COMP_CNT(vgpr_comp_cnt
));
76 si_pm4_set_reg(pm4
, R_00B32C_SPI_SHADER_PGM_RSRC2_ES
,
77 S_00B32C_USER_SGPR(num_user_sgprs
));
79 sctx
->b
.flags
|= R600_CONTEXT_INV_SHADER_CACHE
;
82 static void si_pipe_shader_gs(struct pipe_context
*ctx
, struct si_pipe_shader
*shader
)
84 struct si_context
*sctx
= (struct si_context
*)ctx
;
85 unsigned gs_vert_itemsize
= shader
->shader
.noutput
* (16 >> 2);
86 unsigned gs_max_vert_out
= shader
->shader
.gs_max_out_vertices
;
87 unsigned gsvs_itemsize
= gs_vert_itemsize
* gs_max_vert_out
;
89 struct si_pm4_state
*pm4
;
90 unsigned num_sgprs
, num_user_sgprs
;
93 /* The GSVS_RING_ITEMSIZE register takes 15 bits */
94 assert(gsvs_itemsize
< (1 << 15));
96 si_pm4_delete_state(sctx
, gs
, shader
->pm4
);
97 pm4
= shader
->pm4
= si_pm4_alloc_state(sctx
);
102 if (gs_max_vert_out
<= 128) {
103 cut_mode
= V_028A40_GS_CUT_128
;
104 } else if (gs_max_vert_out
<= 256) {
105 cut_mode
= V_028A40_GS_CUT_256
;
106 } else if (gs_max_vert_out
<= 512) {
107 cut_mode
= V_028A40_GS_CUT_512
;
109 assert(gs_max_vert_out
<= 1024);
110 cut_mode
= V_028A40_GS_CUT_1024
;
113 si_pm4_set_reg(pm4
, R_028A40_VGT_GS_MODE
,
114 S_028A40_MODE(V_028A40_GS_SCENARIO_G
) |
115 S_028A40_CUT_MODE(cut_mode
)|
116 S_028A40_ES_WRITE_OPTIMIZE(1) |
117 S_028A40_GS_WRITE_OPTIMIZE(1));
119 si_pm4_set_reg(pm4
, R_028A60_VGT_GSVS_RING_OFFSET_1
, gsvs_itemsize
);
120 si_pm4_set_reg(pm4
, R_028A64_VGT_GSVS_RING_OFFSET_2
, gsvs_itemsize
);
121 si_pm4_set_reg(pm4
, R_028A68_VGT_GSVS_RING_OFFSET_3
, gsvs_itemsize
);
123 si_pm4_set_reg(pm4
, R_028AAC_VGT_ESGS_RING_ITEMSIZE
,
124 shader
->shader
.nparam
* (16 >> 2));
125 si_pm4_set_reg(pm4
, R_028AB0_VGT_GSVS_RING_ITEMSIZE
, gsvs_itemsize
);
127 si_pm4_set_reg(pm4
, R_028B38_VGT_GS_MAX_VERT_OUT
, gs_max_vert_out
);
129 si_pm4_set_reg(pm4
, R_028B5C_VGT_GS_VERT_ITEMSIZE
, gs_vert_itemsize
);
131 va
= shader
->bo
->gpu_address
;
132 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_SHADER_DATA
);
133 si_pm4_set_reg(pm4
, R_00B220_SPI_SHADER_PGM_LO_GS
, va
>> 8);
134 si_pm4_set_reg(pm4
, R_00B224_SPI_SHADER_PGM_HI_GS
, va
>> 40);
136 num_user_sgprs
= SI_GS_NUM_USER_SGPR
;
137 num_sgprs
= shader
->num_sgprs
;
138 /* Two SGPRs after user SGPRs are pre-loaded with gs2vs_offset, gs_wave_id */
139 if ((num_user_sgprs
+ 2) > num_sgprs
) {
140 /* Last 2 reserved SGPRs are used for VCC */
141 num_sgprs
= num_user_sgprs
+ 2 + 2;
143 assert(num_sgprs
<= 104);
145 si_pm4_set_reg(pm4
, R_00B228_SPI_SHADER_PGM_RSRC1_GS
,
146 S_00B228_VGPRS((shader
->num_vgprs
- 1) / 4) |
147 S_00B228_SGPRS((num_sgprs
- 1) / 8));
148 si_pm4_set_reg(pm4
, R_00B22C_SPI_SHADER_PGM_RSRC2_GS
,
149 S_00B22C_USER_SGPR(num_user_sgprs
));
151 sctx
->b
.flags
|= R600_CONTEXT_INV_SHADER_CACHE
;
154 static void si_pipe_shader_vs(struct pipe_context
*ctx
, struct si_pipe_shader
*shader
)
156 struct si_context
*sctx
= (struct si_context
*)ctx
;
157 struct si_pm4_state
*pm4
;
158 unsigned num_sgprs
, num_user_sgprs
;
159 unsigned nparams
, i
, vgpr_comp_cnt
;
162 si_pm4_delete_state(sctx
, vs
, shader
->pm4
);
163 pm4
= shader
->pm4
= si_pm4_alloc_state(sctx
);
168 va
= shader
->bo
->gpu_address
;
169 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_SHADER_DATA
);
171 vgpr_comp_cnt
= shader
->shader
.uses_instanceid
? 3 : 0;
173 num_user_sgprs
= SI_VS_NUM_USER_SGPR
;
174 num_sgprs
= shader
->num_sgprs
;
175 if (num_user_sgprs
> num_sgprs
) {
176 /* Last 2 reserved SGPRs are used for VCC */
177 num_sgprs
= num_user_sgprs
+ 2;
179 assert(num_sgprs
<= 104);
181 /* Certain attributes (position, psize, etc.) don't count as params.
182 * VS is required to export at least one param and r600_shader_from_tgsi()
183 * takes care of adding a dummy export.
185 for (nparams
= 0, i
= 0 ; i
< shader
->shader
.noutput
; i
++) {
186 switch (shader
->shader
.output
[i
].name
) {
187 case TGSI_SEMANTIC_CLIPVERTEX
:
188 case TGSI_SEMANTIC_POSITION
:
189 case TGSI_SEMANTIC_PSIZE
:
198 si_pm4_set_reg(pm4
, R_0286C4_SPI_VS_OUT_CONFIG
,
199 S_0286C4_VS_EXPORT_COUNT(nparams
- 1));
201 si_pm4_set_reg(pm4
, R_02870C_SPI_SHADER_POS_FORMAT
,
202 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP
) |
203 S_02870C_POS1_EXPORT_FORMAT(shader
->shader
.nr_pos_exports
> 1 ?
204 V_02870C_SPI_SHADER_4COMP
:
205 V_02870C_SPI_SHADER_NONE
) |
206 S_02870C_POS2_EXPORT_FORMAT(shader
->shader
.nr_pos_exports
> 2 ?
207 V_02870C_SPI_SHADER_4COMP
:
208 V_02870C_SPI_SHADER_NONE
) |
209 S_02870C_POS3_EXPORT_FORMAT(shader
->shader
.nr_pos_exports
> 3 ?
210 V_02870C_SPI_SHADER_4COMP
:
211 V_02870C_SPI_SHADER_NONE
));
213 si_pm4_set_reg(pm4
, R_00B120_SPI_SHADER_PGM_LO_VS
, va
>> 8);
214 si_pm4_set_reg(pm4
, R_00B124_SPI_SHADER_PGM_HI_VS
, va
>> 40);
215 si_pm4_set_reg(pm4
, R_00B128_SPI_SHADER_PGM_RSRC1_VS
,
216 S_00B128_VGPRS((shader
->num_vgprs
- 1) / 4) |
217 S_00B128_SGPRS((num_sgprs
- 1) / 8) |
218 S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt
));
219 si_pm4_set_reg(pm4
, R_00B12C_SPI_SHADER_PGM_RSRC2_VS
,
220 S_00B12C_USER_SGPR(num_user_sgprs
) |
221 S_00B12C_SO_BASE0_EN(!!shader
->selector
->so
.stride
[0]) |
222 S_00B12C_SO_BASE1_EN(!!shader
->selector
->so
.stride
[1]) |
223 S_00B12C_SO_BASE2_EN(!!shader
->selector
->so
.stride
[2]) |
224 S_00B12C_SO_BASE3_EN(!!shader
->selector
->so
.stride
[3]) |
225 S_00B12C_SO_EN(!!shader
->selector
->so
.num_outputs
));
227 sctx
->b
.flags
|= R600_CONTEXT_INV_SHADER_CACHE
;
230 static void si_pipe_shader_ps(struct pipe_context
*ctx
, struct si_pipe_shader
*shader
)
232 struct si_context
*sctx
= (struct si_context
*)ctx
;
233 struct si_pm4_state
*pm4
;
234 unsigned i
, spi_ps_in_control
;
235 unsigned num_sgprs
, num_user_sgprs
;
236 unsigned spi_baryc_cntl
= 0, spi_ps_input_ena
;
239 si_pm4_delete_state(sctx
, ps
, shader
->pm4
);
240 pm4
= shader
->pm4
= si_pm4_alloc_state(sctx
);
245 for (i
= 0; i
< shader
->shader
.ninput
; i
++) {
246 switch (shader
->shader
.input
[i
].name
) {
247 case TGSI_SEMANTIC_POSITION
:
248 if (shader
->shader
.input
[i
].centroid
) {
249 /* SPI_BARYC_CNTL.POS_FLOAT_LOCATION
251 * 0 -> Position = pixel center (default)
252 * 1 -> Position = pixel centroid
253 * 2 -> Position = iterated sample number XXX:
254 * What does this mean?
256 spi_baryc_cntl
|= S_0286E0_POS_FLOAT_LOCATION(1);
259 case TGSI_SEMANTIC_FACE
:
264 spi_ps_in_control
= S_0286D8_NUM_INTERP(shader
->shader
.nparam
) |
265 S_0286D8_BC_OPTIMIZE_DISABLE(1);
267 si_pm4_set_reg(pm4
, R_0286E0_SPI_BARYC_CNTL
, spi_baryc_cntl
);
268 spi_ps_input_ena
= shader
->spi_ps_input_ena
;
269 /* we need to enable at least one of them, otherwise we hang the GPU */
270 assert(G_0286CC_PERSP_SAMPLE_ENA(spi_ps_input_ena
) ||
271 G_0286CC_PERSP_CENTER_ENA(spi_ps_input_ena
) ||
272 G_0286CC_PERSP_CENTROID_ENA(spi_ps_input_ena
) ||
273 G_0286CC_PERSP_PULL_MODEL_ENA(spi_ps_input_ena
) ||
274 G_0286CC_LINEAR_SAMPLE_ENA(spi_ps_input_ena
) ||
275 G_0286CC_LINEAR_CENTER_ENA(spi_ps_input_ena
) ||
276 G_0286CC_LINEAR_CENTROID_ENA(spi_ps_input_ena
) ||
277 G_0286CC_LINE_STIPPLE_TEX_ENA(spi_ps_input_ena
));
279 si_pm4_set_reg(pm4
, R_0286CC_SPI_PS_INPUT_ENA
, spi_ps_input_ena
);
280 si_pm4_set_reg(pm4
, R_0286D0_SPI_PS_INPUT_ADDR
, spi_ps_input_ena
);
281 si_pm4_set_reg(pm4
, R_0286D8_SPI_PS_IN_CONTROL
, spi_ps_in_control
);
283 si_pm4_set_reg(pm4
, R_028710_SPI_SHADER_Z_FORMAT
, shader
->spi_shader_z_format
);
284 si_pm4_set_reg(pm4
, R_028714_SPI_SHADER_COL_FORMAT
,
285 shader
->spi_shader_col_format
);
286 si_pm4_set_reg(pm4
, R_02823C_CB_SHADER_MASK
, shader
->cb_shader_mask
);
288 va
= shader
->bo
->gpu_address
;
289 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_SHADER_DATA
);
290 si_pm4_set_reg(pm4
, R_00B020_SPI_SHADER_PGM_LO_PS
, va
>> 8);
291 si_pm4_set_reg(pm4
, R_00B024_SPI_SHADER_PGM_HI_PS
, va
>> 40);
293 num_user_sgprs
= SI_PS_NUM_USER_SGPR
;
294 num_sgprs
= shader
->num_sgprs
;
295 /* One SGPR after user SGPRs is pre-loaded with {prim_mask, lds_offset} */
296 if ((num_user_sgprs
+ 1) > num_sgprs
) {
297 /* Last 2 reserved SGPRs are used for VCC */
298 num_sgprs
= num_user_sgprs
+ 1 + 2;
300 assert(num_sgprs
<= 104);
302 si_pm4_set_reg(pm4
, R_00B028_SPI_SHADER_PGM_RSRC1_PS
,
303 S_00B028_VGPRS((shader
->num_vgprs
- 1) / 4) |
304 S_00B028_SGPRS((num_sgprs
- 1) / 8));
305 si_pm4_set_reg(pm4
, R_00B02C_SPI_SHADER_PGM_RSRC2_PS
,
306 S_00B02C_EXTRA_LDS_SIZE(shader
->lds_size
) |
307 S_00B02C_USER_SGPR(num_user_sgprs
));
309 sctx
->b
.flags
|= R600_CONTEXT_INV_SHADER_CACHE
;
316 static unsigned si_conv_pipe_prim(unsigned pprim
)
318 static const unsigned prim_conv
[] = {
319 [PIPE_PRIM_POINTS
] = V_008958_DI_PT_POINTLIST
,
320 [PIPE_PRIM_LINES
] = V_008958_DI_PT_LINELIST
,
321 [PIPE_PRIM_LINE_LOOP
] = V_008958_DI_PT_LINELOOP
,
322 [PIPE_PRIM_LINE_STRIP
] = V_008958_DI_PT_LINESTRIP
,
323 [PIPE_PRIM_TRIANGLES
] = V_008958_DI_PT_TRILIST
,
324 [PIPE_PRIM_TRIANGLE_STRIP
] = V_008958_DI_PT_TRISTRIP
,
325 [PIPE_PRIM_TRIANGLE_FAN
] = V_008958_DI_PT_TRIFAN
,
326 [PIPE_PRIM_QUADS
] = V_008958_DI_PT_QUADLIST
,
327 [PIPE_PRIM_QUAD_STRIP
] = V_008958_DI_PT_QUADSTRIP
,
328 [PIPE_PRIM_POLYGON
] = V_008958_DI_PT_POLYGON
,
329 [PIPE_PRIM_LINES_ADJACENCY
] = V_008958_DI_PT_LINELIST_ADJ
,
330 [PIPE_PRIM_LINE_STRIP_ADJACENCY
] = V_008958_DI_PT_LINESTRIP_ADJ
,
331 [PIPE_PRIM_TRIANGLES_ADJACENCY
] = V_008958_DI_PT_TRILIST_ADJ
,
332 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY
] = V_008958_DI_PT_TRISTRIP_ADJ
,
333 [R600_PRIM_RECTANGLE_LIST
] = V_008958_DI_PT_RECTLIST
335 unsigned result
= prim_conv
[pprim
];
337 R600_ERR("unsupported primitive type %d\n", pprim
);
342 static unsigned si_conv_prim_to_gs_out(unsigned mode
)
344 static const int prim_conv
[] = {
345 [PIPE_PRIM_POINTS
] = V_028A6C_OUTPRIM_TYPE_POINTLIST
,
346 [PIPE_PRIM_LINES
] = V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
347 [PIPE_PRIM_LINE_LOOP
] = V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
348 [PIPE_PRIM_LINE_STRIP
] = V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
349 [PIPE_PRIM_TRIANGLES
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
350 [PIPE_PRIM_TRIANGLE_STRIP
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
351 [PIPE_PRIM_TRIANGLE_FAN
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
352 [PIPE_PRIM_QUADS
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
353 [PIPE_PRIM_QUAD_STRIP
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
354 [PIPE_PRIM_POLYGON
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
355 [PIPE_PRIM_LINES_ADJACENCY
] = V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
356 [PIPE_PRIM_LINE_STRIP_ADJACENCY
] = V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
357 [PIPE_PRIM_TRIANGLES_ADJACENCY
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
358 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
359 [R600_PRIM_RECTANGLE_LIST
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
361 assert(mode
< Elements(prim_conv
));
363 return prim_conv
[mode
];
366 static unsigned si_get_ia_multi_vgt_param(struct si_context
*sctx
,
367 const struct pipe_draw_info
*info
)
369 struct si_state_rasterizer
*rs
= sctx
->queued
.named
.rasterizer
;
370 unsigned prim
= info
->mode
;
371 unsigned primgroup_size
= 128; /* recommended without a GS */
373 /* SWITCH_ON_EOP(0) is always preferable. */
374 bool wd_switch_on_eop
= false;
375 bool ia_switch_on_eop
= false;
376 bool partial_vs_wave
= false;
379 primgroup_size
= 64; /* recommended with a GS */
381 /* This is a hardware requirement. */
382 if ((rs
&& rs
->line_stipple_enable
) ||
383 (sctx
->b
.screen
->debug_flags
& DBG_SWITCH_ON_EOP
)) {
384 ia_switch_on_eop
= true;
385 wd_switch_on_eop
= true;
388 if (sctx
->b
.streamout
.streamout_enabled
||
389 sctx
->b
.streamout
.prims_gen_query_enabled
)
390 partial_vs_wave
= true;
392 if (sctx
->b
.chip_class
>= CIK
) {
393 /* WD_SWITCH_ON_EOP has no effect on GPUs with less than
394 * 4 shader engines. Set 1 to pass the assertion below.
395 * The other cases are hardware requirements. */
396 if (sctx
->b
.screen
->info
.max_se
< 4 ||
397 prim
== PIPE_PRIM_POLYGON
||
398 prim
== PIPE_PRIM_LINE_LOOP
||
399 prim
== PIPE_PRIM_TRIANGLE_FAN
||
400 prim
== PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY
||
401 info
->primitive_restart
)
402 wd_switch_on_eop
= true;
404 /* Hawaii hangs if instancing is enabled and WD_SWITCH_ON_EOP is 0.
405 * We don't know that for indirect drawing, so treat it as
406 * always problematic. */
407 if (sctx
->b
.family
== CHIP_HAWAII
&&
408 (info
->indirect
|| info
->instance_count
> 1))
409 wd_switch_on_eop
= true;
411 /* If the WD switch is false, the IA switch must be false too. */
412 assert(wd_switch_on_eop
|| !ia_switch_on_eop
);
415 return S_028AA8_SWITCH_ON_EOP(ia_switch_on_eop
) |
416 S_028AA8_PARTIAL_VS_WAVE_ON(partial_vs_wave
) |
417 S_028AA8_PRIMGROUP_SIZE(primgroup_size
- 1) |
418 S_028AA8_WD_SWITCH_ON_EOP(sctx
->b
.chip_class
>= CIK
? wd_switch_on_eop
: 0);
421 static bool si_update_draw_info_state(struct si_context
*sctx
,
422 const struct pipe_draw_info
*info
,
423 const struct pipe_index_buffer
*ib
)
425 struct si_pm4_state
*pm4
= si_pm4_alloc_state(sctx
);
426 struct si_shader
*vs
= si_get_vs_state(sctx
);
427 unsigned prim
= si_conv_pipe_prim(info
->mode
);
428 unsigned gs_out_prim
=
429 si_conv_prim_to_gs_out(sctx
->gs_shader
?
430 sctx
->gs_shader
->current
->shader
.gs_output_prim
:
432 unsigned ls_mask
= 0;
433 unsigned ia_multi_vgt_param
= si_get_ia_multi_vgt_param(sctx
, info
);
443 if (sctx
->b
.chip_class
>= CIK
) {
444 si_pm4_set_reg(pm4
, R_028B74_VGT_DISPATCH_DRAW_INDEX
,
445 ib
->index_size
== 4 ? 0xFC000000 : 0xFC00);
447 si_pm4_cmd_begin(pm4
, PKT3_DRAW_PREAMBLE
);
448 si_pm4_cmd_add(pm4
, prim
); /* VGT_PRIMITIVE_TYPE */
449 si_pm4_cmd_add(pm4
, ia_multi_vgt_param
); /* IA_MULTI_VGT_PARAM */
450 si_pm4_cmd_add(pm4
, 0); /* VGT_LS_HS_CONFIG */
451 si_pm4_cmd_end(pm4
, false);
453 si_pm4_set_reg(pm4
, R_008958_VGT_PRIMITIVE_TYPE
, prim
);
454 si_pm4_set_reg(pm4
, R_028AA8_IA_MULTI_VGT_PARAM
, ia_multi_vgt_param
);
457 si_pm4_set_reg(pm4
, R_028A6C_VGT_GS_OUT_PRIM_TYPE
, gs_out_prim
);
458 si_pm4_set_reg(pm4
, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX
, info
->restart_index
);
459 si_pm4_set_reg(pm4
, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN
, info
->primitive_restart
);
461 if (prim
== V_008958_DI_PT_LINELIST
)
463 else if (prim
== V_008958_DI_PT_LINESTRIP
)
465 si_pm4_set_reg(pm4
, R_028A0C_PA_SC_LINE_STIPPLE
,
466 S_028A0C_AUTO_RESET_CNTL(ls_mask
) |
467 sctx
->pa_sc_line_stipple
);
469 if (info
->mode
== PIPE_PRIM_QUADS
|| info
->mode
== PIPE_PRIM_QUAD_STRIP
|| info
->mode
== PIPE_PRIM_POLYGON
) {
470 si_pm4_set_reg(pm4
, R_028814_PA_SU_SC_MODE_CNTL
,
471 S_028814_PROVOKING_VTX_LAST(1) | sctx
->pa_su_sc_mode_cntl
);
473 si_pm4_set_reg(pm4
, R_028814_PA_SU_SC_MODE_CNTL
, sctx
->pa_su_sc_mode_cntl
);
475 si_pm4_set_reg(pm4
, R_02881C_PA_CL_VS_OUT_CNTL
,
476 S_02881C_USE_VTX_POINT_SIZE(vs
->vs_out_point_size
) |
477 S_02881C_USE_VTX_EDGE_FLAG(vs
->vs_out_edgeflag
) |
478 S_02881C_USE_VTX_RENDER_TARGET_INDX(vs
->vs_out_layer
) |
479 S_02881C_VS_OUT_CCDIST0_VEC_ENA((vs
->clip_dist_write
& 0x0F) != 0) |
480 S_02881C_VS_OUT_CCDIST1_VEC_ENA((vs
->clip_dist_write
& 0xF0) != 0) |
481 S_02881C_VS_OUT_MISC_VEC_ENA(vs
->vs_out_misc_write
) |
482 (sctx
->queued
.named
.rasterizer
->clip_plane_enable
&
483 vs
->clip_dist_write
));
484 si_pm4_set_reg(pm4
, R_028810_PA_CL_CLIP_CNTL
,
485 sctx
->queued
.named
.rasterizer
->pa_cl_clip_cntl
|
486 (vs
->clip_dist_write
? 0 :
487 sctx
->queued
.named
.rasterizer
->clip_plane_enable
& 0x3F));
489 si_pm4_set_state(sctx
, draw_info
, pm4
);
493 static void si_update_spi_map(struct si_context
*sctx
)
495 struct si_shader
*ps
= &sctx
->ps_shader
->current
->shader
;
496 struct si_shader
*vs
= si_get_vs_state(sctx
);
497 struct si_pm4_state
*pm4
= si_pm4_alloc_state(sctx
);
500 for (i
= 0; i
< ps
->ninput
; i
++) {
501 unsigned name
= ps
->input
[i
].name
;
502 unsigned param_offset
= ps
->input
[i
].param_offset
;
504 if (name
== TGSI_SEMANTIC_POSITION
)
505 /* Read from preloaded VGPRs, not parameters */
511 if (ps
->input
[i
].interpolate
== TGSI_INTERPOLATE_CONSTANT
||
512 (ps
->input
[i
].interpolate
== TGSI_INTERPOLATE_COLOR
&&
513 sctx
->ps_shader
->current
->key
.ps
.flatshade
)) {
514 tmp
|= S_028644_FLAT_SHADE(1);
517 if (name
== TGSI_SEMANTIC_GENERIC
&&
518 sctx
->sprite_coord_enable
& (1 << ps
->input
[i
].sid
)) {
519 tmp
|= S_028644_PT_SPRITE_TEX(1);
522 for (j
= 0; j
< vs
->noutput
; j
++) {
523 if (name
== vs
->output
[j
].name
&&
524 ps
->input
[i
].sid
== vs
->output
[j
].sid
) {
525 tmp
|= S_028644_OFFSET(vs
->output
[j
].param_offset
);
530 if (j
== vs
->noutput
) {
531 /* No corresponding output found, load defaults into input */
532 tmp
|= S_028644_OFFSET(0x20);
536 R_028644_SPI_PS_INPUT_CNTL_0
+ param_offset
* 4,
539 if (name
== TGSI_SEMANTIC_COLOR
&&
540 sctx
->ps_shader
->current
->key
.ps
.color_two_side
) {
541 name
= TGSI_SEMANTIC_BCOLOR
;
547 si_pm4_set_state(sctx
, spi
, pm4
);
550 /* Initialize state related to ESGS / GSVS ring buffers */
551 static void si_init_gs_rings(struct si_context
*sctx
)
553 unsigned size
= 128 * 1024;
555 assert(!sctx
->gs_rings
);
556 sctx
->gs_rings
= si_pm4_alloc_state(sctx
);
558 sctx
->esgs_ring
.buffer
=
559 pipe_buffer_create(sctx
->b
.b
.screen
, PIPE_BIND_CUSTOM
,
560 PIPE_USAGE_DEFAULT
, size
);
561 sctx
->esgs_ring
.buffer_size
= size
;
563 size
= 64 * 1024 * 1024;
564 sctx
->gsvs_ring
.buffer
=
565 pipe_buffer_create(sctx
->b
.b
.screen
, PIPE_BIND_CUSTOM
,
566 PIPE_USAGE_DEFAULT
, size
);
567 sctx
->gsvs_ring
.buffer_size
= size
;
569 if (sctx
->b
.chip_class
>= CIK
) {
570 si_pm4_set_reg(sctx
->gs_rings
, R_030900_VGT_ESGS_RING_SIZE
,
571 sctx
->esgs_ring
.buffer_size
/ 256);
572 si_pm4_set_reg(sctx
->gs_rings
, R_030904_VGT_GSVS_RING_SIZE
,
573 sctx
->gsvs_ring
.buffer_size
/ 256);
575 si_pm4_set_reg(sctx
->gs_rings
, R_0088C8_VGT_ESGS_RING_SIZE
,
576 sctx
->esgs_ring
.buffer_size
/ 256);
577 si_pm4_set_reg(sctx
->gs_rings
, R_0088CC_VGT_GSVS_RING_SIZE
,
578 sctx
->gsvs_ring
.buffer_size
/ 256);
581 si_set_ring_buffer(&sctx
->b
.b
, PIPE_SHADER_VERTEX
, SI_RING_ESGS
,
582 &sctx
->esgs_ring
, 0, sctx
->esgs_ring
.buffer_size
,
584 si_set_ring_buffer(&sctx
->b
.b
, PIPE_SHADER_GEOMETRY
, SI_RING_ESGS
,
585 &sctx
->esgs_ring
, 0, sctx
->esgs_ring
.buffer_size
,
587 si_set_ring_buffer(&sctx
->b
.b
, PIPE_SHADER_VERTEX
, SI_RING_GSVS
,
588 &sctx
->gsvs_ring
, 0, sctx
->gsvs_ring
.buffer_size
,
592 static void si_update_derived_state(struct si_context
*sctx
)
594 struct pipe_context
* ctx
= (struct pipe_context
*)sctx
;
596 if (!sctx
->blitter
->running
) {
597 /* Flush depth textures which need to be flushed. */
598 for (int i
= 0; i
< SI_NUM_SHADERS
; i
++) {
599 if (sctx
->samplers
[i
].depth_texture_mask
) {
600 si_flush_depth_textures(sctx
, &sctx
->samplers
[i
]);
602 if (sctx
->samplers
[i
].compressed_colortex_mask
) {
603 si_decompress_color_textures(sctx
, &sctx
->samplers
[i
]);
608 if (sctx
->gs_shader
) {
609 si_shader_select(ctx
, sctx
->gs_shader
);
611 if (!sctx
->gs_shader
->current
->pm4
) {
612 si_pipe_shader_gs(ctx
, sctx
->gs_shader
->current
);
613 si_pipe_shader_vs(ctx
,
614 sctx
->gs_shader
->current
->gs_copy_shader
);
617 si_pm4_bind_state(sctx
, gs
, sctx
->gs_shader
->current
->pm4
);
618 si_pm4_bind_state(sctx
, vs
, sctx
->gs_shader
->current
->gs_copy_shader
->pm4
);
620 sctx
->b
.streamout
.stride_in_dw
= sctx
->gs_shader
->so
.stride
;
622 si_shader_select(ctx
, sctx
->vs_shader
);
624 if (!sctx
->vs_shader
->current
->pm4
)
625 si_pipe_shader_es(ctx
, sctx
->vs_shader
->current
);
627 si_pm4_bind_state(sctx
, es
, sctx
->vs_shader
->current
->pm4
);
630 si_init_gs_rings(sctx
);
631 if (sctx
->emitted
.named
.gs_rings
!= sctx
->gs_rings
)
632 sctx
->b
.flags
|= R600_CONTEXT_VGT_FLUSH
;
633 si_pm4_bind_state(sctx
, gs_rings
, sctx
->gs_rings
);
635 si_set_ring_buffer(ctx
, PIPE_SHADER_GEOMETRY
, SI_RING_GSVS
,
637 sctx
->gs_shader
->current
->shader
.gs_max_out_vertices
*
638 sctx
->gs_shader
->current
->shader
.noutput
* 16,
639 64, true, true, 4, 16);
642 sctx
->gs_on
= si_pm4_alloc_state(sctx
);
644 si_pm4_set_reg(sctx
->gs_on
, R_028B54_VGT_SHADER_STAGES_EN
,
645 S_028B54_ES_EN(V_028B54_ES_STAGE_REAL
) |
647 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER
));
649 si_pm4_bind_state(sctx
, gs_onoff
, sctx
->gs_on
);
651 si_shader_select(ctx
, sctx
->vs_shader
);
653 if (!sctx
->vs_shader
->current
->pm4
)
654 si_pipe_shader_vs(ctx
, sctx
->vs_shader
->current
);
656 si_pm4_bind_state(sctx
, vs
, sctx
->vs_shader
->current
->pm4
);
658 sctx
->b
.streamout
.stride_in_dw
= sctx
->vs_shader
->so
.stride
;
661 sctx
->gs_off
= si_pm4_alloc_state(sctx
);
663 si_pm4_set_reg(sctx
->gs_off
, R_028A40_VGT_GS_MODE
, 0);
664 si_pm4_set_reg(sctx
->gs_off
, R_028B54_VGT_SHADER_STAGES_EN
, 0);
666 si_pm4_bind_state(sctx
, gs_onoff
, sctx
->gs_off
);
667 si_pm4_bind_state(sctx
, gs_rings
, NULL
);
668 si_pm4_bind_state(sctx
, gs
, NULL
);
669 si_pm4_bind_state(sctx
, es
, NULL
);
672 si_shader_select(ctx
, sctx
->ps_shader
);
674 if (!sctx
->ps_shader
->current
->pm4
)
675 si_pipe_shader_ps(ctx
, sctx
->ps_shader
->current
);
677 si_pm4_bind_state(sctx
, ps
, sctx
->ps_shader
->current
->pm4
);
679 if (si_pm4_state_changed(sctx
, ps
) || si_pm4_state_changed(sctx
, vs
)) {
680 /* XXX: Emitting the PS state even when only the VS changed
681 * fixes random failures with piglit glsl-max-varyings.
684 sctx
->emitted
.named
.ps
= NULL
;
685 si_update_spi_map(sctx
);
688 if (sctx
->ps_db_shader_control
!= sctx
->ps_shader
->current
->db_shader_control
) {
689 sctx
->ps_db_shader_control
= sctx
->ps_shader
->current
->db_shader_control
;
690 sctx
->db_render_state
.dirty
= true;
694 static void si_state_draw(struct si_context
*sctx
,
695 const struct pipe_draw_info
*info
,
696 const struct pipe_index_buffer
*ib
)
698 unsigned sh_base_reg
= (sctx
->gs_shader
? R_00B330_SPI_SHADER_USER_DATA_ES_0
:
699 R_00B130_SPI_SHADER_USER_DATA_VS_0
);
700 struct si_pm4_state
*pm4
= si_pm4_alloc_state(sctx
);
705 if (info
->count_from_stream_output
) {
706 struct r600_so_target
*t
=
707 (struct r600_so_target
*)info
->count_from_stream_output
;
708 uint64_t va
= t
->buf_filled_size
->gpu_address
+
709 t
->buf_filled_size_offset
;
711 si_pm4_set_reg(pm4
, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE
,
714 si_pm4_cmd_begin(pm4
, PKT3_COPY_DATA
);
716 COPY_DATA_SRC_SEL(COPY_DATA_MEM
) |
717 COPY_DATA_DST_SEL(COPY_DATA_REG
) |
718 COPY_DATA_WR_CONFIRM
);
719 si_pm4_cmd_add(pm4
, va
); /* src address lo */
720 si_pm4_cmd_add(pm4
, va
>> 32UL); /* src address hi */
721 si_pm4_cmd_add(pm4
, R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE
>> 2);
722 si_pm4_cmd_add(pm4
, 0); /* unused */
723 si_pm4_add_bo(pm4
, t
->buf_filled_size
, RADEON_USAGE_READ
,
725 si_pm4_cmd_end(pm4
, true);
729 si_pm4_cmd_begin(pm4
, PKT3_INDEX_TYPE
);
730 if (ib
->index_size
== 4) {
731 si_pm4_cmd_add(pm4
, V_028A7C_VGT_INDEX_32
| (SI_BIG_ENDIAN
?
732 V_028A7C_VGT_DMA_SWAP_32_BIT
: 0));
734 si_pm4_cmd_add(pm4
, V_028A7C_VGT_INDEX_16
| (SI_BIG_ENDIAN
?
735 V_028A7C_VGT_DMA_SWAP_16_BIT
: 0));
737 si_pm4_cmd_end(pm4
, sctx
->b
.predicate_drawing
);
739 if (!info
->indirect
) {
740 si_pm4_cmd_begin(pm4
, PKT3_NUM_INSTANCES
);
741 si_pm4_cmd_add(pm4
, info
->instance_count
);
742 si_pm4_cmd_end(pm4
, sctx
->b
.predicate_drawing
);
744 si_pm4_set_reg(pm4
, sh_base_reg
+ SI_SGPR_BASE_VERTEX
* 4,
745 info
->indexed
? info
->index_bias
: info
->start
);
746 si_pm4_set_reg(pm4
, sh_base_reg
+ SI_SGPR_START_INSTANCE
* 4,
747 info
->start_instance
);
749 si_pm4_add_bo(pm4
, (struct r600_resource
*)info
->indirect
,
750 RADEON_USAGE_READ
, RADEON_PRIO_MIN
);
754 uint32_t max_size
= (ib
->buffer
->width0
- ib
->offset
) /
755 sctx
->index_buffer
.index_size
;
756 uint64_t va
= r600_resource(ib
->buffer
)->gpu_address
+ ib
->offset
;
758 si_pm4_add_bo(pm4
, (struct r600_resource
*)ib
->buffer
, RADEON_USAGE_READ
,
761 if (info
->indirect
) {
762 uint64_t indirect_va
= r600_resource(info
->indirect
)->gpu_address
;
763 si_cmd_draw_index_indirect(pm4
, indirect_va
, va
, max_size
,
764 info
->indirect_offset
,
765 sh_base_reg
+ SI_SGPR_BASE_VERTEX
* 4,
766 sh_base_reg
+ SI_SGPR_START_INSTANCE
* 4,
767 sctx
->b
.predicate_drawing
);
769 va
+= info
->start
* ib
->index_size
;
770 si_cmd_draw_index_2(pm4
, max_size
, va
, info
->count
,
771 V_0287F0_DI_SRC_SEL_DMA
,
772 sctx
->b
.predicate_drawing
);
775 if (info
->indirect
) {
776 uint64_t indirect_va
= r600_resource(info
->indirect
)->gpu_address
;
777 si_cmd_draw_indirect(pm4
, indirect_va
, info
->indirect_offset
,
778 sh_base_reg
+ SI_SGPR_BASE_VERTEX
* 4,
779 sh_base_reg
+ SI_SGPR_START_INSTANCE
* 4,
780 sctx
->b
.predicate_drawing
);
782 si_cmd_draw_index_auto(pm4
, info
->count
,
783 V_0287F0_DI_SRC_SEL_AUTO_INDEX
|
784 S_0287F0_USE_OPAQUE(!!info
->count_from_stream_output
),
785 sctx
->b
.predicate_drawing
);
789 si_pm4_set_state(sctx
, draw
, pm4
);
792 void si_emit_cache_flush(struct r600_common_context
*sctx
, struct r600_atom
*atom
)
794 struct radeon_winsys_cs
*cs
= sctx
->rings
.gfx
.cs
;
795 uint32_t cp_coher_cntl
= 0;
797 /* XXX SI flushes both ICACHE and KCACHE if either flag is set.
798 * XXX CIK shouldn't have this issue. Test CIK before separating the flags
799 * XXX to ensure there is no regression. Also find out if there is another
800 * XXX way to flush either ICACHE or KCACHE but not both for SI. */
801 if (sctx
->flags
& (R600_CONTEXT_INV_SHADER_CACHE
|
802 R600_CONTEXT_INV_CONST_CACHE
)) {
803 cp_coher_cntl
|= S_0085F0_SH_ICACHE_ACTION_ENA(1) |
804 S_0085F0_SH_KCACHE_ACTION_ENA(1);
806 if (sctx
->flags
& (R600_CONTEXT_INV_TEX_CACHE
|
807 R600_CONTEXT_STREAMOUT_FLUSH
)) {
808 cp_coher_cntl
|= S_0085F0_TC_ACTION_ENA(1) |
809 S_0085F0_TCL1_ACTION_ENA(1);
811 if (sctx
->flags
& R600_CONTEXT_FLUSH_AND_INV_CB
) {
812 cp_coher_cntl
|= S_0085F0_CB_ACTION_ENA(1) |
813 S_0085F0_CB0_DEST_BASE_ENA(1) |
814 S_0085F0_CB1_DEST_BASE_ENA(1) |
815 S_0085F0_CB2_DEST_BASE_ENA(1) |
816 S_0085F0_CB3_DEST_BASE_ENA(1) |
817 S_0085F0_CB4_DEST_BASE_ENA(1) |
818 S_0085F0_CB5_DEST_BASE_ENA(1) |
819 S_0085F0_CB6_DEST_BASE_ENA(1) |
820 S_0085F0_CB7_DEST_BASE_ENA(1);
822 if (sctx
->flags
& R600_CONTEXT_FLUSH_AND_INV_DB
) {
823 cp_coher_cntl
|= S_0085F0_DB_ACTION_ENA(1) |
824 S_0085F0_DB_DEST_BASE_ENA(1);
828 if (sctx
->chip_class
>= CIK
) {
829 radeon_emit(cs
, PKT3(PKT3_ACQUIRE_MEM
, 5, 0));
830 radeon_emit(cs
, cp_coher_cntl
); /* CP_COHER_CNTL */
831 radeon_emit(cs
, 0xffffffff); /* CP_COHER_SIZE */
832 radeon_emit(cs
, 0xff); /* CP_COHER_SIZE_HI */
833 radeon_emit(cs
, 0); /* CP_COHER_BASE */
834 radeon_emit(cs
, 0); /* CP_COHER_BASE_HI */
835 radeon_emit(cs
, 0x0000000A); /* POLL_INTERVAL */
837 radeon_emit(cs
, PKT3(PKT3_SURFACE_SYNC
, 3, 0));
838 radeon_emit(cs
, cp_coher_cntl
); /* CP_COHER_CNTL */
839 radeon_emit(cs
, 0xffffffff); /* CP_COHER_SIZE */
840 radeon_emit(cs
, 0); /* CP_COHER_BASE */
841 radeon_emit(cs
, 0x0000000A); /* POLL_INTERVAL */
845 if (sctx
->flags
& R600_CONTEXT_FLUSH_AND_INV_CB_META
) {
846 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
847 radeon_emit(cs
, EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_META
) | EVENT_INDEX(0));
849 if (sctx
->flags
& R600_CONTEXT_FLUSH_AND_INV_DB_META
) {
850 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
851 radeon_emit(cs
, EVENT_TYPE(V_028A90_FLUSH_AND_INV_DB_META
) | EVENT_INDEX(0));
854 if (sctx
->flags
& (R600_CONTEXT_WAIT_3D_IDLE
|
855 R600_CONTEXT_PS_PARTIAL_FLUSH
)) {
856 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
857 radeon_emit(cs
, EVENT_TYPE(V_028A90_PS_PARTIAL_FLUSH
) | EVENT_INDEX(4));
858 } else if (sctx
->flags
& R600_CONTEXT_STREAMOUT_FLUSH
) {
859 /* Needed if streamout buffers are going to be used as a source. */
860 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
861 radeon_emit(cs
, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH
) | EVENT_INDEX(4));
864 if (sctx
->flags
& R600_CONTEXT_VGT_FLUSH
) {
865 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
866 radeon_emit(cs
, EVENT_TYPE(V_028A90_VGT_FLUSH
) | EVENT_INDEX(0));
868 if (sctx
->flags
& R600_CONTEXT_VGT_STREAMOUT_SYNC
) {
869 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
870 radeon_emit(cs
, EVENT_TYPE(V_028A90_VGT_STREAMOUT_SYNC
) | EVENT_INDEX(0));
876 const struct r600_atom si_atom_cache_flush
= { si_emit_cache_flush
, 17 }; /* number of CS dwords */
878 static void si_get_draw_start_count(struct si_context
*sctx
,
879 const struct pipe_draw_info
*info
,
880 unsigned *start
, unsigned *count
)
882 if (info
->indirect
) {
883 struct r600_resource
*indirect
=
884 (struct r600_resource
*)info
->indirect
;
885 int *data
= r600_buffer_map_sync_with_rings(&sctx
->b
,
886 indirect
, PIPE_TRANSFER_READ
);
887 data
+= info
->indirect_offset
/sizeof(int);
891 *start
= info
->start
;
892 *count
= info
->count
;
896 void si_draw_vbo(struct pipe_context
*ctx
, const struct pipe_draw_info
*info
)
898 struct si_context
*sctx
= (struct si_context
*)ctx
;
899 struct pipe_index_buffer ib
= {};
902 if (!info
->count
&& !info
->indirect
&&
903 (info
->indexed
|| !info
->count_from_stream_output
))
906 if (!sctx
->ps_shader
|| !sctx
->vs_shader
)
909 si_update_derived_state(sctx
);
911 if (sctx
->vertex_buffers_dirty
) {
912 si_update_vertex_buffers(sctx
);
913 sctx
->vertex_buffers_dirty
= false;
917 /* Initialize the index buffer struct. */
918 pipe_resource_reference(&ib
.buffer
, sctx
->index_buffer
.buffer
);
919 ib
.user_buffer
= sctx
->index_buffer
.user_buffer
;
920 ib
.index_size
= sctx
->index_buffer
.index_size
;
921 ib
.offset
= sctx
->index_buffer
.offset
;
923 /* Translate or upload, if needed. */
924 if (ib
.index_size
== 1) {
925 struct pipe_resource
*out_buffer
= NULL
;
926 unsigned out_offset
, start
, count
, start_offset
;
929 si_get_draw_start_count(sctx
, info
, &start
, &count
);
930 start_offset
= start
* ib
.index_size
;
932 u_upload_alloc(sctx
->b
.uploader
, start_offset
, count
* 2,
933 &out_offset
, &out_buffer
, &ptr
);
935 util_shorten_ubyte_elts_to_userptr(&sctx
->b
.b
, &ib
, 0,
936 ib
.offset
+ start_offset
,
939 pipe_resource_reference(&ib
.buffer
, NULL
);
940 ib
.user_buffer
= NULL
;
941 ib
.buffer
= out_buffer
;
942 /* info->start will be added by the drawing code */
943 ib
.offset
= out_offset
- start_offset
;
945 } else if (ib
.user_buffer
&& !ib
.buffer
) {
946 unsigned start
, count
, start_offset
;
948 si_get_draw_start_count(sctx
, info
, &start
, &count
);
949 start_offset
= start
* ib
.index_size
;
951 u_upload_data(sctx
->b
.uploader
, start_offset
, count
* ib
.index_size
,
952 (char*)ib
.user_buffer
+ start_offset
,
953 &ib
.offset
, &ib
.buffer
);
954 /* info->start will be added by the drawing code */
955 ib
.offset
-= start_offset
;
959 if (!si_update_draw_info_state(sctx
, info
, &ib
))
962 si_state_draw(sctx
, info
, &ib
);
964 sctx
->pm4_dirty_cdwords
+= si_pm4_dirty_dw(sctx
);
966 /* Check flush flags. */
968 sctx
->atoms
.s
.cache_flush
->dirty
= true;
970 si_need_cs_space(sctx
, 0, TRUE
);
973 for (i
= 0; i
< SI_NUM_ATOMS(sctx
); i
++) {
974 if (sctx
->atoms
.array
[i
]->dirty
) {
975 sctx
->atoms
.array
[i
]->emit(&sctx
->b
, sctx
->atoms
.array
[i
]);
976 sctx
->atoms
.array
[i
]->dirty
= false;
980 si_pm4_emit_dirty(sctx
);
981 sctx
->pm4_dirty_cdwords
= 0;
984 if (sctx
->screen
->b
.trace_bo
) {
989 /* Workaround for a VGT hang when streamout is enabled.
990 * It must be done after drawing. */
991 if (sctx
->b
.family
== CHIP_HAWAII
&&
992 (sctx
->b
.streamout
.streamout_enabled
||
993 sctx
->b
.streamout
.prims_gen_query_enabled
)) {
994 sctx
->b
.flags
|= R600_CONTEXT_VGT_STREAMOUT_SYNC
;
997 /* Set the depth buffer as dirty. */
998 if (sctx
->framebuffer
.state
.zsbuf
) {
999 struct pipe_surface
*surf
= sctx
->framebuffer
.state
.zsbuf
;
1000 struct r600_texture
*rtex
= (struct r600_texture
*)surf
->texture
;
1002 rtex
->dirty_level_mask
|= 1 << surf
->u
.tex
.level
;
1004 if (sctx
->framebuffer
.compressed_cb_mask
) {
1005 struct pipe_surface
*surf
;
1006 struct r600_texture
*rtex
;
1007 unsigned mask
= sctx
->framebuffer
.compressed_cb_mask
;
1010 unsigned i
= u_bit_scan(&mask
);
1011 surf
= sctx
->framebuffer
.state
.cbufs
[i
];
1012 rtex
= (struct r600_texture
*)surf
->texture
;
1014 rtex
->dirty_level_mask
|= 1 << surf
->u
.tex
.level
;
1018 pipe_resource_reference(&ib
.buffer
, NULL
);
1019 sctx
->b
.num_draw_calls
++;