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626ba9533f44375b8a8494eb0a44fbf46ce019a6
[mesa.git] / src / gallium / drivers / radeonsi / si_state_draw.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Christian König <christian.koenig@amd.com>
25 */
26
27 #include "util/u_memory.h"
28 #include "util/u_framebuffer.h"
29 #include "util/u_blitter.h"
30 #include "tgsi/tgsi_parse.h"
31 #include "radeonsi_pipe.h"
32 #include "radeonsi_shader.h"
33 #include "si_state.h"
34 #include "../radeon/r600_cs.h"
35 #include "sid.h"
36
37 /*
38 * Shaders
39 */
40
41 static void si_pipe_shader_vs(struct pipe_context *ctx, struct si_pipe_shader *shader)
42 {
43 struct r600_context *rctx = (struct r600_context *)ctx;
44 struct si_pm4_state *pm4;
45 unsigned num_sgprs, num_user_sgprs;
46 unsigned nparams, i, vgpr_comp_cnt;
47 uint64_t va;
48
49 si_pm4_delete_state(rctx, vs, shader->pm4);
50 pm4 = shader->pm4 = si_pm4_alloc_state(rctx);
51
52 if (pm4 == NULL)
53 return;
54
55 /* Certain attributes (position, psize, etc.) don't count as params.
56 * VS is required to export at least one param and r600_shader_from_tgsi()
57 * takes care of adding a dummy export.
58 */
59 for (nparams = 0, i = 0 ; i < shader->shader.noutput; i++) {
60 switch (shader->shader.output[i].name) {
61 case TGSI_SEMANTIC_CLIPVERTEX:
62 case TGSI_SEMANTIC_POSITION:
63 case TGSI_SEMANTIC_PSIZE:
64 break;
65 default:
66 nparams++;
67 }
68 }
69 if (nparams < 1)
70 nparams = 1;
71
72 si_pm4_set_reg(pm4, R_0286C4_SPI_VS_OUT_CONFIG,
73 S_0286C4_VS_EXPORT_COUNT(nparams - 1));
74
75 si_pm4_set_reg(pm4, R_02870C_SPI_SHADER_POS_FORMAT,
76 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
77 S_02870C_POS1_EXPORT_FORMAT(shader->shader.nr_pos_exports > 1 ?
78 V_02870C_SPI_SHADER_4COMP :
79 V_02870C_SPI_SHADER_NONE) |
80 S_02870C_POS2_EXPORT_FORMAT(shader->shader.nr_pos_exports > 2 ?
81 V_02870C_SPI_SHADER_4COMP :
82 V_02870C_SPI_SHADER_NONE) |
83 S_02870C_POS3_EXPORT_FORMAT(shader->shader.nr_pos_exports > 3 ?
84 V_02870C_SPI_SHADER_4COMP :
85 V_02870C_SPI_SHADER_NONE));
86
87 va = r600_resource_va(ctx->screen, (void *)shader->bo);
88 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ);
89 si_pm4_set_reg(pm4, R_00B120_SPI_SHADER_PGM_LO_VS, va >> 8);
90 si_pm4_set_reg(pm4, R_00B124_SPI_SHADER_PGM_HI_VS, va >> 40);
91
92 num_user_sgprs = SI_VS_NUM_USER_SGPR;
93 num_sgprs = shader->num_sgprs;
94 if (num_user_sgprs > num_sgprs) {
95 /* Last 2 reserved SGPRs are used for VCC */
96 num_sgprs = num_user_sgprs + 2;
97 }
98 assert(num_sgprs <= 104);
99
100 vgpr_comp_cnt = shader->shader.uses_instanceid ? 3 : 0;
101
102 si_pm4_set_reg(pm4, R_00B128_SPI_SHADER_PGM_RSRC1_VS,
103 S_00B128_VGPRS((shader->num_vgprs - 1) / 4) |
104 S_00B128_SGPRS((num_sgprs - 1) / 8) |
105 S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt));
106 si_pm4_set_reg(pm4, R_00B12C_SPI_SHADER_PGM_RSRC2_VS,
107 S_00B12C_USER_SGPR(num_user_sgprs) |
108 S_00B12C_SO_BASE0_EN(!!shader->selector->so.stride[0]) |
109 S_00B12C_SO_BASE1_EN(!!shader->selector->so.stride[1]) |
110 S_00B12C_SO_BASE2_EN(!!shader->selector->so.stride[2]) |
111 S_00B12C_SO_BASE3_EN(!!shader->selector->so.stride[3]) |
112 S_00B12C_SO_EN(!!shader->selector->so.num_outputs));
113
114 if (rctx->b.chip_class >= CIK) {
115 si_pm4_set_reg(pm4, R_00B118_SPI_SHADER_PGM_RSRC3_VS,
116 S_00B118_CU_EN(0xffff));
117 si_pm4_set_reg(pm4, R_00B11C_SPI_SHADER_LATE_ALLOC_VS,
118 S_00B11C_LIMIT(0));
119 }
120
121 si_pm4_bind_state(rctx, vs, shader->pm4);
122 rctx->b.flags |= R600_CONTEXT_INV_SHADER_CACHE;
123 }
124
125 static void si_pipe_shader_ps(struct pipe_context *ctx, struct si_pipe_shader *shader)
126 {
127 struct r600_context *rctx = (struct r600_context *)ctx;
128 struct si_pm4_state *pm4;
129 unsigned i, exports_ps, num_cout, spi_ps_in_control, db_shader_control;
130 unsigned num_sgprs, num_user_sgprs;
131 unsigned spi_baryc_cntl = 0, spi_ps_input_ena, spi_shader_z_format;
132 uint64_t va;
133
134 si_pm4_delete_state(rctx, ps, shader->pm4);
135 pm4 = shader->pm4 = si_pm4_alloc_state(rctx);
136
137 if (pm4 == NULL)
138 return;
139
140 db_shader_control = S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z) |
141 S_02880C_ALPHA_TO_MASK_DISABLE(rctx->fb_cb0_is_integer);
142
143 for (i = 0; i < shader->shader.ninput; i++) {
144 switch (shader->shader.input[i].name) {
145 case TGSI_SEMANTIC_POSITION:
146 if (shader->shader.input[i].centroid) {
147 /* SPI_BARYC_CNTL.POS_FLOAT_LOCATION
148 * Possible vaules:
149 * 0 -> Position = pixel center (default)
150 * 1 -> Position = pixel centroid
151 * 2 -> Position = iterated sample number XXX:
152 * What does this mean?
153 */
154 spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(1);
155 }
156 /* Fall through */
157 case TGSI_SEMANTIC_FACE:
158 continue;
159 }
160 }
161
162 for (i = 0; i < shader->shader.noutput; i++) {
163 if (shader->shader.output[i].name == TGSI_SEMANTIC_POSITION)
164 db_shader_control |= S_02880C_Z_EXPORT_ENABLE(1);
165 if (shader->shader.output[i].name == TGSI_SEMANTIC_STENCIL)
166 db_shader_control |= S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(1);
167 }
168 if (shader->shader.uses_kill || shader->key.ps.alpha_func != PIPE_FUNC_ALWAYS)
169 db_shader_control |= S_02880C_KILL_ENABLE(1);
170
171 exports_ps = 0;
172 num_cout = 0;
173 for (i = 0; i < shader->shader.noutput; i++) {
174 if (shader->shader.output[i].name == TGSI_SEMANTIC_POSITION ||
175 shader->shader.output[i].name == TGSI_SEMANTIC_STENCIL)
176 exports_ps |= 1;
177 else if (shader->shader.output[i].name == TGSI_SEMANTIC_COLOR) {
178 if (shader->shader.fs_write_all)
179 num_cout = shader->shader.nr_cbufs;
180 else
181 num_cout++;
182 }
183 }
184 if (!exports_ps) {
185 /* always at least export 1 component per pixel */
186 exports_ps = 2;
187 }
188
189 spi_ps_in_control = S_0286D8_NUM_INTERP(shader->shader.ninterp) |
190 S_0286D8_BC_OPTIMIZE_DISABLE(1);
191
192 si_pm4_set_reg(pm4, R_0286E0_SPI_BARYC_CNTL, spi_baryc_cntl);
193 spi_ps_input_ena = shader->spi_ps_input_ena;
194 /* we need to enable at least one of them, otherwise we hang the GPU */
195 assert(G_0286CC_PERSP_SAMPLE_ENA(spi_ps_input_ena) ||
196 G_0286CC_PERSP_CENTER_ENA(spi_ps_input_ena) ||
197 G_0286CC_PERSP_CENTROID_ENA(spi_ps_input_ena) ||
198 G_0286CC_PERSP_PULL_MODEL_ENA(spi_ps_input_ena) ||
199 G_0286CC_LINEAR_SAMPLE_ENA(spi_ps_input_ena) ||
200 G_0286CC_LINEAR_CENTER_ENA(spi_ps_input_ena) ||
201 G_0286CC_LINEAR_CENTROID_ENA(spi_ps_input_ena) ||
202 G_0286CC_LINE_STIPPLE_TEX_ENA(spi_ps_input_ena));
203
204 si_pm4_set_reg(pm4, R_0286CC_SPI_PS_INPUT_ENA, spi_ps_input_ena);
205 si_pm4_set_reg(pm4, R_0286D0_SPI_PS_INPUT_ADDR, spi_ps_input_ena);
206 si_pm4_set_reg(pm4, R_0286D8_SPI_PS_IN_CONTROL, spi_ps_in_control);
207
208 if (G_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(db_shader_control))
209 spi_shader_z_format = V_028710_SPI_SHADER_32_GR;
210 else if (G_02880C_Z_EXPORT_ENABLE(db_shader_control))
211 spi_shader_z_format = V_028710_SPI_SHADER_32_R;
212 else
213 spi_shader_z_format = 0;
214 si_pm4_set_reg(pm4, R_028710_SPI_SHADER_Z_FORMAT, spi_shader_z_format);
215 si_pm4_set_reg(pm4, R_028714_SPI_SHADER_COL_FORMAT,
216 shader->spi_shader_col_format);
217 si_pm4_set_reg(pm4, R_02823C_CB_SHADER_MASK, shader->cb_shader_mask);
218
219 va = r600_resource_va(ctx->screen, (void *)shader->bo);
220 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ);
221 si_pm4_set_reg(pm4, R_00B020_SPI_SHADER_PGM_LO_PS, va >> 8);
222 si_pm4_set_reg(pm4, R_00B024_SPI_SHADER_PGM_HI_PS, va >> 40);
223
224 num_user_sgprs = SI_PS_NUM_USER_SGPR;
225 num_sgprs = shader->num_sgprs;
226 /* One SGPR after user SGPRs is pre-loaded with {prim_mask, lds_offset} */
227 if ((num_user_sgprs + 1) > num_sgprs) {
228 /* Last 2 reserved SGPRs are used for VCC */
229 num_sgprs = num_user_sgprs + 1 + 2;
230 }
231 assert(num_sgprs <= 104);
232
233 si_pm4_set_reg(pm4, R_00B028_SPI_SHADER_PGM_RSRC1_PS,
234 S_00B028_VGPRS((shader->num_vgprs - 1) / 4) |
235 S_00B028_SGPRS((num_sgprs - 1) / 8));
236 si_pm4_set_reg(pm4, R_00B02C_SPI_SHADER_PGM_RSRC2_PS,
237 S_00B02C_EXTRA_LDS_SIZE(shader->lds_size) |
238 S_00B02C_USER_SGPR(num_user_sgprs));
239 if (rctx->b.chip_class >= CIK) {
240 si_pm4_set_reg(pm4, R_00B01C_SPI_SHADER_PGM_RSRC3_PS,
241 S_00B01C_CU_EN(0xffff));
242 }
243
244 si_pm4_set_reg(pm4, R_02880C_DB_SHADER_CONTROL, db_shader_control);
245
246 shader->cb0_is_integer = rctx->fb_cb0_is_integer;
247 shader->sprite_coord_enable = rctx->sprite_coord_enable;
248 si_pm4_bind_state(rctx, ps, shader->pm4);
249 rctx->b.flags |= R600_CONTEXT_INV_SHADER_CACHE;
250 }
251
252 /*
253 * Drawing
254 */
255
256 static unsigned si_conv_pipe_prim(unsigned pprim)
257 {
258 static const unsigned prim_conv[] = {
259 [PIPE_PRIM_POINTS] = V_008958_DI_PT_POINTLIST,
260 [PIPE_PRIM_LINES] = V_008958_DI_PT_LINELIST,
261 [PIPE_PRIM_LINE_LOOP] = V_008958_DI_PT_LINELOOP,
262 [PIPE_PRIM_LINE_STRIP] = V_008958_DI_PT_LINESTRIP,
263 [PIPE_PRIM_TRIANGLES] = V_008958_DI_PT_TRILIST,
264 [PIPE_PRIM_TRIANGLE_STRIP] = V_008958_DI_PT_TRISTRIP,
265 [PIPE_PRIM_TRIANGLE_FAN] = V_008958_DI_PT_TRIFAN,
266 [PIPE_PRIM_QUADS] = V_008958_DI_PT_QUADLIST,
267 [PIPE_PRIM_QUAD_STRIP] = V_008958_DI_PT_QUADSTRIP,
268 [PIPE_PRIM_POLYGON] = V_008958_DI_PT_POLYGON,
269 [PIPE_PRIM_LINES_ADJACENCY] = ~0,
270 [PIPE_PRIM_LINE_STRIP_ADJACENCY] = ~0,
271 [PIPE_PRIM_TRIANGLES_ADJACENCY] = ~0,
272 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY] = ~0
273 };
274 unsigned result = prim_conv[pprim];
275 if (result == ~0) {
276 R600_ERR("unsupported primitive type %d\n", pprim);
277 }
278 return result;
279 }
280
281 static unsigned r600_conv_prim_to_gs_out(unsigned mode)
282 {
283 static const int prim_conv[] = {
284 [PIPE_PRIM_POINTS] = V_028A6C_OUTPRIM_TYPE_POINTLIST,
285 [PIPE_PRIM_LINES] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
286 [PIPE_PRIM_LINE_LOOP] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
287 [PIPE_PRIM_LINE_STRIP] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
288 [PIPE_PRIM_TRIANGLES] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
289 [PIPE_PRIM_TRIANGLE_STRIP] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
290 [PIPE_PRIM_TRIANGLE_FAN] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
291 [PIPE_PRIM_QUADS] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
292 [PIPE_PRIM_QUAD_STRIP] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
293 [PIPE_PRIM_POLYGON] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
294 [PIPE_PRIM_LINES_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
295 [PIPE_PRIM_LINE_STRIP_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
296 [PIPE_PRIM_TRIANGLES_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
297 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
298 };
299 assert(mode < Elements(prim_conv));
300
301 return prim_conv[mode];
302 }
303
304 static bool si_update_draw_info_state(struct r600_context *rctx,
305 const struct pipe_draw_info *info,
306 const struct pipe_index_buffer *ib)
307 {
308 struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx);
309 struct si_shader *vs = &rctx->vs_shader->current->shader;
310 unsigned prim = si_conv_pipe_prim(info->mode);
311 unsigned gs_out_prim = r600_conv_prim_to_gs_out(info->mode);
312 unsigned ls_mask = 0;
313
314 if (pm4 == NULL)
315 return false;
316
317 if (prim == ~0) {
318 FREE(pm4);
319 return false;
320 }
321
322 if (rctx->b.chip_class >= CIK) {
323 bool wd_switch_on_eop = prim == V_008958_DI_PT_POLYGON ||
324 prim == V_008958_DI_PT_LINELOOP ||
325 prim == V_008958_DI_PT_TRIFAN ||
326 prim == V_008958_DI_PT_TRISTRIP_ADJ ||
327 info->primitive_restart;
328
329 si_pm4_set_reg(pm4, R_028AA8_IA_MULTI_VGT_PARAM,
330 S_028AA8_SWITCH_ON_EOP(1) |
331 S_028AA8_PARTIAL_VS_WAVE_ON(1) |
332 S_028AA8_PRIMGROUP_SIZE(63) |
333 S_028AA8_WD_SWITCH_ON_EOP(wd_switch_on_eop));
334 si_pm4_set_reg(pm4, R_028B74_VGT_DISPATCH_DRAW_INDEX,
335 ib->index_size == 4 ? 0xFC000000 : 0xFC00);
336
337 si_pm4_set_reg(pm4, R_030908_VGT_PRIMITIVE_TYPE, prim);
338 } else {
339 si_pm4_set_reg(pm4, R_008958_VGT_PRIMITIVE_TYPE, prim);
340 }
341
342 si_pm4_set_reg(pm4, R_028A6C_VGT_GS_OUT_PRIM_TYPE, gs_out_prim);
343 si_pm4_set_reg(pm4, R_028400_VGT_MAX_VTX_INDX, ~0);
344 si_pm4_set_reg(pm4, R_028404_VGT_MIN_VTX_INDX, 0);
345 si_pm4_set_reg(pm4, R_028408_VGT_INDX_OFFSET,
346 info->indexed ? info->index_bias : info->start);
347 si_pm4_set_reg(pm4, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, info->restart_index);
348 si_pm4_set_reg(pm4, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, info->primitive_restart);
349 si_pm4_set_reg(pm4, R_00B130_SPI_SHADER_USER_DATA_VS_0 + SI_SGPR_START_INSTANCE * 4,
350 info->start_instance);
351
352 if (prim == V_008958_DI_PT_LINELIST)
353 ls_mask = 1;
354 else if (prim == V_008958_DI_PT_LINESTRIP)
355 ls_mask = 2;
356 si_pm4_set_reg(pm4, R_028A0C_PA_SC_LINE_STIPPLE,
357 S_028A0C_AUTO_RESET_CNTL(ls_mask) |
358 rctx->pa_sc_line_stipple);
359
360 if (info->mode == PIPE_PRIM_QUADS || info->mode == PIPE_PRIM_QUAD_STRIP || info->mode == PIPE_PRIM_POLYGON) {
361 si_pm4_set_reg(pm4, R_028814_PA_SU_SC_MODE_CNTL,
362 S_028814_PROVOKING_VTX_LAST(1) | rctx->pa_su_sc_mode_cntl);
363 } else {
364 si_pm4_set_reg(pm4, R_028814_PA_SU_SC_MODE_CNTL, rctx->pa_su_sc_mode_cntl);
365 }
366 si_pm4_set_reg(pm4, R_02881C_PA_CL_VS_OUT_CNTL,
367 S_02881C_USE_VTX_POINT_SIZE(vs->vs_out_point_size) |
368 S_02881C_VS_OUT_CCDIST0_VEC_ENA((vs->clip_dist_write & 0x0F) != 0) |
369 S_02881C_VS_OUT_CCDIST1_VEC_ENA((vs->clip_dist_write & 0xF0) != 0) |
370 S_02881C_VS_OUT_MISC_VEC_ENA(vs->vs_out_misc_write) |
371 (rctx->queued.named.rasterizer->clip_plane_enable &
372 vs->clip_dist_write));
373 si_pm4_set_reg(pm4, R_028810_PA_CL_CLIP_CNTL,
374 rctx->queued.named.rasterizer->pa_cl_clip_cntl |
375 (vs->clip_dist_write ? 0 :
376 rctx->queued.named.rasterizer->clip_plane_enable & 0x3F));
377
378 si_pm4_set_state(rctx, draw_info, pm4);
379 return true;
380 }
381
382 static void si_update_spi_map(struct r600_context *rctx)
383 {
384 struct si_shader *ps = &rctx->ps_shader->current->shader;
385 struct si_shader *vs = &rctx->vs_shader->current->shader;
386 struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx);
387 unsigned i, j, tmp;
388
389 for (i = 0; i < ps->ninput; i++) {
390 unsigned name = ps->input[i].name;
391 unsigned param_offset = ps->input[i].param_offset;
392
393 if (name == TGSI_SEMANTIC_POSITION)
394 /* Read from preloaded VGPRs, not parameters */
395 continue;
396
397 bcolor:
398 tmp = 0;
399
400 if (ps->input[i].interpolate == TGSI_INTERPOLATE_CONSTANT ||
401 (ps->input[i].interpolate == TGSI_INTERPOLATE_COLOR &&
402 rctx->ps_shader->current->key.ps.flatshade)) {
403 tmp |= S_028644_FLAT_SHADE(1);
404 }
405
406 if (name == TGSI_SEMANTIC_GENERIC &&
407 rctx->sprite_coord_enable & (1 << ps->input[i].sid)) {
408 tmp |= S_028644_PT_SPRITE_TEX(1);
409 }
410
411 for (j = 0; j < vs->noutput; j++) {
412 if (name == vs->output[j].name &&
413 ps->input[i].sid == vs->output[j].sid) {
414 tmp |= S_028644_OFFSET(vs->output[j].param_offset);
415 break;
416 }
417 }
418
419 if (j == vs->noutput) {
420 /* No corresponding output found, load defaults into input */
421 tmp |= S_028644_OFFSET(0x20);
422 }
423
424 si_pm4_set_reg(pm4,
425 R_028644_SPI_PS_INPUT_CNTL_0 + param_offset * 4,
426 tmp);
427
428 if (name == TGSI_SEMANTIC_COLOR &&
429 rctx->ps_shader->current->key.ps.color_two_side) {
430 name = TGSI_SEMANTIC_BCOLOR;
431 param_offset++;
432 goto bcolor;
433 }
434 }
435
436 si_pm4_set_state(rctx, spi, pm4);
437 }
438
439 static void si_update_derived_state(struct r600_context *rctx)
440 {
441 struct pipe_context * ctx = (struct pipe_context*)rctx;
442 unsigned vs_dirty = 0, ps_dirty = 0;
443
444 if (!rctx->blitter->running) {
445 /* Flush depth textures which need to be flushed. */
446 for (int i = 0; i < SI_NUM_SHADERS; i++) {
447 if (rctx->samplers[i].depth_texture_mask) {
448 si_flush_depth_textures(rctx, &rctx->samplers[i]);
449 }
450 if (rctx->samplers[i].compressed_colortex_mask) {
451 r600_decompress_color_textures(rctx, &rctx->samplers[i]);
452 }
453 }
454 }
455
456 si_shader_select(ctx, rctx->vs_shader, &vs_dirty);
457
458 if (!rctx->vs_shader->current->pm4) {
459 si_pipe_shader_vs(ctx, rctx->vs_shader->current);
460 vs_dirty = 0;
461 }
462
463 if (vs_dirty) {
464 si_pm4_bind_state(rctx, vs, rctx->vs_shader->current->pm4);
465 }
466
467
468 si_shader_select(ctx, rctx->ps_shader, &ps_dirty);
469
470 if (!rctx->ps_shader->current->pm4) {
471 si_pipe_shader_ps(ctx, rctx->ps_shader->current);
472 ps_dirty = 0;
473 }
474 if (!rctx->ps_shader->current->bo) {
475 if (!rctx->dummy_pixel_shader->pm4)
476 si_pipe_shader_ps(ctx, rctx->dummy_pixel_shader);
477 else
478 si_pm4_bind_state(rctx, vs, rctx->dummy_pixel_shader->pm4);
479
480 ps_dirty = 0;
481 }
482 if (rctx->ps_shader->current->cb0_is_integer != rctx->fb_cb0_is_integer) {
483 si_pipe_shader_ps(ctx, rctx->ps_shader->current);
484 ps_dirty = 1;
485 }
486
487 if (ps_dirty) {
488 si_pm4_bind_state(rctx, ps, rctx->ps_shader->current->pm4);
489 }
490
491 if (si_pm4_state_changed(rctx, ps) || si_pm4_state_changed(rctx, vs)) {
492 /* XXX: Emitting the PS state even when only the VS changed
493 * fixes random failures with piglit glsl-max-varyings.
494 * Not sure why...
495 */
496 rctx->emitted.named.ps = NULL;
497 si_update_spi_map(rctx);
498 }
499 }
500
501 static void si_vertex_buffer_update(struct r600_context *rctx)
502 {
503 struct pipe_context *ctx = &rctx->b.b;
504 struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx);
505 bool bound[PIPE_MAX_ATTRIBS] = {};
506 unsigned i, count;
507 uint64_t va;
508
509 rctx->b.flags |= R600_CONTEXT_INV_TEX_CACHE;
510
511 count = rctx->vertex_elements->count;
512 assert(count <= 256 / 4);
513
514 si_pm4_sh_data_begin(pm4);
515 for (i = 0 ; i < count; i++) {
516 struct pipe_vertex_element *ve = &rctx->vertex_elements->elements[i];
517 struct pipe_vertex_buffer *vb;
518 struct r600_resource *rbuffer;
519 unsigned offset;
520
521 if (ve->vertex_buffer_index >= rctx->nr_vertex_buffers)
522 continue;
523
524 vb = &rctx->vertex_buffer[ve->vertex_buffer_index];
525 rbuffer = (struct r600_resource*)vb->buffer;
526 if (rbuffer == NULL)
527 continue;
528
529 offset = 0;
530 offset += vb->buffer_offset;
531 offset += ve->src_offset;
532
533 va = r600_resource_va(ctx->screen, (void*)rbuffer);
534 va += offset;
535
536 /* Fill in T# buffer resource description */
537 si_pm4_sh_data_add(pm4, va & 0xFFFFFFFF);
538 si_pm4_sh_data_add(pm4, (S_008F04_BASE_ADDRESS_HI(va >> 32) |
539 S_008F04_STRIDE(vb->stride)));
540 if (vb->stride)
541 /* Round up by rounding down and adding 1 */
542 si_pm4_sh_data_add(pm4,
543 (vb->buffer->width0 - offset -
544 util_format_get_blocksize(ve->src_format)) /
545 vb->stride + 1);
546 else
547 si_pm4_sh_data_add(pm4, vb->buffer->width0 - offset);
548 si_pm4_sh_data_add(pm4, rctx->vertex_elements->rsrc_word3[i]);
549
550 if (!bound[ve->vertex_buffer_index]) {
551 si_pm4_add_bo(pm4, rbuffer, RADEON_USAGE_READ);
552 bound[ve->vertex_buffer_index] = true;
553 }
554 }
555 si_pm4_sh_data_end(pm4, R_00B130_SPI_SHADER_USER_DATA_VS_0, SI_SGPR_VERTEX_BUFFER);
556 si_pm4_set_state(rctx, vertex_buffers, pm4);
557 }
558
559 static void si_state_draw(struct r600_context *rctx,
560 const struct pipe_draw_info *info,
561 const struct pipe_index_buffer *ib)
562 {
563 struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx);
564
565 if (pm4 == NULL)
566 return;
567
568 /* queries need some special values
569 * (this is non-zero if any query is active) */
570 if (rctx->num_cs_dw_nontimer_queries_suspend) {
571 struct si_state_dsa *dsa = rctx->queued.named.dsa;
572
573 si_pm4_set_reg(pm4, R_028004_DB_COUNT_CONTROL,
574 S_028004_PERFECT_ZPASS_COUNTS(1) |
575 S_028004_SAMPLE_RATE(rctx->fb_log_samples));
576 si_pm4_set_reg(pm4, R_02800C_DB_RENDER_OVERRIDE,
577 dsa->db_render_override |
578 S_02800C_NOOP_CULL_DISABLE(1));
579 }
580
581 if (info->count_from_stream_output) {
582 struct r600_so_target *t =
583 (struct r600_so_target*)info->count_from_stream_output;
584 uint64_t va = r600_resource_va(&rctx->screen->b.b,
585 &t->buf_filled_size->b.b);
586 va += t->buf_filled_size_offset;
587
588 si_pm4_set_reg(pm4, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE,
589 t->stride_in_dw);
590
591 si_pm4_cmd_begin(pm4, PKT3_COPY_DATA);
592 si_pm4_cmd_add(pm4,
593 COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
594 COPY_DATA_DST_SEL(COPY_DATA_REG) |
595 COPY_DATA_WR_CONFIRM);
596 si_pm4_cmd_add(pm4, va); /* src address lo */
597 si_pm4_cmd_add(pm4, va >> 32UL); /* src address hi */
598 si_pm4_cmd_add(pm4, R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE >> 2);
599 si_pm4_cmd_add(pm4, 0); /* unused */
600 si_pm4_add_bo(pm4, t->buf_filled_size, RADEON_USAGE_READ);
601 si_pm4_cmd_end(pm4, true);
602 }
603
604 /* draw packet */
605 si_pm4_cmd_begin(pm4, PKT3_INDEX_TYPE);
606 if (ib->index_size == 4) {
607 si_pm4_cmd_add(pm4, V_028A7C_VGT_INDEX_32 | (R600_BIG_ENDIAN ?
608 V_028A7C_VGT_DMA_SWAP_32_BIT : 0));
609 } else {
610 si_pm4_cmd_add(pm4, V_028A7C_VGT_INDEX_16 | (R600_BIG_ENDIAN ?
611 V_028A7C_VGT_DMA_SWAP_16_BIT : 0));
612 }
613 si_pm4_cmd_end(pm4, rctx->predicate_drawing);
614
615 si_pm4_cmd_begin(pm4, PKT3_NUM_INSTANCES);
616 si_pm4_cmd_add(pm4, info->instance_count);
617 si_pm4_cmd_end(pm4, rctx->predicate_drawing);
618
619 if (info->indexed) {
620 uint32_t max_size = (ib->buffer->width0 - ib->offset) /
621 rctx->index_buffer.index_size;
622 uint64_t va;
623 va = r600_resource_va(&rctx->screen->b.b, ib->buffer);
624 va += ib->offset;
625
626 si_pm4_add_bo(pm4, (struct r600_resource *)ib->buffer, RADEON_USAGE_READ);
627 si_cmd_draw_index_2(pm4, max_size, va, info->count,
628 V_0287F0_DI_SRC_SEL_DMA,
629 rctx->predicate_drawing);
630 } else {
631 uint32_t initiator = V_0287F0_DI_SRC_SEL_AUTO_INDEX;
632 initiator |= S_0287F0_USE_OPAQUE(!!info->count_from_stream_output);
633 si_cmd_draw_index_auto(pm4, info->count, initiator, rctx->predicate_drawing);
634 }
635 si_pm4_set_state(rctx, draw, pm4);
636 }
637
638 void si_emit_cache_flush(struct r600_common_context *rctx, struct r600_atom *atom)
639 {
640 struct radeon_winsys_cs *cs = rctx->rings.gfx.cs;
641 uint32_t cp_coher_cntl = 0;
642
643 /* XXX SI flushes both ICACHE and KCACHE if either flag is set.
644 * XXX CIK shouldn't have this issue. Test CIK before separating the flags
645 * XXX to ensure there is no regression. Also find out if there is another
646 * XXX way to flush either ICACHE or KCACHE but not both for SI. */
647 if (rctx->flags & (R600_CONTEXT_INV_SHADER_CACHE |
648 R600_CONTEXT_INV_CONST_CACHE)) {
649 cp_coher_cntl |= S_0085F0_SH_ICACHE_ACTION_ENA(1) |
650 S_0085F0_SH_KCACHE_ACTION_ENA(1);
651 }
652 if (rctx->flags & (R600_CONTEXT_INV_TEX_CACHE |
653 R600_CONTEXT_STREAMOUT_FLUSH)) {
654 cp_coher_cntl |= S_0085F0_TC_ACTION_ENA(1) |
655 S_0085F0_TCL1_ACTION_ENA(1);
656 }
657 if (rctx->flags & R600_CONTEXT_FLUSH_AND_INV_CB) {
658 cp_coher_cntl |= S_0085F0_CB_ACTION_ENA(1) |
659 S_0085F0_CB0_DEST_BASE_ENA(1) |
660 S_0085F0_CB1_DEST_BASE_ENA(1) |
661 S_0085F0_CB2_DEST_BASE_ENA(1) |
662 S_0085F0_CB3_DEST_BASE_ENA(1) |
663 S_0085F0_CB4_DEST_BASE_ENA(1) |
664 S_0085F0_CB5_DEST_BASE_ENA(1) |
665 S_0085F0_CB6_DEST_BASE_ENA(1) |
666 S_0085F0_CB7_DEST_BASE_ENA(1);
667 }
668 if (rctx->flags & R600_CONTEXT_FLUSH_AND_INV_DB) {
669 cp_coher_cntl |= S_0085F0_DB_ACTION_ENA(1) |
670 S_0085F0_DB_DEST_BASE_ENA(1);
671 }
672
673 if (cp_coher_cntl) {
674 if (rctx->chip_class >= CIK) {
675 radeon_emit(cs, PKT3(PKT3_ACQUIRE_MEM, 5, 0));
676 radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */
677 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
678 radeon_emit(cs, 0xff); /* CP_COHER_SIZE_HI */
679 radeon_emit(cs, 0); /* CP_COHER_BASE */
680 radeon_emit(cs, 0); /* CP_COHER_BASE_HI */
681 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
682 } else {
683 radeon_emit(cs, PKT3(PKT3_SURFACE_SYNC, 3, 0));
684 radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */
685 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
686 radeon_emit(cs, 0); /* CP_COHER_BASE */
687 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
688 }
689 }
690
691 if (rctx->flags & R600_CONTEXT_FLUSH_AND_INV_CB_META) {
692 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
693 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_META) | EVENT_INDEX(0));
694 }
695
696 if (rctx->flags & R600_CONTEXT_WAIT_3D_IDLE) {
697 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
698 radeon_emit(cs, EVENT_TYPE(V_028A90_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
699 } else if (rctx->flags & R600_CONTEXT_STREAMOUT_FLUSH) {
700 /* Needed if streamout buffers are going to be used as a source. */
701 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
702 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
703 }
704
705 rctx->flags = 0;
706 }
707
708 const struct r600_atom si_atom_cache_flush = { si_emit_cache_flush, 11 }; /* number of CS dwords */
709
710 void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info)
711 {
712 struct r600_context *rctx = (struct r600_context *)ctx;
713 struct pipe_index_buffer ib = {};
714 uint32_t i;
715
716 if (!info->count && (info->indexed || !info->count_from_stream_output))
717 return;
718
719 if (!rctx->ps_shader || !rctx->vs_shader)
720 return;
721
722 si_update_derived_state(rctx);
723 si_vertex_buffer_update(rctx);
724
725 if (info->indexed) {
726 /* Initialize the index buffer struct. */
727 pipe_resource_reference(&ib.buffer, rctx->index_buffer.buffer);
728 ib.user_buffer = rctx->index_buffer.user_buffer;
729 ib.index_size = rctx->index_buffer.index_size;
730 ib.offset = rctx->index_buffer.offset + info->start * ib.index_size;
731
732 /* Translate or upload, if needed. */
733 r600_translate_index_buffer(rctx, &ib, info->count);
734
735 if (ib.user_buffer && !ib.buffer) {
736 r600_upload_index_buffer(rctx, &ib, info->count);
737 }
738 }
739
740 if (!si_update_draw_info_state(rctx, info, &ib))
741 return;
742
743 si_state_draw(rctx, info, &ib);
744
745 rctx->pm4_dirty_cdwords += si_pm4_dirty_dw(rctx);
746
747 /* Check flush flags. */
748 if (rctx->b.flags)
749 rctx->atoms.cache_flush->dirty = true;
750
751 si_need_cs_space(rctx, 0, TRUE);
752
753 /* Emit states. */
754 for (i = 0; i < SI_NUM_ATOMS(rctx); i++) {
755 if (rctx->atoms.array[i]->dirty) {
756 rctx->atoms.array[i]->emit(&rctx->b, rctx->atoms.array[i]);
757 rctx->atoms.array[i]->dirty = false;
758 }
759 }
760
761 si_pm4_emit_dirty(rctx);
762 rctx->pm4_dirty_cdwords = 0;
763
764 #if R600_TRACE_CS
765 if (rctx->screen->trace_bo) {
766 r600_trace_emit(rctx);
767 }
768 #endif
769
770 /* Set the depth buffer as dirty. */
771 if (rctx->framebuffer.zsbuf) {
772 struct pipe_surface *surf = rctx->framebuffer.zsbuf;
773 struct r600_texture *rtex = (struct r600_texture *)surf->texture;
774
775 rtex->dirty_level_mask |= 1 << surf->u.tex.level;
776 }
777 if (rctx->fb_compressed_cb_mask) {
778 struct pipe_surface *surf;
779 struct r600_texture *rtex;
780 unsigned mask = rctx->fb_compressed_cb_mask;
781
782 do {
783 unsigned i = u_bit_scan(&mask);
784 surf = rctx->framebuffer.cbufs[i];
785 rtex = (struct r600_texture*)surf->texture;
786
787 rtex->dirty_level_mask |= 1 << surf->u.tex.level;
788 } while (mask);
789 }
790
791 pipe_resource_reference(&ib.buffer, NULL);
792 }