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llvmpipe: Call pipe_thread_wait() on Linux.
[mesa.git] / src / gallium / drivers / radeonsi / si_state_draw.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Christian König <christian.koenig@amd.com>
25 */
26
27 #include "si_pipe.h"
28 #include "si_shader.h"
29 #include "radeon/r600_cs.h"
30 #include "sid.h"
31
32 #include "util/u_format.h"
33 #include "util/u_index_modify.h"
34 #include "util/u_memory.h"
35 #include "util/u_prim.h"
36 #include "util/u_upload_mgr.h"
37
38 /*
39 * Shaders
40 */
41
42 static void si_shader_es(struct si_shader *shader)
43 {
44 struct si_pm4_state *pm4;
45 unsigned num_sgprs, num_user_sgprs;
46 unsigned vgpr_comp_cnt;
47 uint64_t va;
48
49 pm4 = shader->pm4 = CALLOC_STRUCT(si_pm4_state);
50
51 if (pm4 == NULL)
52 return;
53
54 va = shader->bo->gpu_address;
55 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_DATA);
56
57 vgpr_comp_cnt = shader->uses_instanceid ? 3 : 0;
58
59 num_user_sgprs = SI_VS_NUM_USER_SGPR;
60 num_sgprs = shader->num_sgprs;
61 /* One SGPR after user SGPRs is pre-loaded with es2gs_offset */
62 if ((num_user_sgprs + 1) > num_sgprs) {
63 /* Last 2 reserved SGPRs are used for VCC */
64 num_sgprs = num_user_sgprs + 1 + 2;
65 }
66 assert(num_sgprs <= 104);
67
68 si_pm4_set_reg(pm4, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8);
69 si_pm4_set_reg(pm4, R_00B324_SPI_SHADER_PGM_HI_ES, va >> 40);
70 si_pm4_set_reg(pm4, R_00B328_SPI_SHADER_PGM_RSRC1_ES,
71 S_00B328_VGPRS((shader->num_vgprs - 1) / 4) |
72 S_00B328_SGPRS((num_sgprs - 1) / 8) |
73 S_00B328_VGPR_COMP_CNT(vgpr_comp_cnt));
74 si_pm4_set_reg(pm4, R_00B32C_SPI_SHADER_PGM_RSRC2_ES,
75 S_00B32C_USER_SGPR(num_user_sgprs));
76 }
77
78 static void si_shader_gs(struct si_shader *shader)
79 {
80 unsigned gs_vert_itemsize = shader->selector->info.num_outputs * (16 >> 2);
81 unsigned gs_max_vert_out = shader->selector->gs_max_out_vertices;
82 unsigned gsvs_itemsize = gs_vert_itemsize * gs_max_vert_out;
83 unsigned cut_mode;
84 struct si_pm4_state *pm4;
85 unsigned num_sgprs, num_user_sgprs;
86 uint64_t va;
87
88 /* The GSVS_RING_ITEMSIZE register takes 15 bits */
89 assert(gsvs_itemsize < (1 << 15));
90
91 pm4 = shader->pm4 = CALLOC_STRUCT(si_pm4_state);
92
93 if (pm4 == NULL)
94 return;
95
96 if (gs_max_vert_out <= 128) {
97 cut_mode = V_028A40_GS_CUT_128;
98 } else if (gs_max_vert_out <= 256) {
99 cut_mode = V_028A40_GS_CUT_256;
100 } else if (gs_max_vert_out <= 512) {
101 cut_mode = V_028A40_GS_CUT_512;
102 } else {
103 assert(gs_max_vert_out <= 1024);
104 cut_mode = V_028A40_GS_CUT_1024;
105 }
106
107 si_pm4_set_reg(pm4, R_028A40_VGT_GS_MODE,
108 S_028A40_MODE(V_028A40_GS_SCENARIO_G) |
109 S_028A40_CUT_MODE(cut_mode)|
110 S_028A40_ES_WRITE_OPTIMIZE(1) |
111 S_028A40_GS_WRITE_OPTIMIZE(1));
112
113 si_pm4_set_reg(pm4, R_028A60_VGT_GSVS_RING_OFFSET_1, gsvs_itemsize);
114 si_pm4_set_reg(pm4, R_028A64_VGT_GSVS_RING_OFFSET_2, gsvs_itemsize);
115 si_pm4_set_reg(pm4, R_028A68_VGT_GSVS_RING_OFFSET_3, gsvs_itemsize);
116
117 si_pm4_set_reg(pm4, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
118 util_bitcount64(shader->selector->gs_used_inputs) * (16 >> 2));
119 si_pm4_set_reg(pm4, R_028AB0_VGT_GSVS_RING_ITEMSIZE, gsvs_itemsize);
120
121 si_pm4_set_reg(pm4, R_028B38_VGT_GS_MAX_VERT_OUT, gs_max_vert_out);
122
123 si_pm4_set_reg(pm4, R_028B5C_VGT_GS_VERT_ITEMSIZE, gs_vert_itemsize);
124
125 va = shader->bo->gpu_address;
126 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_DATA);
127 si_pm4_set_reg(pm4, R_00B220_SPI_SHADER_PGM_LO_GS, va >> 8);
128 si_pm4_set_reg(pm4, R_00B224_SPI_SHADER_PGM_HI_GS, va >> 40);
129
130 num_user_sgprs = SI_GS_NUM_USER_SGPR;
131 num_sgprs = shader->num_sgprs;
132 /* Two SGPRs after user SGPRs are pre-loaded with gs2vs_offset, gs_wave_id */
133 if ((num_user_sgprs + 2) > num_sgprs) {
134 /* Last 2 reserved SGPRs are used for VCC */
135 num_sgprs = num_user_sgprs + 2 + 2;
136 }
137 assert(num_sgprs <= 104);
138
139 si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS,
140 S_00B228_VGPRS((shader->num_vgprs - 1) / 4) |
141 S_00B228_SGPRS((num_sgprs - 1) / 8));
142 si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS,
143 S_00B22C_USER_SGPR(num_user_sgprs));
144 }
145
146 static void si_shader_vs(struct si_shader *shader)
147 {
148 struct tgsi_shader_info *info = &shader->selector->info;
149 struct si_pm4_state *pm4;
150 unsigned num_sgprs, num_user_sgprs;
151 unsigned nparams, i, vgpr_comp_cnt;
152 uint64_t va;
153
154 pm4 = shader->pm4 = CALLOC_STRUCT(si_pm4_state);
155
156 if (pm4 == NULL)
157 return;
158
159 va = shader->bo->gpu_address;
160 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_DATA);
161
162 vgpr_comp_cnt = shader->uses_instanceid ? 3 : 0;
163
164 if (shader->is_gs_copy_shader)
165 num_user_sgprs = SI_GSCOPY_NUM_USER_SGPR;
166 else
167 num_user_sgprs = SI_VS_NUM_USER_SGPR;
168
169 num_sgprs = shader->num_sgprs;
170 if (num_user_sgprs > num_sgprs) {
171 /* Last 2 reserved SGPRs are used for VCC */
172 num_sgprs = num_user_sgprs + 2;
173 }
174 assert(num_sgprs <= 104);
175
176 /* Certain attributes (position, psize, etc.) don't count as params.
177 * VS is required to export at least one param and r600_shader_from_tgsi()
178 * takes care of adding a dummy export.
179 */
180 for (nparams = 0, i = 0 ; i < info->num_outputs; i++) {
181 switch (info->output_semantic_name[i]) {
182 case TGSI_SEMANTIC_CLIPVERTEX:
183 case TGSI_SEMANTIC_POSITION:
184 case TGSI_SEMANTIC_PSIZE:
185 break;
186 default:
187 nparams++;
188 }
189 }
190 if (nparams < 1)
191 nparams = 1;
192
193 si_pm4_set_reg(pm4, R_0286C4_SPI_VS_OUT_CONFIG,
194 S_0286C4_VS_EXPORT_COUNT(nparams - 1));
195
196 si_pm4_set_reg(pm4, R_02870C_SPI_SHADER_POS_FORMAT,
197 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
198 S_02870C_POS1_EXPORT_FORMAT(shader->nr_pos_exports > 1 ?
199 V_02870C_SPI_SHADER_4COMP :
200 V_02870C_SPI_SHADER_NONE) |
201 S_02870C_POS2_EXPORT_FORMAT(shader->nr_pos_exports > 2 ?
202 V_02870C_SPI_SHADER_4COMP :
203 V_02870C_SPI_SHADER_NONE) |
204 S_02870C_POS3_EXPORT_FORMAT(shader->nr_pos_exports > 3 ?
205 V_02870C_SPI_SHADER_4COMP :
206 V_02870C_SPI_SHADER_NONE));
207
208 si_pm4_set_reg(pm4, R_00B120_SPI_SHADER_PGM_LO_VS, va >> 8);
209 si_pm4_set_reg(pm4, R_00B124_SPI_SHADER_PGM_HI_VS, va >> 40);
210 si_pm4_set_reg(pm4, R_00B128_SPI_SHADER_PGM_RSRC1_VS,
211 S_00B128_VGPRS((shader->num_vgprs - 1) / 4) |
212 S_00B128_SGPRS((num_sgprs - 1) / 8) |
213 S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt));
214 si_pm4_set_reg(pm4, R_00B12C_SPI_SHADER_PGM_RSRC2_VS,
215 S_00B12C_USER_SGPR(num_user_sgprs) |
216 S_00B12C_SO_BASE0_EN(!!shader->selector->so.stride[0]) |
217 S_00B12C_SO_BASE1_EN(!!shader->selector->so.stride[1]) |
218 S_00B12C_SO_BASE2_EN(!!shader->selector->so.stride[2]) |
219 S_00B12C_SO_BASE3_EN(!!shader->selector->so.stride[3]) |
220 S_00B12C_SO_EN(!!shader->selector->so.num_outputs));
221 }
222
223 static void si_shader_ps(struct si_shader *shader)
224 {
225 struct tgsi_shader_info *info = &shader->selector->info;
226 struct si_pm4_state *pm4;
227 unsigned i, spi_ps_in_control;
228 unsigned num_sgprs, num_user_sgprs;
229 unsigned spi_baryc_cntl = 0, spi_ps_input_ena;
230 uint64_t va;
231
232 pm4 = shader->pm4 = CALLOC_STRUCT(si_pm4_state);
233
234 if (pm4 == NULL)
235 return;
236
237 for (i = 0; i < info->num_inputs; i++) {
238 switch (info->input_semantic_name[i]) {
239 case TGSI_SEMANTIC_POSITION:
240 if (info->input_interpolate_loc[i] ==
241 TGSI_INTERPOLATE_LOC_CENTROID) {
242 /* SPI_BARYC_CNTL.POS_FLOAT_LOCATION
243 * Possible vaules:
244 * 0 -> Position = pixel center (default)
245 * 1 -> Position = pixel centroid
246 * 2 -> Position = iterated sample number XXX:
247 * What does this mean?
248 */
249 spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(1);
250 }
251 /* Fall through */
252 case TGSI_SEMANTIC_FACE:
253 continue;
254 }
255 }
256
257 spi_ps_in_control = S_0286D8_NUM_INTERP(shader->nparam) |
258 S_0286D8_BC_OPTIMIZE_DISABLE(1);
259
260 si_pm4_set_reg(pm4, R_0286E0_SPI_BARYC_CNTL, spi_baryc_cntl);
261 spi_ps_input_ena = shader->spi_ps_input_ena;
262 /* we need to enable at least one of them, otherwise we hang the GPU */
263 assert(G_0286CC_PERSP_SAMPLE_ENA(spi_ps_input_ena) ||
264 G_0286CC_PERSP_CENTER_ENA(spi_ps_input_ena) ||
265 G_0286CC_PERSP_CENTROID_ENA(spi_ps_input_ena) ||
266 G_0286CC_PERSP_PULL_MODEL_ENA(spi_ps_input_ena) ||
267 G_0286CC_LINEAR_SAMPLE_ENA(spi_ps_input_ena) ||
268 G_0286CC_LINEAR_CENTER_ENA(spi_ps_input_ena) ||
269 G_0286CC_LINEAR_CENTROID_ENA(spi_ps_input_ena) ||
270 G_0286CC_LINE_STIPPLE_TEX_ENA(spi_ps_input_ena));
271
272 si_pm4_set_reg(pm4, R_0286CC_SPI_PS_INPUT_ENA, spi_ps_input_ena);
273 si_pm4_set_reg(pm4, R_0286D0_SPI_PS_INPUT_ADDR, spi_ps_input_ena);
274 si_pm4_set_reg(pm4, R_0286D8_SPI_PS_IN_CONTROL, spi_ps_in_control);
275
276 si_pm4_set_reg(pm4, R_028710_SPI_SHADER_Z_FORMAT, shader->spi_shader_z_format);
277 si_pm4_set_reg(pm4, R_028714_SPI_SHADER_COL_FORMAT,
278 shader->spi_shader_col_format);
279 si_pm4_set_reg(pm4, R_02823C_CB_SHADER_MASK, shader->cb_shader_mask);
280
281 va = shader->bo->gpu_address;
282 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_DATA);
283 si_pm4_set_reg(pm4, R_00B020_SPI_SHADER_PGM_LO_PS, va >> 8);
284 si_pm4_set_reg(pm4, R_00B024_SPI_SHADER_PGM_HI_PS, va >> 40);
285
286 num_user_sgprs = SI_PS_NUM_USER_SGPR;
287 num_sgprs = shader->num_sgprs;
288 /* One SGPR after user SGPRs is pre-loaded with {prim_mask, lds_offset} */
289 if ((num_user_sgprs + 1) > num_sgprs) {
290 /* Last 2 reserved SGPRs are used for VCC */
291 num_sgprs = num_user_sgprs + 1 + 2;
292 }
293 assert(num_sgprs <= 104);
294
295 si_pm4_set_reg(pm4, R_00B028_SPI_SHADER_PGM_RSRC1_PS,
296 S_00B028_VGPRS((shader->num_vgprs - 1) / 4) |
297 S_00B028_SGPRS((num_sgprs - 1) / 8));
298 si_pm4_set_reg(pm4, R_00B02C_SPI_SHADER_PGM_RSRC2_PS,
299 S_00B02C_EXTRA_LDS_SIZE(shader->lds_size) |
300 S_00B02C_USER_SGPR(num_user_sgprs));
301 }
302
303 void si_shader_init_pm4_state(struct si_shader *shader)
304 {
305 switch (shader->selector->type) {
306 case PIPE_SHADER_VERTEX:
307 if (shader->key.vs.as_es)
308 si_shader_es(shader);
309 else
310 si_shader_vs(shader);
311 break;
312 case PIPE_SHADER_GEOMETRY:
313 si_shader_gs(shader);
314 si_shader_vs(shader->gs_copy_shader);
315 break;
316 case PIPE_SHADER_FRAGMENT:
317 si_shader_ps(shader);
318 break;
319 default:
320 assert(0);
321 }
322 }
323
324 /*
325 * Drawing
326 */
327
328 static unsigned si_conv_pipe_prim(unsigned pprim)
329 {
330 static const unsigned prim_conv[] = {
331 [PIPE_PRIM_POINTS] = V_008958_DI_PT_POINTLIST,
332 [PIPE_PRIM_LINES] = V_008958_DI_PT_LINELIST,
333 [PIPE_PRIM_LINE_LOOP] = V_008958_DI_PT_LINELOOP,
334 [PIPE_PRIM_LINE_STRIP] = V_008958_DI_PT_LINESTRIP,
335 [PIPE_PRIM_TRIANGLES] = V_008958_DI_PT_TRILIST,
336 [PIPE_PRIM_TRIANGLE_STRIP] = V_008958_DI_PT_TRISTRIP,
337 [PIPE_PRIM_TRIANGLE_FAN] = V_008958_DI_PT_TRIFAN,
338 [PIPE_PRIM_QUADS] = V_008958_DI_PT_QUADLIST,
339 [PIPE_PRIM_QUAD_STRIP] = V_008958_DI_PT_QUADSTRIP,
340 [PIPE_PRIM_POLYGON] = V_008958_DI_PT_POLYGON,
341 [PIPE_PRIM_LINES_ADJACENCY] = V_008958_DI_PT_LINELIST_ADJ,
342 [PIPE_PRIM_LINE_STRIP_ADJACENCY] = V_008958_DI_PT_LINESTRIP_ADJ,
343 [PIPE_PRIM_TRIANGLES_ADJACENCY] = V_008958_DI_PT_TRILIST_ADJ,
344 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY] = V_008958_DI_PT_TRISTRIP_ADJ,
345 [R600_PRIM_RECTANGLE_LIST] = V_008958_DI_PT_RECTLIST
346 };
347 unsigned result = prim_conv[pprim];
348 if (result == ~0) {
349 R600_ERR("unsupported primitive type %d\n", pprim);
350 }
351 return result;
352 }
353
354 static unsigned si_conv_prim_to_gs_out(unsigned mode)
355 {
356 static const int prim_conv[] = {
357 [PIPE_PRIM_POINTS] = V_028A6C_OUTPRIM_TYPE_POINTLIST,
358 [PIPE_PRIM_LINES] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
359 [PIPE_PRIM_LINE_LOOP] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
360 [PIPE_PRIM_LINE_STRIP] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
361 [PIPE_PRIM_TRIANGLES] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
362 [PIPE_PRIM_TRIANGLE_STRIP] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
363 [PIPE_PRIM_TRIANGLE_FAN] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
364 [PIPE_PRIM_QUADS] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
365 [PIPE_PRIM_QUAD_STRIP] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
366 [PIPE_PRIM_POLYGON] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
367 [PIPE_PRIM_LINES_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
368 [PIPE_PRIM_LINE_STRIP_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
369 [PIPE_PRIM_TRIANGLES_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
370 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
371 [R600_PRIM_RECTANGLE_LIST] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
372 };
373 assert(mode < Elements(prim_conv));
374
375 return prim_conv[mode];
376 }
377
378 static unsigned si_get_ia_multi_vgt_param(struct si_context *sctx,
379 const struct pipe_draw_info *info)
380 {
381 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
382 unsigned prim = info->mode;
383 unsigned primgroup_size = 128; /* recommended without a GS */
384
385 /* SWITCH_ON_EOP(0) is always preferable. */
386 bool wd_switch_on_eop = false;
387 bool ia_switch_on_eop = false;
388 bool partial_vs_wave = false;
389
390 if (sctx->gs_shader)
391 primgroup_size = 64; /* recommended with a GS */
392
393 /* This is a hardware requirement. */
394 if ((rs && rs->line_stipple_enable) ||
395 (sctx->b.screen->debug_flags & DBG_SWITCH_ON_EOP)) {
396 ia_switch_on_eop = true;
397 wd_switch_on_eop = true;
398 }
399
400 if (sctx->b.streamout.streamout_enabled ||
401 sctx->b.streamout.prims_gen_query_enabled)
402 partial_vs_wave = true;
403
404 if (sctx->b.chip_class >= CIK) {
405 /* WD_SWITCH_ON_EOP has no effect on GPUs with less than
406 * 4 shader engines. Set 1 to pass the assertion below.
407 * The other cases are hardware requirements. */
408 if (sctx->b.screen->info.max_se < 4 ||
409 prim == PIPE_PRIM_POLYGON ||
410 prim == PIPE_PRIM_LINE_LOOP ||
411 prim == PIPE_PRIM_TRIANGLE_FAN ||
412 prim == PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY ||
413 info->primitive_restart)
414 wd_switch_on_eop = true;
415
416 /* Hawaii hangs if instancing is enabled and WD_SWITCH_ON_EOP is 0.
417 * We don't know that for indirect drawing, so treat it as
418 * always problematic. */
419 if (sctx->b.family == CHIP_HAWAII &&
420 (info->indirect || info->instance_count > 1))
421 wd_switch_on_eop = true;
422
423 /* If the WD switch is false, the IA switch must be false too. */
424 assert(wd_switch_on_eop || !ia_switch_on_eop);
425 }
426
427 return S_028AA8_SWITCH_ON_EOP(ia_switch_on_eop) |
428 S_028AA8_PARTIAL_VS_WAVE_ON(partial_vs_wave) |
429 S_028AA8_PRIMGROUP_SIZE(primgroup_size - 1) |
430 S_028AA8_WD_SWITCH_ON_EOP(sctx->b.chip_class >= CIK ? wd_switch_on_eop : 0);
431 }
432
433 static bool si_update_draw_info_state(struct si_context *sctx,
434 const struct pipe_draw_info *info,
435 const struct pipe_index_buffer *ib)
436 {
437 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
438 struct si_shader *vs = si_get_vs_state(sctx);
439 unsigned prim = si_conv_pipe_prim(info->mode);
440 unsigned gs_out_prim =
441 si_conv_prim_to_gs_out(sctx->gs_shader ?
442 sctx->gs_shader->gs_output_prim :
443 info->mode);
444 unsigned ls_mask = 0;
445 unsigned ia_multi_vgt_param = si_get_ia_multi_vgt_param(sctx, info);
446
447 if (pm4 == NULL)
448 return false;
449
450 if (prim == ~0) {
451 FREE(pm4);
452 return false;
453 }
454
455 if (sctx->b.chip_class >= CIK) {
456 si_pm4_set_reg(pm4, R_028B74_VGT_DISPATCH_DRAW_INDEX,
457 ib->index_size == 4 ? 0xFC000000 : 0xFC00);
458
459 si_pm4_cmd_begin(pm4, PKT3_DRAW_PREAMBLE);
460 si_pm4_cmd_add(pm4, prim); /* VGT_PRIMITIVE_TYPE */
461 si_pm4_cmd_add(pm4, ia_multi_vgt_param); /* IA_MULTI_VGT_PARAM */
462 si_pm4_cmd_add(pm4, 0); /* VGT_LS_HS_CONFIG */
463 si_pm4_cmd_end(pm4, false);
464 } else {
465 si_pm4_set_reg(pm4, R_008958_VGT_PRIMITIVE_TYPE, prim);
466 si_pm4_set_reg(pm4, R_028AA8_IA_MULTI_VGT_PARAM, ia_multi_vgt_param);
467 }
468
469 si_pm4_set_reg(pm4, R_028A6C_VGT_GS_OUT_PRIM_TYPE, gs_out_prim);
470 si_pm4_set_reg(pm4, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, info->restart_index);
471 si_pm4_set_reg(pm4, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, info->primitive_restart);
472
473 if (prim == V_008958_DI_PT_LINELIST)
474 ls_mask = 1;
475 else if (prim == V_008958_DI_PT_LINESTRIP)
476 ls_mask = 2;
477 si_pm4_set_reg(pm4, R_028A0C_PA_SC_LINE_STIPPLE,
478 S_028A0C_AUTO_RESET_CNTL(ls_mask) |
479 sctx->pa_sc_line_stipple);
480
481 if (info->mode == PIPE_PRIM_QUADS || info->mode == PIPE_PRIM_QUAD_STRIP || info->mode == PIPE_PRIM_POLYGON) {
482 si_pm4_set_reg(pm4, R_028814_PA_SU_SC_MODE_CNTL,
483 S_028814_PROVOKING_VTX_LAST(1) | sctx->pa_su_sc_mode_cntl);
484 } else {
485 si_pm4_set_reg(pm4, R_028814_PA_SU_SC_MODE_CNTL, sctx->pa_su_sc_mode_cntl);
486 }
487 si_pm4_set_reg(pm4, R_02881C_PA_CL_VS_OUT_CNTL,
488 S_02881C_USE_VTX_POINT_SIZE(vs->vs_out_point_size) |
489 S_02881C_USE_VTX_EDGE_FLAG(vs->vs_out_edgeflag) |
490 S_02881C_USE_VTX_RENDER_TARGET_INDX(vs->vs_out_layer) |
491 S_02881C_VS_OUT_CCDIST0_VEC_ENA((vs->clip_dist_write & 0x0F) != 0) |
492 S_02881C_VS_OUT_CCDIST1_VEC_ENA((vs->clip_dist_write & 0xF0) != 0) |
493 S_02881C_VS_OUT_MISC_VEC_ENA(vs->vs_out_misc_write) |
494 (sctx->queued.named.rasterizer->clip_plane_enable &
495 vs->clip_dist_write));
496 si_pm4_set_reg(pm4, R_028810_PA_CL_CLIP_CNTL,
497 sctx->queued.named.rasterizer->pa_cl_clip_cntl |
498 (vs->clip_dist_write ? 0 :
499 sctx->queued.named.rasterizer->clip_plane_enable & 0x3F));
500
501 si_pm4_set_state(sctx, draw_info, pm4);
502 return true;
503 }
504
505 static void si_update_spi_map(struct si_context *sctx)
506 {
507 struct si_shader *ps = sctx->ps_shader->current;
508 struct si_shader *vs = si_get_vs_state(sctx);
509 struct tgsi_shader_info *psinfo = &ps->selector->info;
510 struct tgsi_shader_info *vsinfo = &vs->selector->info;
511 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
512 unsigned i, j, tmp;
513
514 for (i = 0; i < psinfo->num_inputs; i++) {
515 unsigned name = psinfo->input_semantic_name[i];
516 unsigned index = psinfo->input_semantic_index[i];
517 unsigned interpolate = psinfo->input_interpolate[i];
518 unsigned param_offset = ps->ps_input_param_offset[i];
519
520 if (name == TGSI_SEMANTIC_POSITION)
521 /* Read from preloaded VGPRs, not parameters */
522 continue;
523
524 bcolor:
525 tmp = 0;
526
527 if (interpolate == TGSI_INTERPOLATE_CONSTANT ||
528 (interpolate == TGSI_INTERPOLATE_COLOR &&
529 ps->key.ps.flatshade)) {
530 tmp |= S_028644_FLAT_SHADE(1);
531 }
532
533 if (name == TGSI_SEMANTIC_GENERIC &&
534 sctx->sprite_coord_enable & (1 << index)) {
535 tmp |= S_028644_PT_SPRITE_TEX(1);
536 }
537
538 for (j = 0; j < vsinfo->num_outputs; j++) {
539 if (name == vsinfo->output_semantic_name[j] &&
540 index == vsinfo->output_semantic_index[j]) {
541 tmp |= S_028644_OFFSET(vs->vs_output_param_offset[j]);
542 break;
543 }
544 }
545
546 if (j == vsinfo->num_outputs) {
547 /* No corresponding output found, load defaults into input */
548 tmp |= S_028644_OFFSET(0x20);
549 }
550
551 si_pm4_set_reg(pm4,
552 R_028644_SPI_PS_INPUT_CNTL_0 + param_offset * 4,
553 tmp);
554
555 if (name == TGSI_SEMANTIC_COLOR &&
556 ps->key.ps.color_two_side) {
557 name = TGSI_SEMANTIC_BCOLOR;
558 param_offset++;
559 goto bcolor;
560 }
561 }
562
563 si_pm4_set_state(sctx, spi, pm4);
564 }
565
566 /* Initialize state related to ESGS / GSVS ring buffers */
567 static void si_init_gs_rings(struct si_context *sctx)
568 {
569 unsigned esgs_ring_size = 128 * 1024;
570 unsigned gsvs_ring_size = 64 * 1024 * 1024;
571
572 assert(!sctx->gs_rings);
573 sctx->gs_rings = CALLOC_STRUCT(si_pm4_state);
574
575 sctx->esgs_ring = pipe_buffer_create(sctx->b.b.screen, PIPE_BIND_CUSTOM,
576 PIPE_USAGE_DEFAULT, esgs_ring_size);
577
578 sctx->gsvs_ring = pipe_buffer_create(sctx->b.b.screen, PIPE_BIND_CUSTOM,
579 PIPE_USAGE_DEFAULT, gsvs_ring_size);
580
581 if (sctx->b.chip_class >= CIK) {
582 si_pm4_set_reg(sctx->gs_rings, R_030900_VGT_ESGS_RING_SIZE,
583 esgs_ring_size / 256);
584 si_pm4_set_reg(sctx->gs_rings, R_030904_VGT_GSVS_RING_SIZE,
585 gsvs_ring_size / 256);
586 } else {
587 si_pm4_set_reg(sctx->gs_rings, R_0088C8_VGT_ESGS_RING_SIZE,
588 esgs_ring_size / 256);
589 si_pm4_set_reg(sctx->gs_rings, R_0088CC_VGT_GSVS_RING_SIZE,
590 gsvs_ring_size / 256);
591 }
592
593 si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_VERTEX, SI_RING_ESGS,
594 sctx->esgs_ring, 0, esgs_ring_size,
595 true, true, 4, 64);
596 si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_GEOMETRY, SI_RING_ESGS,
597 sctx->esgs_ring, 0, esgs_ring_size,
598 false, false, 0, 0);
599 si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_VERTEX, SI_RING_GSVS,
600 sctx->gsvs_ring, 0, gsvs_ring_size,
601 false, false, 0, 0);
602 }
603
604 static void si_update_derived_state(struct si_context *sctx)
605 {
606 struct pipe_context * ctx = (struct pipe_context*)sctx;
607
608 if (!sctx->blitter->running) {
609 /* Flush depth textures which need to be flushed. */
610 for (int i = 0; i < SI_NUM_SHADERS; i++) {
611 if (sctx->samplers[i].depth_texture_mask) {
612 si_flush_depth_textures(sctx, &sctx->samplers[i]);
613 }
614 if (sctx->samplers[i].compressed_colortex_mask) {
615 si_decompress_color_textures(sctx, &sctx->samplers[i]);
616 }
617 }
618 }
619
620 if (sctx->gs_shader) {
621 si_shader_select(ctx, sctx->gs_shader);
622 si_pm4_bind_state(sctx, gs, sctx->gs_shader->current->pm4);
623 si_pm4_bind_state(sctx, vs, sctx->gs_shader->current->gs_copy_shader->pm4);
624
625 sctx->b.streamout.stride_in_dw = sctx->gs_shader->so.stride;
626
627 si_shader_select(ctx, sctx->vs_shader);
628 si_pm4_bind_state(sctx, es, sctx->vs_shader->current->pm4);
629
630 if (!sctx->gs_rings)
631 si_init_gs_rings(sctx);
632 if (sctx->emitted.named.gs_rings != sctx->gs_rings)
633 sctx->b.flags |= R600_CONTEXT_VGT_FLUSH;
634 si_pm4_bind_state(sctx, gs_rings, sctx->gs_rings);
635
636 si_set_ring_buffer(ctx, PIPE_SHADER_GEOMETRY, SI_RING_GSVS,
637 sctx->gsvs_ring,
638 sctx->gs_shader->gs_max_out_vertices *
639 sctx->gs_shader->info.num_outputs * 16,
640 64, true, true, 4, 16);
641
642 if (!sctx->gs_on) {
643 sctx->gs_on = CALLOC_STRUCT(si_pm4_state);
644
645 si_pm4_set_reg(sctx->gs_on, R_028B54_VGT_SHADER_STAGES_EN,
646 S_028B54_ES_EN(V_028B54_ES_STAGE_REAL) |
647 S_028B54_GS_EN(1) |
648 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER));
649 }
650 si_pm4_bind_state(sctx, gs_onoff, sctx->gs_on);
651 } else {
652 si_shader_select(ctx, sctx->vs_shader);
653 si_pm4_bind_state(sctx, vs, sctx->vs_shader->current->pm4);
654
655 sctx->b.streamout.stride_in_dw = sctx->vs_shader->so.stride;
656
657 if (!sctx->gs_off) {
658 sctx->gs_off = CALLOC_STRUCT(si_pm4_state);
659
660 si_pm4_set_reg(sctx->gs_off, R_028A40_VGT_GS_MODE, 0);
661 si_pm4_set_reg(sctx->gs_off, R_028B54_VGT_SHADER_STAGES_EN, 0);
662 }
663 si_pm4_bind_state(sctx, gs_onoff, sctx->gs_off);
664 si_pm4_bind_state(sctx, gs_rings, NULL);
665 si_pm4_bind_state(sctx, gs, NULL);
666 si_pm4_bind_state(sctx, es, NULL);
667 }
668
669 si_shader_select(ctx, sctx->ps_shader);
670
671 if (!sctx->ps_shader->current) {
672 struct si_shader_selector *sel;
673
674 /* use a dummy shader if compiling the shader (variant) failed */
675 si_make_dummy_ps(sctx);
676 sel = sctx->dummy_pixel_shader;
677 si_shader_select(ctx, sel);
678 sctx->ps_shader->current = sel->current;
679 }
680
681 si_pm4_bind_state(sctx, ps, sctx->ps_shader->current->pm4);
682
683 if (si_pm4_state_changed(sctx, ps) || si_pm4_state_changed(sctx, vs))
684 si_update_spi_map(sctx);
685
686 if (sctx->ps_db_shader_control != sctx->ps_shader->current->db_shader_control) {
687 sctx->ps_db_shader_control = sctx->ps_shader->current->db_shader_control;
688 sctx->db_render_state.dirty = true;
689 }
690 }
691
692 static void si_state_draw(struct si_context *sctx,
693 const struct pipe_draw_info *info,
694 const struct pipe_index_buffer *ib)
695 {
696 unsigned sh_base_reg = (sctx->gs_shader ? R_00B330_SPI_SHADER_USER_DATA_ES_0 :
697 R_00B130_SPI_SHADER_USER_DATA_VS_0);
698 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
699
700 if (pm4 == NULL)
701 return;
702
703 if (info->count_from_stream_output) {
704 struct r600_so_target *t =
705 (struct r600_so_target*)info->count_from_stream_output;
706 uint64_t va = t->buf_filled_size->gpu_address +
707 t->buf_filled_size_offset;
708
709 si_pm4_set_reg(pm4, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE,
710 t->stride_in_dw);
711
712 si_pm4_cmd_begin(pm4, PKT3_COPY_DATA);
713 si_pm4_cmd_add(pm4,
714 COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
715 COPY_DATA_DST_SEL(COPY_DATA_REG) |
716 COPY_DATA_WR_CONFIRM);
717 si_pm4_cmd_add(pm4, va); /* src address lo */
718 si_pm4_cmd_add(pm4, va >> 32UL); /* src address hi */
719 si_pm4_cmd_add(pm4, R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE >> 2);
720 si_pm4_cmd_add(pm4, 0); /* unused */
721 si_pm4_add_bo(pm4, t->buf_filled_size, RADEON_USAGE_READ,
722 RADEON_PRIO_MIN);
723 si_pm4_cmd_end(pm4, true);
724 }
725
726 /* draw packet */
727 si_pm4_cmd_begin(pm4, PKT3_INDEX_TYPE);
728 if (ib->index_size == 4) {
729 si_pm4_cmd_add(pm4, V_028A7C_VGT_INDEX_32 | (SI_BIG_ENDIAN ?
730 V_028A7C_VGT_DMA_SWAP_32_BIT : 0));
731 } else {
732 si_pm4_cmd_add(pm4, V_028A7C_VGT_INDEX_16 | (SI_BIG_ENDIAN ?
733 V_028A7C_VGT_DMA_SWAP_16_BIT : 0));
734 }
735 si_pm4_cmd_end(pm4, sctx->b.predicate_drawing);
736
737 if (!info->indirect) {
738 si_pm4_cmd_begin(pm4, PKT3_NUM_INSTANCES);
739 si_pm4_cmd_add(pm4, info->instance_count);
740 si_pm4_cmd_end(pm4, sctx->b.predicate_drawing);
741
742 si_pm4_set_reg(pm4, sh_base_reg + SI_SGPR_BASE_VERTEX * 4,
743 info->indexed ? info->index_bias : info->start);
744 si_pm4_set_reg(pm4, sh_base_reg + SI_SGPR_START_INSTANCE * 4,
745 info->start_instance);
746 } else {
747 si_pm4_add_bo(pm4, (struct r600_resource *)info->indirect,
748 RADEON_USAGE_READ, RADEON_PRIO_MIN);
749 }
750
751 if (info->indexed) {
752 uint32_t max_size = (ib->buffer->width0 - ib->offset) /
753 ib->index_size;
754 uint64_t va = r600_resource(ib->buffer)->gpu_address + ib->offset;
755
756 si_pm4_add_bo(pm4, (struct r600_resource *)ib->buffer, RADEON_USAGE_READ,
757 RADEON_PRIO_MIN);
758
759 if (info->indirect) {
760 uint64_t indirect_va = r600_resource(info->indirect)->gpu_address;
761 si_cmd_draw_index_indirect(pm4, indirect_va, va, max_size,
762 info->indirect_offset,
763 sh_base_reg + SI_SGPR_BASE_VERTEX * 4,
764 sh_base_reg + SI_SGPR_START_INSTANCE * 4,
765 sctx->b.predicate_drawing);
766 } else {
767 va += info->start * ib->index_size;
768 si_cmd_draw_index_2(pm4, max_size, va, info->count,
769 V_0287F0_DI_SRC_SEL_DMA,
770 sctx->b.predicate_drawing);
771 }
772 } else {
773 if (info->indirect) {
774 uint64_t indirect_va = r600_resource(info->indirect)->gpu_address;
775 si_cmd_draw_indirect(pm4, indirect_va, info->indirect_offset,
776 sh_base_reg + SI_SGPR_BASE_VERTEX * 4,
777 sh_base_reg + SI_SGPR_START_INSTANCE * 4,
778 sctx->b.predicate_drawing);
779 } else {
780 si_cmd_draw_index_auto(pm4, info->count,
781 V_0287F0_DI_SRC_SEL_AUTO_INDEX |
782 S_0287F0_USE_OPAQUE(!!info->count_from_stream_output),
783 sctx->b.predicate_drawing);
784 }
785 }
786
787 si_pm4_set_state(sctx, draw, pm4);
788 }
789
790 void si_emit_cache_flush(struct r600_common_context *sctx, struct r600_atom *atom)
791 {
792 struct radeon_winsys_cs *cs = sctx->rings.gfx.cs;
793 uint32_t cp_coher_cntl = 0;
794 uint32_t compute =
795 PKT3_SHADER_TYPE_S(!!(sctx->flags & R600_CONTEXT_FLAG_COMPUTE));
796
797 /* XXX SI flushes both ICACHE and KCACHE if either flag is set.
798 * XXX CIK shouldn't have this issue. Test CIK before separating the flags
799 * XXX to ensure there is no regression. Also find out if there is another
800 * XXX way to flush either ICACHE or KCACHE but not both for SI. */
801 if (sctx->flags & (R600_CONTEXT_INV_SHADER_CACHE |
802 R600_CONTEXT_INV_CONST_CACHE)) {
803 cp_coher_cntl |= S_0085F0_SH_ICACHE_ACTION_ENA(1) |
804 S_0085F0_SH_KCACHE_ACTION_ENA(1);
805 }
806 if (sctx->flags & (R600_CONTEXT_INV_TEX_CACHE |
807 R600_CONTEXT_STREAMOUT_FLUSH)) {
808 cp_coher_cntl |= S_0085F0_TC_ACTION_ENA(1) |
809 S_0085F0_TCL1_ACTION_ENA(1);
810 }
811 if (sctx->flags & R600_CONTEXT_FLUSH_AND_INV_CB) {
812 cp_coher_cntl |= S_0085F0_CB_ACTION_ENA(1) |
813 S_0085F0_CB0_DEST_BASE_ENA(1) |
814 S_0085F0_CB1_DEST_BASE_ENA(1) |
815 S_0085F0_CB2_DEST_BASE_ENA(1) |
816 S_0085F0_CB3_DEST_BASE_ENA(1) |
817 S_0085F0_CB4_DEST_BASE_ENA(1) |
818 S_0085F0_CB5_DEST_BASE_ENA(1) |
819 S_0085F0_CB6_DEST_BASE_ENA(1) |
820 S_0085F0_CB7_DEST_BASE_ENA(1);
821 }
822 if (sctx->flags & R600_CONTEXT_FLUSH_AND_INV_DB) {
823 cp_coher_cntl |= S_0085F0_DB_ACTION_ENA(1) |
824 S_0085F0_DB_DEST_BASE_ENA(1);
825 }
826
827 if (cp_coher_cntl) {
828 if (sctx->chip_class >= CIK) {
829 radeon_emit(cs, PKT3(PKT3_ACQUIRE_MEM, 5, 0) | compute);
830 radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */
831 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
832 radeon_emit(cs, 0xff); /* CP_COHER_SIZE_HI */
833 radeon_emit(cs, 0); /* CP_COHER_BASE */
834 radeon_emit(cs, 0); /* CP_COHER_BASE_HI */
835 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
836 } else {
837 radeon_emit(cs, PKT3(PKT3_SURFACE_SYNC, 3, 0) | compute);
838 radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */
839 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
840 radeon_emit(cs, 0); /* CP_COHER_BASE */
841 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
842 }
843 }
844
845 if (sctx->flags & R600_CONTEXT_FLUSH_AND_INV_CB_META) {
846 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0) | compute);
847 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_META) | EVENT_INDEX(0));
848 }
849 if (sctx->flags & R600_CONTEXT_FLUSH_AND_INV_DB_META) {
850 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0) | compute);
851 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_DB_META) | EVENT_INDEX(0));
852 }
853 if (sctx->flags & R600_CONTEXT_FLUSH_WITH_INV_L2) {
854 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0) | compute);
855 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH) | EVENT_INDEX(7) |
856 EVENT_WRITE_INV_L2);
857 }
858
859 if (sctx->flags & (R600_CONTEXT_WAIT_3D_IDLE |
860 R600_CONTEXT_PS_PARTIAL_FLUSH)) {
861 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0) | compute);
862 radeon_emit(cs, EVENT_TYPE(V_028A90_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
863 } else if (sctx->flags & R600_CONTEXT_STREAMOUT_FLUSH) {
864 /* Needed if streamout buffers are going to be used as a source. */
865 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0) | compute);
866 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
867 }
868
869 if (sctx->flags & R600_CONTEXT_CS_PARTIAL_FLUSH) {
870 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0) | compute);
871 radeon_emit(cs, EVENT_TYPE(V_028A90_CS_PARTIAL_FLUSH | EVENT_INDEX(4)));
872 }
873
874 if (sctx->flags & R600_CONTEXT_VGT_FLUSH) {
875 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0) | compute);
876 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
877 }
878 if (sctx->flags & R600_CONTEXT_VGT_STREAMOUT_SYNC) {
879 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0) | compute);
880 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_STREAMOUT_SYNC) | EVENT_INDEX(0));
881 }
882
883 sctx->flags = 0;
884 }
885
886 const struct r600_atom si_atom_cache_flush = { si_emit_cache_flush, 21 }; /* number of CS dwords */
887
888 static void si_get_draw_start_count(struct si_context *sctx,
889 const struct pipe_draw_info *info,
890 unsigned *start, unsigned *count)
891 {
892 if (info->indirect) {
893 struct r600_resource *indirect =
894 (struct r600_resource*)info->indirect;
895 int *data = r600_buffer_map_sync_with_rings(&sctx->b,
896 indirect, PIPE_TRANSFER_READ);
897 data += info->indirect_offset/sizeof(int);
898 *start = data[2];
899 *count = data[0];
900 } else {
901 *start = info->start;
902 *count = info->count;
903 }
904 }
905
906 void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info)
907 {
908 struct si_context *sctx = (struct si_context *)ctx;
909 struct pipe_index_buffer ib = {};
910 uint32_t i;
911
912 if (!info->count && !info->indirect &&
913 (info->indexed || !info->count_from_stream_output))
914 return;
915
916 if (!sctx->ps_shader || !sctx->vs_shader)
917 return;
918
919 si_update_derived_state(sctx);
920
921 if (sctx->vertex_buffers_dirty) {
922 si_update_vertex_buffers(sctx);
923 sctx->vertex_buffers_dirty = false;
924 }
925
926 if (info->indexed) {
927 /* Initialize the index buffer struct. */
928 pipe_resource_reference(&ib.buffer, sctx->index_buffer.buffer);
929 ib.user_buffer = sctx->index_buffer.user_buffer;
930 ib.index_size = sctx->index_buffer.index_size;
931 ib.offset = sctx->index_buffer.offset;
932
933 /* Translate or upload, if needed. */
934 if (ib.index_size == 1) {
935 struct pipe_resource *out_buffer = NULL;
936 unsigned out_offset, start, count, start_offset;
937 void *ptr;
938
939 si_get_draw_start_count(sctx, info, &start, &count);
940 start_offset = start * ib.index_size;
941
942 u_upload_alloc(sctx->b.uploader, start_offset, count * 2,
943 &out_offset, &out_buffer, &ptr);
944
945 util_shorten_ubyte_elts_to_userptr(&sctx->b.b, &ib, 0,
946 ib.offset + start_offset,
947 count, ptr);
948
949 pipe_resource_reference(&ib.buffer, NULL);
950 ib.user_buffer = NULL;
951 ib.buffer = out_buffer;
952 /* info->start will be added by the drawing code */
953 ib.offset = out_offset - start_offset;
954 ib.index_size = 2;
955 } else if (ib.user_buffer && !ib.buffer) {
956 unsigned start, count, start_offset;
957
958 si_get_draw_start_count(sctx, info, &start, &count);
959 start_offset = start * ib.index_size;
960
961 u_upload_data(sctx->b.uploader, start_offset, count * ib.index_size,
962 (char*)ib.user_buffer + start_offset,
963 &ib.offset, &ib.buffer);
964 /* info->start will be added by the drawing code */
965 ib.offset -= start_offset;
966 }
967 }
968
969 if (!si_update_draw_info_state(sctx, info, &ib))
970 return;
971
972 si_state_draw(sctx, info, &ib);
973
974 sctx->pm4_dirty_cdwords += si_pm4_dirty_dw(sctx);
975
976 /* Check flush flags. */
977 if (sctx->b.flags)
978 sctx->atoms.s.cache_flush->dirty = true;
979
980 si_need_cs_space(sctx, 0, TRUE);
981
982 /* Emit states. */
983 for (i = 0; i < SI_NUM_ATOMS(sctx); i++) {
984 if (sctx->atoms.array[i]->dirty) {
985 sctx->atoms.array[i]->emit(&sctx->b, sctx->atoms.array[i]);
986 sctx->atoms.array[i]->dirty = false;
987 }
988 }
989
990 si_pm4_emit_dirty(sctx);
991 sctx->pm4_dirty_cdwords = 0;
992
993 #if SI_TRACE_CS
994 if (sctx->screen->b.trace_bo) {
995 si_trace_emit(sctx);
996 }
997 #endif
998
999 /* Workaround for a VGT hang when streamout is enabled.
1000 * It must be done after drawing. */
1001 if (sctx->b.family == CHIP_HAWAII &&
1002 (sctx->b.streamout.streamout_enabled ||
1003 sctx->b.streamout.prims_gen_query_enabled)) {
1004 sctx->b.flags |= R600_CONTEXT_VGT_STREAMOUT_SYNC;
1005 }
1006
1007 /* Set the depth buffer as dirty. */
1008 if (sctx->framebuffer.state.zsbuf) {
1009 struct pipe_surface *surf = sctx->framebuffer.state.zsbuf;
1010 struct r600_texture *rtex = (struct r600_texture *)surf->texture;
1011
1012 rtex->dirty_level_mask |= 1 << surf->u.tex.level;
1013 }
1014 if (sctx->framebuffer.compressed_cb_mask) {
1015 struct pipe_surface *surf;
1016 struct r600_texture *rtex;
1017 unsigned mask = sctx->framebuffer.compressed_cb_mask;
1018
1019 do {
1020 unsigned i = u_bit_scan(&mask);
1021 surf = sctx->framebuffer.state.cbufs[i];
1022 rtex = (struct r600_texture*)surf->texture;
1023
1024 rtex->dirty_level_mask |= 1 << surf->u.tex.level;
1025 } while (mask);
1026 }
1027
1028 pipe_resource_reference(&ib.buffer, NULL);
1029 sctx->b.num_draw_calls++;
1030 }
1031
1032 #if SI_TRACE_CS
1033 void si_trace_emit(struct si_context *sctx)
1034 {
1035 struct si_screen *sscreen = sctx->screen;
1036 struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs;
1037 uint64_t va;
1038
1039 va = sscreen->b.trace_bo->gpu_address;
1040 r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx, sscreen->b.trace_bo,
1041 RADEON_USAGE_READWRITE, RADEON_PRIO_MIN);
1042 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 4, 0));
1043 radeon_emit(cs, PKT3_WRITE_DATA_DST_SEL(PKT3_WRITE_DATA_DST_SEL_MEM_SYNC) |
1044 PKT3_WRITE_DATA_WR_CONFIRM |
1045 PKT3_WRITE_DATA_ENGINE_SEL(PKT3_WRITE_DATA_ENGINE_SEL_ME));
1046 radeon_emit(cs, va & 0xFFFFFFFFUL);
1047 radeon_emit(cs, (va >> 32UL) & 0xFFFFFFFFUL);
1048 radeon_emit(cs, cs->cdw);
1049 radeon_emit(cs, sscreen->b.cs_count);
1050 }
1051 #endif