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[mesa.git] / src / gallium / drivers / radeonsi / si_state_draw.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Christian König <christian.koenig@amd.com>
25 */
26
27 #include "si_pipe.h"
28 #include "si_shader.h"
29 #include "radeon/r600_cs.h"
30 #include "sid.h"
31
32 #include "util/u_index_modify.h"
33 #include "util/u_upload_mgr.h"
34 #include "util/u_prim.h"
35 #include "util/u_memory.h"
36
37 static unsigned si_conv_pipe_prim(unsigned mode)
38 {
39 static const unsigned prim_conv[] = {
40 [PIPE_PRIM_POINTS] = V_008958_DI_PT_POINTLIST,
41 [PIPE_PRIM_LINES] = V_008958_DI_PT_LINELIST,
42 [PIPE_PRIM_LINE_LOOP] = V_008958_DI_PT_LINELOOP,
43 [PIPE_PRIM_LINE_STRIP] = V_008958_DI_PT_LINESTRIP,
44 [PIPE_PRIM_TRIANGLES] = V_008958_DI_PT_TRILIST,
45 [PIPE_PRIM_TRIANGLE_STRIP] = V_008958_DI_PT_TRISTRIP,
46 [PIPE_PRIM_TRIANGLE_FAN] = V_008958_DI_PT_TRIFAN,
47 [PIPE_PRIM_QUADS] = V_008958_DI_PT_QUADLIST,
48 [PIPE_PRIM_QUAD_STRIP] = V_008958_DI_PT_QUADSTRIP,
49 [PIPE_PRIM_POLYGON] = V_008958_DI_PT_POLYGON,
50 [PIPE_PRIM_LINES_ADJACENCY] = V_008958_DI_PT_LINELIST_ADJ,
51 [PIPE_PRIM_LINE_STRIP_ADJACENCY] = V_008958_DI_PT_LINESTRIP_ADJ,
52 [PIPE_PRIM_TRIANGLES_ADJACENCY] = V_008958_DI_PT_TRILIST_ADJ,
53 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY] = V_008958_DI_PT_TRISTRIP_ADJ,
54 [PIPE_PRIM_PATCHES] = V_008958_DI_PT_PATCH,
55 [R600_PRIM_RECTANGLE_LIST] = V_008958_DI_PT_RECTLIST
56 };
57 assert(mode < ARRAY_SIZE(prim_conv));
58 return prim_conv[mode];
59 }
60
61 static unsigned si_conv_prim_to_gs_out(unsigned mode)
62 {
63 static const int prim_conv[] = {
64 [PIPE_PRIM_POINTS] = V_028A6C_OUTPRIM_TYPE_POINTLIST,
65 [PIPE_PRIM_LINES] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
66 [PIPE_PRIM_LINE_LOOP] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
67 [PIPE_PRIM_LINE_STRIP] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
68 [PIPE_PRIM_TRIANGLES] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
69 [PIPE_PRIM_TRIANGLE_STRIP] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
70 [PIPE_PRIM_TRIANGLE_FAN] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
71 [PIPE_PRIM_QUADS] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
72 [PIPE_PRIM_QUAD_STRIP] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
73 [PIPE_PRIM_POLYGON] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
74 [PIPE_PRIM_LINES_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
75 [PIPE_PRIM_LINE_STRIP_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
76 [PIPE_PRIM_TRIANGLES_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
77 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
78 [PIPE_PRIM_PATCHES] = V_028A6C_OUTPRIM_TYPE_POINTLIST,
79 [R600_PRIM_RECTANGLE_LIST] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
80 };
81 assert(mode < ARRAY_SIZE(prim_conv));
82
83 return prim_conv[mode];
84 }
85
86 /**
87 * This calculates the LDS size for tessellation shaders (VS, TCS, TES).
88 * LS.LDS_SIZE is shared by all 3 shader stages.
89 *
90 * The information about LDS and other non-compile-time parameters is then
91 * written to userdata SGPRs.
92 */
93 static void si_emit_derived_tess_state(struct si_context *sctx,
94 const struct pipe_draw_info *info,
95 unsigned *num_patches)
96 {
97 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
98 struct si_shader_ctx_state *ls = &sctx->vs_shader;
99 /* The TES pointer will only be used for sctx->last_tcs.
100 * It would be wrong to think that TCS = TES. */
101 struct si_shader_selector *tcs =
102 sctx->tcs_shader.cso ? sctx->tcs_shader.cso : sctx->tes_shader.cso;
103 unsigned tes_sh_base = sctx->shader_userdata.sh_base[PIPE_SHADER_TESS_EVAL];
104 unsigned num_tcs_input_cp = info->vertices_per_patch;
105 unsigned num_tcs_output_cp, num_tcs_inputs, num_tcs_outputs;
106 unsigned num_tcs_patch_outputs;
107 unsigned input_vertex_size, output_vertex_size, pervertex_output_patch_size;
108 unsigned input_patch_size, output_patch_size, output_patch0_offset;
109 unsigned perpatch_output_offset, lds_size, ls_rsrc2;
110 unsigned tcs_in_layout, tcs_out_layout, tcs_out_offsets;
111 unsigned offchip_layout, hardware_lds_size;
112
113 /* This calculates how shader inputs and outputs among VS, TCS, and TES
114 * are laid out in LDS. */
115 num_tcs_inputs = util_last_bit64(ls->cso->outputs_written);
116
117 if (sctx->tcs_shader.cso) {
118 num_tcs_outputs = util_last_bit64(tcs->outputs_written);
119 num_tcs_output_cp = tcs->info.properties[TGSI_PROPERTY_TCS_VERTICES_OUT];
120 num_tcs_patch_outputs = util_last_bit64(tcs->patch_outputs_written);
121 } else {
122 /* No TCS. Route varyings from LS to TES. */
123 num_tcs_outputs = num_tcs_inputs;
124 num_tcs_output_cp = num_tcs_input_cp;
125 num_tcs_patch_outputs = 2; /* TESSINNER + TESSOUTER */
126 }
127
128 input_vertex_size = num_tcs_inputs * 16;
129 output_vertex_size = num_tcs_outputs * 16;
130
131 input_patch_size = num_tcs_input_cp * input_vertex_size;
132
133 pervertex_output_patch_size = num_tcs_output_cp * output_vertex_size;
134 output_patch_size = pervertex_output_patch_size + num_tcs_patch_outputs * 16;
135
136 /* Ensure that we only need one wave per SIMD so we don't need to check
137 * resource usage. Also ensures that the number of tcs in and out
138 * vertices per threadgroup are at most 256.
139 */
140 *num_patches = 64 / MAX2(num_tcs_input_cp, num_tcs_output_cp) * 4;
141
142 /* Make sure that the data fits in LDS. This assumes the shaders only
143 * use LDS for the inputs and outputs.
144 */
145 hardware_lds_size = sctx->b.chip_class >= CIK ? 65536 : 32768;
146 *num_patches = MIN2(*num_patches, hardware_lds_size / (input_patch_size +
147 output_patch_size));
148
149 /* Make sure the output data fits in the offchip buffer */
150 *num_patches = MIN2(*num_patches, SI_TESS_OFFCHIP_BLOCK_SIZE /
151 output_patch_size);
152
153 /* Not necessary for correctness, but improves performance. The
154 * specific value is taken from the proprietary driver.
155 */
156 *num_patches = MIN2(*num_patches, 40);
157
158 output_patch0_offset = input_patch_size * *num_patches;
159 perpatch_output_offset = output_patch0_offset + pervertex_output_patch_size;
160
161 lds_size = output_patch0_offset + output_patch_size * *num_patches;
162 ls_rsrc2 = ls->current->config.rsrc2;
163
164 if (sctx->b.chip_class >= CIK) {
165 assert(lds_size <= 65536);
166 ls_rsrc2 |= S_00B52C_LDS_SIZE(align(lds_size, 512) / 512);
167 } else {
168 assert(lds_size <= 32768);
169 ls_rsrc2 |= S_00B52C_LDS_SIZE(align(lds_size, 256) / 256);
170 }
171
172 if (sctx->last_ls == ls->current &&
173 sctx->last_tcs == tcs &&
174 sctx->last_tes_sh_base == tes_sh_base &&
175 sctx->last_num_tcs_input_cp == num_tcs_input_cp)
176 return;
177
178 sctx->last_ls = ls->current;
179 sctx->last_tcs = tcs;
180 sctx->last_tes_sh_base = tes_sh_base;
181 sctx->last_num_tcs_input_cp = num_tcs_input_cp;
182
183 /* Due to a hw bug, RSRC2_LS must be written twice with another
184 * LS register written in between. */
185 if (sctx->b.chip_class == CIK && sctx->b.family != CHIP_HAWAII)
186 radeon_set_sh_reg(cs, R_00B52C_SPI_SHADER_PGM_RSRC2_LS, ls_rsrc2);
187 radeon_set_sh_reg_seq(cs, R_00B528_SPI_SHADER_PGM_RSRC1_LS, 2);
188 radeon_emit(cs, ls->current->config.rsrc1);
189 radeon_emit(cs, ls_rsrc2);
190
191 /* Compute userdata SGPRs. */
192 assert(((input_vertex_size / 4) & ~0xff) == 0);
193 assert(((output_vertex_size / 4) & ~0xff) == 0);
194 assert(((input_patch_size / 4) & ~0x1fff) == 0);
195 assert(((output_patch_size / 4) & ~0x1fff) == 0);
196 assert(((output_patch0_offset / 16) & ~0xffff) == 0);
197 assert(((perpatch_output_offset / 16) & ~0xffff) == 0);
198 assert(num_tcs_input_cp <= 32);
199 assert(num_tcs_output_cp <= 32);
200
201 tcs_in_layout = (input_patch_size / 4) |
202 ((input_vertex_size / 4) << 13);
203 tcs_out_layout = (output_patch_size / 4) |
204 ((output_vertex_size / 4) << 13);
205 tcs_out_offsets = (output_patch0_offset / 16) |
206 ((perpatch_output_offset / 16) << 16);
207 offchip_layout = (pervertex_output_patch_size * *num_patches << 16) |
208 (num_tcs_output_cp << 9) | *num_patches;
209
210 /* Set them for LS. */
211 radeon_set_sh_reg(cs,
212 R_00B530_SPI_SHADER_USER_DATA_LS_0 + SI_SGPR_LS_OUT_LAYOUT * 4,
213 tcs_in_layout);
214
215 /* Set them for TCS. */
216 radeon_set_sh_reg_seq(cs,
217 R_00B430_SPI_SHADER_USER_DATA_HS_0 + SI_SGPR_TCS_OFFCHIP_LAYOUT * 4, 4);
218 radeon_emit(cs, offchip_layout);
219 radeon_emit(cs, tcs_out_offsets);
220 radeon_emit(cs, tcs_out_layout | (num_tcs_input_cp << 26));
221 radeon_emit(cs, tcs_in_layout);
222
223 /* Set them for TES. */
224 radeon_set_sh_reg_seq(cs, tes_sh_base + SI_SGPR_TCS_OFFCHIP_LAYOUT * 4, 1);
225 radeon_emit(cs, offchip_layout);
226 }
227
228 static unsigned si_num_prims_for_vertices(const struct pipe_draw_info *info)
229 {
230 switch (info->mode) {
231 case PIPE_PRIM_PATCHES:
232 return info->count / info->vertices_per_patch;
233 case R600_PRIM_RECTANGLE_LIST:
234 return info->count / 3;
235 default:
236 return u_prims_for_vertices(info->mode, info->count);
237 }
238 }
239
240 static unsigned si_get_ia_multi_vgt_param(struct si_context *sctx,
241 const struct pipe_draw_info *info,
242 unsigned num_patches)
243 {
244 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
245 unsigned prim = info->mode;
246 unsigned primgroup_size = 128; /* recommended without a GS */
247 unsigned max_primgroup_in_wave = 2;
248
249 /* SWITCH_ON_EOP(0) is always preferable. */
250 bool wd_switch_on_eop = false;
251 bool ia_switch_on_eop = false;
252 bool ia_switch_on_eoi = false;
253 bool partial_vs_wave = false;
254 bool partial_es_wave = false;
255
256 if (sctx->gs_shader.cso)
257 primgroup_size = 64; /* recommended with a GS */
258
259 if (sctx->tes_shader.cso) {
260 /* primgroup_size must be set to a multiple of NUM_PATCHES */
261 primgroup_size = num_patches;
262
263 /* SWITCH_ON_EOI must be set if PrimID is used. */
264 if ((sctx->tcs_shader.cso && sctx->tcs_shader.cso->info.uses_primid) ||
265 sctx->tes_shader.cso->info.uses_primid)
266 ia_switch_on_eoi = true;
267
268 /* Bug with tessellation and GS on Bonaire and older 2 SE chips. */
269 if ((sctx->b.family == CHIP_TAHITI ||
270 sctx->b.family == CHIP_PITCAIRN ||
271 sctx->b.family == CHIP_BONAIRE) &&
272 sctx->gs_shader.cso)
273 partial_vs_wave = true;
274
275 /* Needed for 028B6C_DISTRIBUTION_MODE != 0 */
276 if (sctx->b.chip_class >= VI) {
277 if (sctx->gs_shader.cso)
278 partial_es_wave = true;
279 else
280 partial_vs_wave = true;
281 }
282 }
283
284 /* This is a hardware requirement. */
285 if ((rs && rs->line_stipple_enable) ||
286 (sctx->b.screen->debug_flags & DBG_SWITCH_ON_EOP)) {
287 ia_switch_on_eop = true;
288 wd_switch_on_eop = true;
289 }
290
291 if (sctx->b.chip_class >= CIK) {
292 /* WD_SWITCH_ON_EOP has no effect on GPUs with less than
293 * 4 shader engines. Set 1 to pass the assertion below.
294 * The other cases are hardware requirements. */
295 if (sctx->b.screen->info.max_se < 4 ||
296 prim == PIPE_PRIM_POLYGON ||
297 prim == PIPE_PRIM_LINE_LOOP ||
298 prim == PIPE_PRIM_TRIANGLE_FAN ||
299 prim == PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY ||
300 info->primitive_restart ||
301 info->count_from_stream_output)
302 wd_switch_on_eop = true;
303
304 /* Hawaii hangs if instancing is enabled and WD_SWITCH_ON_EOP is 0.
305 * We don't know that for indirect drawing, so treat it as
306 * always problematic. */
307 if (sctx->b.family == CHIP_HAWAII &&
308 (info->indirect || info->instance_count > 1))
309 wd_switch_on_eop = true;
310
311 /* Performance recommendation for 4 SE Gfx7-8 parts if
312 * instances are smaller than a primgroup. Ignore the fact
313 * primgroup_size is a primitive count, not vertex count.
314 * Don't do anything for indirect draws.
315 */
316 if (sctx->b.chip_class <= VI &&
317 sctx->b.screen->info.max_se >= 4 &&
318 !info->indirect &&
319 info->instance_count > 1 && info->count < primgroup_size)
320 wd_switch_on_eop = true;
321
322 /* Required on CIK and later. */
323 if (sctx->b.screen->info.max_se > 2 && !wd_switch_on_eop)
324 ia_switch_on_eoi = true;
325
326 /* Required by Hawaii and, for some special cases, by VI. */
327 if (ia_switch_on_eoi &&
328 (sctx->b.family == CHIP_HAWAII ||
329 (sctx->b.chip_class == VI &&
330 (sctx->gs_shader.cso || max_primgroup_in_wave != 2))))
331 partial_vs_wave = true;
332
333 /* Instancing bug on Bonaire. */
334 if (sctx->b.family == CHIP_BONAIRE && ia_switch_on_eoi &&
335 (info->indirect || info->instance_count > 1))
336 partial_vs_wave = true;
337
338 /* If the WD switch is false, the IA switch must be false too. */
339 assert(wd_switch_on_eop || !ia_switch_on_eop);
340 }
341
342 /* If SWITCH_ON_EOI is set, PARTIAL_ES_WAVE must be set too. */
343 if (ia_switch_on_eoi)
344 partial_es_wave = true;
345
346 /* GS requirement. */
347 if (SI_GS_PER_ES / primgroup_size >= sctx->screen->gs_table_depth - 3)
348 partial_es_wave = true;
349
350 /* Hw bug with single-primitive instances and SWITCH_ON_EOI
351 * on multi-SE chips. */
352 if (sctx->b.screen->info.max_se >= 2 && ia_switch_on_eoi &&
353 (info->indirect ||
354 (info->instance_count > 1 &&
355 si_num_prims_for_vertices(info) <= 1)))
356 sctx->b.flags |= SI_CONTEXT_VGT_FLUSH;
357
358 return S_028AA8_SWITCH_ON_EOP(ia_switch_on_eop) |
359 S_028AA8_SWITCH_ON_EOI(ia_switch_on_eoi) |
360 S_028AA8_PARTIAL_VS_WAVE_ON(partial_vs_wave) |
361 S_028AA8_PARTIAL_ES_WAVE_ON(partial_es_wave) |
362 S_028AA8_PRIMGROUP_SIZE(primgroup_size - 1) |
363 S_028AA8_WD_SWITCH_ON_EOP(sctx->b.chip_class >= CIK ? wd_switch_on_eop : 0) |
364 S_028AA8_MAX_PRIMGRP_IN_WAVE(sctx->b.chip_class >= VI ?
365 max_primgroup_in_wave : 0);
366 }
367
368 static unsigned si_get_ls_hs_config(struct si_context *sctx,
369 const struct pipe_draw_info *info,
370 unsigned num_patches)
371 {
372 unsigned num_output_cp;
373
374 if (!sctx->tes_shader.cso)
375 return 0;
376
377 num_output_cp = sctx->tcs_shader.cso ?
378 sctx->tcs_shader.cso->info.properties[TGSI_PROPERTY_TCS_VERTICES_OUT] :
379 info->vertices_per_patch;
380
381 return S_028B58_NUM_PATCHES(num_patches) |
382 S_028B58_HS_NUM_INPUT_CP(info->vertices_per_patch) |
383 S_028B58_HS_NUM_OUTPUT_CP(num_output_cp);
384 }
385
386 static void si_emit_scratch_reloc(struct si_context *sctx)
387 {
388 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
389
390 if (!sctx->emit_scratch_reloc)
391 return;
392
393 radeon_set_context_reg(cs, R_0286E8_SPI_TMPRING_SIZE,
394 sctx->spi_tmpring_size);
395
396 if (sctx->scratch_buffer) {
397 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
398 sctx->scratch_buffer, RADEON_USAGE_READWRITE,
399 RADEON_PRIO_SCRATCH_BUFFER);
400
401 }
402 sctx->emit_scratch_reloc = false;
403 }
404
405 /* rast_prim is the primitive type after GS. */
406 static void si_emit_rasterizer_prim_state(struct si_context *sctx)
407 {
408 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
409 unsigned rast_prim = sctx->current_rast_prim;
410 struct si_state_rasterizer *rs = sctx->emitted.named.rasterizer;
411
412 /* Skip this if not rendering lines. */
413 if (rast_prim != PIPE_PRIM_LINES &&
414 rast_prim != PIPE_PRIM_LINE_LOOP &&
415 rast_prim != PIPE_PRIM_LINE_STRIP &&
416 rast_prim != PIPE_PRIM_LINES_ADJACENCY &&
417 rast_prim != PIPE_PRIM_LINE_STRIP_ADJACENCY)
418 return;
419
420 if (rast_prim == sctx->last_rast_prim &&
421 rs->pa_sc_line_stipple == sctx->last_sc_line_stipple)
422 return;
423
424 radeon_set_context_reg(cs, R_028A0C_PA_SC_LINE_STIPPLE,
425 rs->pa_sc_line_stipple |
426 S_028A0C_AUTO_RESET_CNTL(rast_prim == PIPE_PRIM_LINES ? 1 :
427 rast_prim == PIPE_PRIM_LINE_STRIP ? 2 : 0));
428
429 sctx->last_rast_prim = rast_prim;
430 sctx->last_sc_line_stipple = rs->pa_sc_line_stipple;
431 }
432
433 static void si_emit_draw_registers(struct si_context *sctx,
434 const struct pipe_draw_info *info)
435 {
436 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
437 unsigned prim = si_conv_pipe_prim(info->mode);
438 unsigned gs_out_prim = si_conv_prim_to_gs_out(sctx->current_rast_prim);
439 unsigned ia_multi_vgt_param, ls_hs_config, num_patches = 0;
440
441 if (sctx->tes_shader.cso)
442 si_emit_derived_tess_state(sctx, info, &num_patches);
443
444 ia_multi_vgt_param = si_get_ia_multi_vgt_param(sctx, info, num_patches);
445 ls_hs_config = si_get_ls_hs_config(sctx, info, num_patches);
446
447 /* Draw state. */
448 if (prim != sctx->last_prim ||
449 ia_multi_vgt_param != sctx->last_multi_vgt_param ||
450 ls_hs_config != sctx->last_ls_hs_config) {
451 if (sctx->b.family >= CHIP_POLARIS10) {
452 radeon_set_context_reg_idx(cs, R_028AA8_IA_MULTI_VGT_PARAM, 1, ia_multi_vgt_param);
453 radeon_set_context_reg_idx(cs, R_028B58_VGT_LS_HS_CONFIG, 2, ls_hs_config);
454 radeon_set_uconfig_reg_idx(cs, R_030908_VGT_PRIMITIVE_TYPE, 1, prim);
455 } else if (sctx->b.chip_class >= CIK) {
456 radeon_emit(cs, PKT3(PKT3_DRAW_PREAMBLE, 2, 0));
457 radeon_emit(cs, prim); /* VGT_PRIMITIVE_TYPE */
458 radeon_emit(cs, ia_multi_vgt_param); /* IA_MULTI_VGT_PARAM */
459 radeon_emit(cs, ls_hs_config); /* VGT_LS_HS_CONFIG */
460 } else {
461 radeon_set_config_reg(cs, R_008958_VGT_PRIMITIVE_TYPE, prim);
462 radeon_set_context_reg(cs, R_028AA8_IA_MULTI_VGT_PARAM, ia_multi_vgt_param);
463 radeon_set_context_reg(cs, R_028B58_VGT_LS_HS_CONFIG, ls_hs_config);
464 }
465
466 sctx->last_prim = prim;
467 sctx->last_multi_vgt_param = ia_multi_vgt_param;
468 sctx->last_ls_hs_config = ls_hs_config;
469 }
470
471 if (gs_out_prim != sctx->last_gs_out_prim) {
472 radeon_set_context_reg(cs, R_028A6C_VGT_GS_OUT_PRIM_TYPE, gs_out_prim);
473 sctx->last_gs_out_prim = gs_out_prim;
474 }
475
476 /* Primitive restart. */
477 if (info->primitive_restart != sctx->last_primitive_restart_en) {
478 radeon_set_context_reg(cs, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, info->primitive_restart);
479 sctx->last_primitive_restart_en = info->primitive_restart;
480
481 if (info->primitive_restart &&
482 (info->restart_index != sctx->last_restart_index ||
483 sctx->last_restart_index == SI_RESTART_INDEX_UNKNOWN)) {
484 radeon_set_context_reg(cs, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
485 info->restart_index);
486 sctx->last_restart_index = info->restart_index;
487 }
488 }
489 }
490
491 static void si_emit_draw_packets(struct si_context *sctx,
492 const struct pipe_draw_info *info,
493 const struct pipe_index_buffer *ib)
494 {
495 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
496 unsigned sh_base_reg = sctx->shader_userdata.sh_base[PIPE_SHADER_VERTEX];
497 bool render_cond_bit = sctx->b.render_cond && !sctx->b.render_cond_force_off;
498
499 if (info->count_from_stream_output) {
500 struct r600_so_target *t =
501 (struct r600_so_target*)info->count_from_stream_output;
502 uint64_t va = t->buf_filled_size->gpu_address +
503 t->buf_filled_size_offset;
504
505 radeon_set_context_reg(cs, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE,
506 t->stride_in_dw);
507
508 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
509 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
510 COPY_DATA_DST_SEL(COPY_DATA_REG) |
511 COPY_DATA_WR_CONFIRM);
512 radeon_emit(cs, va); /* src address lo */
513 radeon_emit(cs, va >> 32); /* src address hi */
514 radeon_emit(cs, R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE >> 2);
515 radeon_emit(cs, 0); /* unused */
516
517 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
518 t->buf_filled_size, RADEON_USAGE_READ,
519 RADEON_PRIO_SO_FILLED_SIZE);
520 }
521
522 /* draw packet */
523 if (info->indexed) {
524 radeon_emit(cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
525
526 /* index type */
527 switch (ib->index_size) {
528 case 1:
529 radeon_emit(cs, V_028A7C_VGT_INDEX_8);
530 break;
531 case 2:
532 radeon_emit(cs, V_028A7C_VGT_INDEX_16 |
533 (SI_BIG_ENDIAN && sctx->b.chip_class <= CIK ?
534 V_028A7C_VGT_DMA_SWAP_16_BIT : 0));
535 break;
536 case 4:
537 radeon_emit(cs, V_028A7C_VGT_INDEX_32 |
538 (SI_BIG_ENDIAN && sctx->b.chip_class <= CIK ?
539 V_028A7C_VGT_DMA_SWAP_32_BIT : 0));
540 break;
541 default:
542 assert(!"unreachable");
543 return;
544 }
545 }
546
547 if (!info->indirect) {
548 int base_vertex;
549
550 radeon_emit(cs, PKT3(PKT3_NUM_INSTANCES, 0, 0));
551 radeon_emit(cs, info->instance_count);
552
553 /* Base vertex and start instance. */
554 base_vertex = info->indexed ? info->index_bias : info->start;
555
556 if (base_vertex != sctx->last_base_vertex ||
557 sctx->last_base_vertex == SI_BASE_VERTEX_UNKNOWN ||
558 info->start_instance != sctx->last_start_instance ||
559 sh_base_reg != sctx->last_sh_base_reg) {
560 radeon_set_sh_reg_seq(cs, sh_base_reg + SI_SGPR_BASE_VERTEX * 4, 2);
561 radeon_emit(cs, base_vertex);
562 radeon_emit(cs, info->start_instance);
563
564 sctx->last_base_vertex = base_vertex;
565 sctx->last_start_instance = info->start_instance;
566 sctx->last_sh_base_reg = sh_base_reg;
567 }
568 } else {
569 si_invalidate_draw_sh_constants(sctx);
570
571 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
572 (struct r600_resource *)info->indirect,
573 RADEON_USAGE_READ, RADEON_PRIO_DRAW_INDIRECT);
574 }
575
576 if (info->indexed) {
577 uint32_t index_max_size = (ib->buffer->width0 - ib->offset) /
578 ib->index_size;
579 uint64_t index_va = r600_resource(ib->buffer)->gpu_address + ib->offset;
580
581 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
582 (struct r600_resource *)ib->buffer,
583 RADEON_USAGE_READ, RADEON_PRIO_INDEX_BUFFER);
584
585 if (info->indirect) {
586 uint64_t indirect_va = r600_resource(info->indirect)->gpu_address;
587
588 assert(indirect_va % 8 == 0);
589 assert(index_va % 2 == 0);
590 assert(info->indirect_offset % 4 == 0);
591
592 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
593 radeon_emit(cs, 1);
594 radeon_emit(cs, indirect_va);
595 radeon_emit(cs, indirect_va >> 32);
596
597 radeon_emit(cs, PKT3(PKT3_INDEX_BASE, 1, 0));
598 radeon_emit(cs, index_va);
599 radeon_emit(cs, index_va >> 32);
600
601 radeon_emit(cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
602 radeon_emit(cs, index_max_size);
603
604 if (sctx->b.family < CHIP_POLARIS10) {
605 radeon_emit(cs, PKT3(PKT3_DRAW_INDEX_INDIRECT, 3, render_cond_bit));
606 radeon_emit(cs, info->indirect_offset);
607 radeon_emit(cs, (sh_base_reg + SI_SGPR_BASE_VERTEX * 4 - SI_SH_REG_OFFSET) >> 2);
608 radeon_emit(cs, (sh_base_reg + SI_SGPR_START_INSTANCE * 4 - SI_SH_REG_OFFSET) >> 2);
609 radeon_emit(cs, V_0287F0_DI_SRC_SEL_DMA);
610 } else {
611 radeon_emit(cs, PKT3(PKT3_DRAW_INDEX_INDIRECT_MULTI, 8, render_cond_bit));
612 radeon_emit(cs, info->indirect_offset);
613 radeon_emit(cs, (sh_base_reg + SI_SGPR_BASE_VERTEX * 4 - SI_SH_REG_OFFSET) >> 2);
614 radeon_emit(cs, (sh_base_reg + SI_SGPR_START_INSTANCE * 4 - SI_SH_REG_OFFSET) >> 2);
615 radeon_emit(cs, 0); /* draw_index */
616 radeon_emit(cs, 1); /* count */
617 radeon_emit(cs, 0); /* count_addr -- disabled */
618 radeon_emit(cs, 0);
619 radeon_emit(cs, 16); /* stride */
620 radeon_emit(cs, V_0287F0_DI_SRC_SEL_DMA);
621 }
622 } else {
623 index_va += info->start * ib->index_size;
624
625 radeon_emit(cs, PKT3(PKT3_DRAW_INDEX_2, 4, render_cond_bit));
626 radeon_emit(cs, index_max_size);
627 radeon_emit(cs, index_va);
628 radeon_emit(cs, (index_va >> 32UL) & 0xFF);
629 radeon_emit(cs, info->count);
630 radeon_emit(cs, V_0287F0_DI_SRC_SEL_DMA);
631 }
632 } else {
633 if (info->indirect) {
634 uint64_t indirect_va = r600_resource(info->indirect)->gpu_address;
635
636 assert(indirect_va % 8 == 0);
637 assert(info->indirect_offset % 4 == 0);
638
639 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
640 radeon_emit(cs, 1);
641 radeon_emit(cs, indirect_va);
642 radeon_emit(cs, indirect_va >> 32);
643
644 if (sctx->b.family < CHIP_POLARIS10) {
645 radeon_emit(cs, PKT3(PKT3_DRAW_INDIRECT, 3, render_cond_bit));
646 radeon_emit(cs, info->indirect_offset);
647 radeon_emit(cs, (sh_base_reg + SI_SGPR_BASE_VERTEX * 4 - SI_SH_REG_OFFSET) >> 2);
648 radeon_emit(cs, (sh_base_reg + SI_SGPR_START_INSTANCE * 4 - SI_SH_REG_OFFSET) >> 2);
649 radeon_emit(cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX);
650 } else {
651 radeon_emit(cs, PKT3(PKT3_DRAW_INDIRECT_MULTI, 8, render_cond_bit));
652 radeon_emit(cs, info->indirect_offset);
653 radeon_emit(cs, (sh_base_reg + SI_SGPR_BASE_VERTEX * 4 - SI_SH_REG_OFFSET) >> 2);
654 radeon_emit(cs, (sh_base_reg + SI_SGPR_START_INSTANCE * 4 - SI_SH_REG_OFFSET) >> 2);
655 radeon_emit(cs, 0); /* draw_index */
656 radeon_emit(cs, 1); /* count */
657 radeon_emit(cs, 0); /* count_addr -- disabled */
658 radeon_emit(cs, 0);
659 radeon_emit(cs, 16); /* stride */
660 radeon_emit(cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX);
661 }
662 } else {
663 radeon_emit(cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, render_cond_bit));
664 radeon_emit(cs, info->count);
665 radeon_emit(cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
666 S_0287F0_USE_OPAQUE(!!info->count_from_stream_output));
667 }
668 }
669 }
670
671 void si_emit_cache_flush(struct si_context *si_ctx, struct r600_atom *atom)
672 {
673 struct r600_common_context *sctx = &si_ctx->b;
674 struct radeon_winsys_cs *cs = sctx->gfx.cs;
675 uint32_t cp_coher_cntl = 0;
676
677 /* SI has a bug that it always flushes ICACHE and KCACHE if either
678 * bit is set. An alternative way is to write SQC_CACHES, but that
679 * doesn't seem to work reliably. Since the bug doesn't affect
680 * correctness (it only does more work than necessary) and
681 * the performance impact is likely negligible, there is no plan
682 * to add a workaround for it.
683 */
684
685 if (sctx->flags & SI_CONTEXT_INV_ICACHE)
686 cp_coher_cntl |= S_0085F0_SH_ICACHE_ACTION_ENA(1);
687 if (sctx->flags & SI_CONTEXT_INV_SMEM_L1)
688 cp_coher_cntl |= S_0085F0_SH_KCACHE_ACTION_ENA(1);
689
690 if (sctx->flags & SI_CONTEXT_INV_VMEM_L1)
691 cp_coher_cntl |= S_0085F0_TCL1_ACTION_ENA(1);
692 if (sctx->flags & SI_CONTEXT_INV_GLOBAL_L2) {
693 cp_coher_cntl |= S_0085F0_TC_ACTION_ENA(1);
694
695 if (sctx->chip_class >= VI)
696 cp_coher_cntl |= S_0301F0_TC_WB_ACTION_ENA(1);
697 }
698
699 if (sctx->flags & SI_CONTEXT_FLUSH_AND_INV_CB) {
700 cp_coher_cntl |= S_0085F0_CB_ACTION_ENA(1) |
701 S_0085F0_CB0_DEST_BASE_ENA(1) |
702 S_0085F0_CB1_DEST_BASE_ENA(1) |
703 S_0085F0_CB2_DEST_BASE_ENA(1) |
704 S_0085F0_CB3_DEST_BASE_ENA(1) |
705 S_0085F0_CB4_DEST_BASE_ENA(1) |
706 S_0085F0_CB5_DEST_BASE_ENA(1) |
707 S_0085F0_CB6_DEST_BASE_ENA(1) |
708 S_0085F0_CB7_DEST_BASE_ENA(1);
709
710 /* Necessary for DCC */
711 if (sctx->chip_class >= VI) {
712 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, 0));
713 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_DATA_TS) |
714 EVENT_INDEX(5));
715 radeon_emit(cs, 0);
716 radeon_emit(cs, 0);
717 radeon_emit(cs, 0);
718 radeon_emit(cs, 0);
719 }
720 }
721 if (sctx->flags & SI_CONTEXT_FLUSH_AND_INV_DB) {
722 cp_coher_cntl |= S_0085F0_DB_ACTION_ENA(1) |
723 S_0085F0_DB_DEST_BASE_ENA(1);
724 }
725
726 if (sctx->flags & SI_CONTEXT_FLUSH_AND_INV_CB_META) {
727 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
728 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_META) | EVENT_INDEX(0));
729 /* needed for wait for idle in SURFACE_SYNC */
730 assert(sctx->flags & SI_CONTEXT_FLUSH_AND_INV_CB);
731 }
732 if (sctx->flags & SI_CONTEXT_FLUSH_AND_INV_DB_META) {
733 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
734 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_DB_META) | EVENT_INDEX(0));
735 /* needed for wait for idle in SURFACE_SYNC */
736 assert(sctx->flags & SI_CONTEXT_FLUSH_AND_INV_DB);
737 }
738
739 /* Wait for shader engines to go idle.
740 * VS and PS waits are unnecessary if SURFACE_SYNC is going to wait
741 * for everything including CB/DB cache flushes.
742 */
743 if (!(sctx->flags & (SI_CONTEXT_FLUSH_AND_INV_CB |
744 SI_CONTEXT_FLUSH_AND_INV_DB))) {
745 if (sctx->flags & SI_CONTEXT_PS_PARTIAL_FLUSH) {
746 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
747 radeon_emit(cs, EVENT_TYPE(V_028A90_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
748 } else if (sctx->flags & SI_CONTEXT_VS_PARTIAL_FLUSH) {
749 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
750 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
751 }
752 }
753 if (sctx->flags & SI_CONTEXT_CS_PARTIAL_FLUSH) {
754 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
755 radeon_emit(cs, EVENT_TYPE(V_028A90_CS_PARTIAL_FLUSH | EVENT_INDEX(4)));
756 }
757
758 /* VGT state synchronization. */
759 if (sctx->flags & SI_CONTEXT_VGT_FLUSH) {
760 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
761 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
762 }
763 if (sctx->flags & SI_CONTEXT_VGT_STREAMOUT_SYNC) {
764 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
765 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_STREAMOUT_SYNC) | EVENT_INDEX(0));
766 }
767
768 /* Make sure ME is idle (it executes most packets) before continuing.
769 * This prevents read-after-write hazards between PFP and ME.
770 */
771 if (cp_coher_cntl || (sctx->flags & SI_CONTEXT_CS_PARTIAL_FLUSH)) {
772 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
773 radeon_emit(cs, 0);
774 }
775
776 /* When one of the DEST_BASE flags is set, SURFACE_SYNC waits for idle.
777 * Therefore, it should be last. Done in PFP.
778 */
779 if (cp_coher_cntl) {
780 /* ACQUIRE_MEM is only required on a compute ring. */
781 radeon_emit(cs, PKT3(PKT3_SURFACE_SYNC, 3, 0));
782 radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */
783 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
784 radeon_emit(cs, 0); /* CP_COHER_BASE */
785 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
786 }
787
788 if (sctx->flags & R600_CONTEXT_START_PIPELINE_STATS) {
789 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
790 radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_START) |
791 EVENT_INDEX(0));
792 } else if (sctx->flags & R600_CONTEXT_STOP_PIPELINE_STATS) {
793 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
794 radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_STOP) |
795 EVENT_INDEX(0));
796 }
797
798 sctx->flags = 0;
799 }
800
801 static void si_get_draw_start_count(struct si_context *sctx,
802 const struct pipe_draw_info *info,
803 unsigned *start, unsigned *count)
804 {
805 if (info->indirect) {
806 struct r600_resource *indirect =
807 (struct r600_resource*)info->indirect;
808 int *data = r600_buffer_map_sync_with_rings(&sctx->b,
809 indirect, PIPE_TRANSFER_READ);
810 data += info->indirect_offset/sizeof(int);
811 *start = data[2];
812 *count = data[0];
813 } else {
814 *start = info->start;
815 *count = info->count;
816 }
817 }
818
819 void si_ce_pre_draw_synchronization(struct si_context *sctx)
820 {
821 if (sctx->ce_need_synchronization) {
822 radeon_emit(sctx->ce_ib, PKT3(PKT3_INCREMENT_CE_COUNTER, 0, 0));
823 radeon_emit(sctx->ce_ib, 1);
824
825 radeon_emit(sctx->b.gfx.cs, PKT3(PKT3_WAIT_ON_CE_COUNTER, 0, 0));
826 radeon_emit(sctx->b.gfx.cs, 1);
827 }
828 }
829
830 void si_ce_post_draw_synchronization(struct si_context *sctx)
831 {
832 if (sctx->ce_need_synchronization) {
833 radeon_emit(sctx->b.gfx.cs, PKT3(PKT3_INCREMENT_DE_COUNTER, 0, 0));
834 radeon_emit(sctx->b.gfx.cs, 0);
835
836 sctx->ce_need_synchronization = false;
837 }
838 }
839
840 void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info)
841 {
842 struct si_context *sctx = (struct si_context *)ctx;
843 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
844 struct pipe_index_buffer ib = {};
845 unsigned mask, dirty_fb_counter, dirty_tex_counter;
846
847 if (!info->count && !info->indirect &&
848 (info->indexed || !info->count_from_stream_output))
849 return;
850
851 if (!sctx->vs_shader.cso) {
852 assert(0);
853 return;
854 }
855 if (!sctx->ps_shader.cso && (!rs || !rs->rasterizer_discard)) {
856 assert(0);
857 return;
858 }
859 if (!!sctx->tes_shader.cso != (info->mode == PIPE_PRIM_PATCHES)) {
860 assert(0);
861 return;
862 }
863
864 /* Re-emit the framebuffer state if needed. */
865 dirty_fb_counter = p_atomic_read(&sctx->b.screen->dirty_fb_counter);
866 if (dirty_fb_counter != sctx->b.last_dirty_fb_counter) {
867 sctx->b.last_dirty_fb_counter = dirty_fb_counter;
868 sctx->framebuffer.dirty_cbufs |=
869 ((1 << sctx->framebuffer.state.nr_cbufs) - 1);
870 sctx->framebuffer.dirty_zsbuf = true;
871 si_mark_atom_dirty(sctx, &sctx->framebuffer.atom);
872 }
873
874 /* Invalidate & recompute texture descriptors if needed. */
875 dirty_tex_counter = p_atomic_read(&sctx->b.screen->dirty_tex_descriptor_counter);
876 if (dirty_tex_counter != sctx->b.last_dirty_tex_descriptor_counter) {
877 sctx->b.last_dirty_tex_descriptor_counter = dirty_tex_counter;
878 si_update_all_texture_descriptors(sctx);
879 }
880
881 si_decompress_graphics_textures(sctx);
882
883 /* Set the rasterization primitive type.
884 *
885 * This must be done after si_decompress_textures, which can call
886 * draw_vbo recursively, and before si_update_shaders, which uses
887 * current_rast_prim for this draw_vbo call. */
888 if (sctx->gs_shader.cso)
889 sctx->current_rast_prim = sctx->gs_shader.cso->gs_output_prim;
890 else if (sctx->tes_shader.cso)
891 sctx->current_rast_prim =
892 sctx->tes_shader.cso->info.properties[TGSI_PROPERTY_TES_PRIM_MODE];
893 else
894 sctx->current_rast_prim = info->mode;
895
896 if (!si_update_shaders(sctx) ||
897 !si_upload_graphics_shader_descriptors(sctx))
898 return;
899
900 if (info->indexed) {
901 /* Initialize the index buffer struct. */
902 pipe_resource_reference(&ib.buffer, sctx->index_buffer.buffer);
903 ib.user_buffer = sctx->index_buffer.user_buffer;
904 ib.index_size = sctx->index_buffer.index_size;
905 ib.offset = sctx->index_buffer.offset;
906
907 /* Translate or upload, if needed. */
908 /* 8-bit indices are supported on VI. */
909 if (sctx->b.chip_class <= CIK && ib.index_size == 1) {
910 struct pipe_resource *out_buffer = NULL;
911 unsigned out_offset, start, count, start_offset;
912 void *ptr;
913
914 si_get_draw_start_count(sctx, info, &start, &count);
915 start_offset = start * ib.index_size;
916
917 u_upload_alloc(sctx->b.uploader, start_offset, count * 2, 256,
918 &out_offset, &out_buffer, &ptr);
919 if (!out_buffer) {
920 pipe_resource_reference(&ib.buffer, NULL);
921 return;
922 }
923
924 util_shorten_ubyte_elts_to_userptr(&sctx->b.b, &ib, 0,
925 ib.offset + start_offset,
926 count, ptr);
927
928 pipe_resource_reference(&ib.buffer, NULL);
929 ib.user_buffer = NULL;
930 ib.buffer = out_buffer;
931 /* info->start will be added by the drawing code */
932 ib.offset = out_offset - start_offset;
933 ib.index_size = 2;
934 } else if (ib.user_buffer && !ib.buffer) {
935 unsigned start, count, start_offset;
936
937 si_get_draw_start_count(sctx, info, &start, &count);
938 start_offset = start * ib.index_size;
939
940 u_upload_data(sctx->b.uploader, start_offset, count * ib.index_size,
941 256, (char*)ib.user_buffer + start_offset,
942 &ib.offset, &ib.buffer);
943 if (!ib.buffer)
944 return;
945 /* info->start will be added by the drawing code */
946 ib.offset -= start_offset;
947 }
948 }
949
950 /* VI reads index buffers through TC L2. */
951 if (info->indexed && sctx->b.chip_class <= CIK &&
952 r600_resource(ib.buffer)->TC_L2_dirty) {
953 sctx->b.flags |= SI_CONTEXT_INV_GLOBAL_L2;
954 r600_resource(ib.buffer)->TC_L2_dirty = false;
955 }
956
957 /* Check flush flags. */
958 if (sctx->b.flags)
959 si_mark_atom_dirty(sctx, sctx->atoms.s.cache_flush);
960
961 si_need_cs_space(sctx);
962
963 /* Emit states. */
964 mask = sctx->dirty_atoms;
965 while (mask) {
966 struct r600_atom *atom = sctx->atoms.array[u_bit_scan(&mask)];
967
968 atom->emit(&sctx->b, atom);
969 }
970 sctx->dirty_atoms = 0;
971
972 si_pm4_emit_dirty(sctx);
973 si_emit_scratch_reloc(sctx);
974 si_emit_rasterizer_prim_state(sctx);
975 si_emit_draw_registers(sctx, info);
976
977 si_ce_pre_draw_synchronization(sctx);
978
979 si_emit_draw_packets(sctx, info, &ib);
980
981 si_ce_post_draw_synchronization(sctx);
982
983 if (sctx->trace_buf)
984 si_trace_emit(sctx);
985
986 /* Workaround for a VGT hang when streamout is enabled.
987 * It must be done after drawing. */
988 if ((sctx->b.family == CHIP_HAWAII ||
989 sctx->b.family == CHIP_TONGA ||
990 sctx->b.family == CHIP_FIJI) &&
991 r600_get_strmout_en(&sctx->b)) {
992 sctx->b.flags |= SI_CONTEXT_VGT_STREAMOUT_SYNC;
993 }
994
995 /* Set the depth buffer as dirty. */
996 if (sctx->framebuffer.state.zsbuf) {
997 struct pipe_surface *surf = sctx->framebuffer.state.zsbuf;
998 struct r600_texture *rtex = (struct r600_texture *)surf->texture;
999
1000 rtex->dirty_level_mask |= 1 << surf->u.tex.level;
1001
1002 if (rtex->surface.flags & RADEON_SURF_SBUFFER)
1003 rtex->stencil_dirty_level_mask |= 1 << surf->u.tex.level;
1004 }
1005 if (sctx->framebuffer.compressed_cb_mask) {
1006 struct pipe_surface *surf;
1007 struct r600_texture *rtex;
1008 unsigned mask = sctx->framebuffer.compressed_cb_mask;
1009
1010 do {
1011 unsigned i = u_bit_scan(&mask);
1012 surf = sctx->framebuffer.state.cbufs[i];
1013 rtex = (struct r600_texture*)surf->texture;
1014
1015 rtex->dirty_level_mask |= 1 << surf->u.tex.level;
1016 } while (mask);
1017 }
1018
1019 pipe_resource_reference(&ib.buffer, NULL);
1020 sctx->b.num_draw_calls++;
1021 if (G_0286E8_WAVESIZE(sctx->spi_tmpring_size))
1022 sctx->b.num_spill_draw_calls++;
1023 }
1024
1025 void si_trace_emit(struct si_context *sctx)
1026 {
1027 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
1028
1029 sctx->trace_id++;
1030 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, sctx->trace_buf,
1031 RADEON_USAGE_READWRITE, RADEON_PRIO_TRACE);
1032 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
1033 radeon_emit(cs, S_370_DST_SEL(V_370_MEMORY_SYNC) |
1034 S_370_WR_CONFIRM(1) |
1035 S_370_ENGINE_SEL(V_370_ME));
1036 radeon_emit(cs, sctx->trace_buf->gpu_address);
1037 radeon_emit(cs, sctx->trace_buf->gpu_address >> 32);
1038 radeon_emit(cs, sctx->trace_id);
1039 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1040 radeon_emit(cs, SI_ENCODE_TRACE_POINT(sctx->trace_id));
1041 }