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7ccfb58d702ca377249dcc9cc77ed9532f725a21
[mesa.git] / src / gallium / drivers / radeonsi / si_state_draw.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Christian König <christian.koenig@amd.com>
25 */
26
27 #include "si_pipe.h"
28 #include "si_shader.h"
29 #include "../radeon/r600_cs.h"
30 #include "sid.h"
31
32 #include "util/u_blitter.h"
33 #include "util/u_format.h"
34 #include "util/u_index_modify.h"
35 #include "util/u_memory.h"
36 #include "util/u_upload_mgr.h"
37
38 /*
39 * Shaders
40 */
41
42 static void si_pipe_shader_es(struct pipe_context *ctx, struct si_pipe_shader *shader)
43 {
44 struct si_context *sctx = (struct si_context *)ctx;
45 struct si_pm4_state *pm4;
46 unsigned num_sgprs, num_user_sgprs;
47 unsigned vgpr_comp_cnt;
48 uint64_t va;
49
50 si_pm4_delete_state(sctx, es, shader->pm4);
51 pm4 = shader->pm4 = si_pm4_alloc_state(sctx);
52
53 if (pm4 == NULL)
54 return;
55
56 va = r600_resource_va(ctx->screen, (void *)shader->bo);
57 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ);
58
59 vgpr_comp_cnt = shader->shader.uses_instanceid ? 3 : 0;
60
61 num_user_sgprs = SI_VS_NUM_USER_SGPR;
62 num_sgprs = shader->num_sgprs;
63 /* One SGPR after user SGPRs is pre-loaded with es2gs_offset */
64 if ((num_user_sgprs + 1) > num_sgprs) {
65 /* Last 2 reserved SGPRs are used for VCC */
66 num_sgprs = num_user_sgprs + 1 + 2;
67 }
68 assert(num_sgprs <= 104);
69
70 si_pm4_set_reg(pm4, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8);
71 si_pm4_set_reg(pm4, R_00B324_SPI_SHADER_PGM_HI_ES, va >> 40);
72 si_pm4_set_reg(pm4, R_00B328_SPI_SHADER_PGM_RSRC1_ES,
73 S_00B328_VGPRS((shader->num_vgprs - 1) / 4) |
74 S_00B328_SGPRS((num_sgprs - 1) / 8) |
75 S_00B328_VGPR_COMP_CNT(vgpr_comp_cnt));
76 si_pm4_set_reg(pm4, R_00B32C_SPI_SHADER_PGM_RSRC2_ES,
77 S_00B32C_USER_SGPR(num_user_sgprs));
78
79 sctx->b.flags |= R600_CONTEXT_INV_SHADER_CACHE;
80 }
81
82 static void si_pipe_shader_gs(struct pipe_context *ctx, struct si_pipe_shader *shader)
83 {
84 struct si_context *sctx = (struct si_context *)ctx;
85 unsigned gs_vert_itemsize = shader->shader.noutput * (16 >> 2);
86 unsigned gs_max_vert_out = shader->shader.gs_max_out_vertices;
87 unsigned gsvs_itemsize = gs_vert_itemsize * gs_max_vert_out;
88 unsigned cut_mode;
89 struct si_pm4_state *pm4;
90 unsigned num_sgprs, num_user_sgprs;
91 uint64_t va;
92
93 /* The GSVS_RING_ITEMSIZE register takes 15 bits */
94 assert(gsvs_itemsize < (1 << 15));
95
96 si_pm4_delete_state(sctx, gs, shader->pm4);
97 pm4 = shader->pm4 = si_pm4_alloc_state(sctx);
98
99 if (pm4 == NULL)
100 return;
101
102 if (gs_max_vert_out <= 128) {
103 cut_mode = V_028A40_GS_CUT_128;
104 } else if (gs_max_vert_out <= 256) {
105 cut_mode = V_028A40_GS_CUT_256;
106 } else if (gs_max_vert_out <= 512) {
107 cut_mode = V_028A40_GS_CUT_512;
108 } else {
109 assert(gs_max_vert_out <= 1024);
110 cut_mode = V_028A40_GS_CUT_1024;
111 }
112
113 si_pm4_set_reg(pm4, R_028A40_VGT_GS_MODE,
114 S_028A40_MODE(V_028A40_GS_SCENARIO_G) |
115 S_028A40_CUT_MODE(cut_mode)|
116 S_028A40_ES_WRITE_OPTIMIZE(1) |
117 S_028A40_GS_WRITE_OPTIMIZE(1));
118
119 si_pm4_set_reg(pm4, R_028A60_VGT_GSVS_RING_OFFSET_1, gsvs_itemsize);
120 si_pm4_set_reg(pm4, R_028A64_VGT_GSVS_RING_OFFSET_2, gsvs_itemsize);
121 si_pm4_set_reg(pm4, R_028A68_VGT_GSVS_RING_OFFSET_3, gsvs_itemsize);
122
123 si_pm4_set_reg(pm4, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
124 shader->shader.nparam * (16 >> 2));
125 si_pm4_set_reg(pm4, R_028AB0_VGT_GSVS_RING_ITEMSIZE, gsvs_itemsize);
126
127 si_pm4_set_reg(pm4, R_028B38_VGT_GS_MAX_VERT_OUT, gs_max_vert_out);
128
129 si_pm4_set_reg(pm4, R_028B5C_VGT_GS_VERT_ITEMSIZE, gs_vert_itemsize);
130
131 va = r600_resource_va(ctx->screen, (void *)shader->bo);
132 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ);
133 si_pm4_set_reg(pm4, R_00B220_SPI_SHADER_PGM_LO_GS, va >> 8);
134 si_pm4_set_reg(pm4, R_00B224_SPI_SHADER_PGM_HI_GS, va >> 40);
135
136 num_user_sgprs = SI_GS_NUM_USER_SGPR;
137 num_sgprs = shader->num_sgprs;
138 /* Two SGPRs after user SGPRs are pre-loaded with gs2vs_offset, gs_wave_id */
139 if ((num_user_sgprs + 2) > num_sgprs) {
140 /* Last 2 reserved SGPRs are used for VCC */
141 num_sgprs = num_user_sgprs + 2 + 2;
142 }
143 assert(num_sgprs <= 104);
144
145 si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS,
146 S_00B228_VGPRS((shader->num_vgprs - 1) / 4) |
147 S_00B228_SGPRS((num_sgprs - 1) / 8));
148 si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS,
149 S_00B22C_USER_SGPR(num_user_sgprs));
150
151 sctx->b.flags |= R600_CONTEXT_INV_SHADER_CACHE;
152 }
153
154 static void si_pipe_shader_vs(struct pipe_context *ctx, struct si_pipe_shader *shader)
155 {
156 struct si_context *sctx = (struct si_context *)ctx;
157 struct si_pm4_state *pm4;
158 unsigned num_sgprs, num_user_sgprs;
159 unsigned nparams, i, vgpr_comp_cnt;
160 uint64_t va;
161
162 si_pm4_delete_state(sctx, vs, shader->pm4);
163 pm4 = shader->pm4 = si_pm4_alloc_state(sctx);
164
165 if (pm4 == NULL)
166 return;
167
168 va = r600_resource_va(ctx->screen, (void *)shader->bo);
169 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ);
170
171 vgpr_comp_cnt = shader->shader.uses_instanceid ? 3 : 0;
172
173 num_user_sgprs = SI_VS_NUM_USER_SGPR;
174 num_sgprs = shader->num_sgprs;
175 if (num_user_sgprs > num_sgprs) {
176 /* Last 2 reserved SGPRs are used for VCC */
177 num_sgprs = num_user_sgprs + 2;
178 }
179 assert(num_sgprs <= 104);
180
181 /* Certain attributes (position, psize, etc.) don't count as params.
182 * VS is required to export at least one param and r600_shader_from_tgsi()
183 * takes care of adding a dummy export.
184 */
185 for (nparams = 0, i = 0 ; i < shader->shader.noutput; i++) {
186 switch (shader->shader.output[i].name) {
187 case TGSI_SEMANTIC_CLIPVERTEX:
188 case TGSI_SEMANTIC_POSITION:
189 case TGSI_SEMANTIC_PSIZE:
190 break;
191 default:
192 nparams++;
193 }
194 }
195 if (nparams < 1)
196 nparams = 1;
197
198 si_pm4_set_reg(pm4, R_0286C4_SPI_VS_OUT_CONFIG,
199 S_0286C4_VS_EXPORT_COUNT(nparams - 1));
200
201 si_pm4_set_reg(pm4, R_02870C_SPI_SHADER_POS_FORMAT,
202 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
203 S_02870C_POS1_EXPORT_FORMAT(shader->shader.nr_pos_exports > 1 ?
204 V_02870C_SPI_SHADER_4COMP :
205 V_02870C_SPI_SHADER_NONE) |
206 S_02870C_POS2_EXPORT_FORMAT(shader->shader.nr_pos_exports > 2 ?
207 V_02870C_SPI_SHADER_4COMP :
208 V_02870C_SPI_SHADER_NONE) |
209 S_02870C_POS3_EXPORT_FORMAT(shader->shader.nr_pos_exports > 3 ?
210 V_02870C_SPI_SHADER_4COMP :
211 V_02870C_SPI_SHADER_NONE));
212
213 si_pm4_set_reg(pm4, R_00B120_SPI_SHADER_PGM_LO_VS, va >> 8);
214 si_pm4_set_reg(pm4, R_00B124_SPI_SHADER_PGM_HI_VS, va >> 40);
215 si_pm4_set_reg(pm4, R_00B128_SPI_SHADER_PGM_RSRC1_VS,
216 S_00B128_VGPRS((shader->num_vgprs - 1) / 4) |
217 S_00B128_SGPRS((num_sgprs - 1) / 8) |
218 S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt));
219 si_pm4_set_reg(pm4, R_00B12C_SPI_SHADER_PGM_RSRC2_VS,
220 S_00B12C_USER_SGPR(num_user_sgprs) |
221 S_00B12C_SO_BASE0_EN(!!shader->selector->so.stride[0]) |
222 S_00B12C_SO_BASE1_EN(!!shader->selector->so.stride[1]) |
223 S_00B12C_SO_BASE2_EN(!!shader->selector->so.stride[2]) |
224 S_00B12C_SO_BASE3_EN(!!shader->selector->so.stride[3]) |
225 S_00B12C_SO_EN(!!shader->selector->so.num_outputs));
226
227 sctx->b.flags |= R600_CONTEXT_INV_SHADER_CACHE;
228 }
229
230 static void si_pipe_shader_ps(struct pipe_context *ctx, struct si_pipe_shader *shader)
231 {
232 struct si_context *sctx = (struct si_context *)ctx;
233 struct si_pm4_state *pm4;
234 unsigned i, exports_ps, spi_ps_in_control, db_shader_control;
235 unsigned num_sgprs, num_user_sgprs;
236 unsigned spi_baryc_cntl = 0, spi_ps_input_ena, spi_shader_z_format;
237 uint64_t va;
238
239 si_pm4_delete_state(sctx, ps, shader->pm4);
240 pm4 = shader->pm4 = si_pm4_alloc_state(sctx);
241
242 if (pm4 == NULL)
243 return;
244
245 db_shader_control = S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z) |
246 S_02880C_ALPHA_TO_MASK_DISABLE(sctx->fb_cb0_is_integer);
247
248 for (i = 0; i < shader->shader.ninput; i++) {
249 switch (shader->shader.input[i].name) {
250 case TGSI_SEMANTIC_POSITION:
251 if (shader->shader.input[i].centroid) {
252 /* SPI_BARYC_CNTL.POS_FLOAT_LOCATION
253 * Possible vaules:
254 * 0 -> Position = pixel center (default)
255 * 1 -> Position = pixel centroid
256 * 2 -> Position = iterated sample number XXX:
257 * What does this mean?
258 */
259 spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(1);
260 }
261 /* Fall through */
262 case TGSI_SEMANTIC_FACE:
263 continue;
264 }
265 }
266
267 for (i = 0; i < shader->shader.noutput; i++) {
268 if (shader->shader.output[i].name == TGSI_SEMANTIC_POSITION)
269 db_shader_control |= S_02880C_Z_EXPORT_ENABLE(1);
270 if (shader->shader.output[i].name == TGSI_SEMANTIC_STENCIL)
271 db_shader_control |= S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(1);
272 }
273 if (shader->shader.uses_kill || shader->key.ps.alpha_func != PIPE_FUNC_ALWAYS)
274 db_shader_control |= S_02880C_KILL_ENABLE(1);
275
276 exports_ps = 0;
277 for (i = 0; i < shader->shader.noutput; i++) {
278 if (shader->shader.output[i].name == TGSI_SEMANTIC_POSITION ||
279 shader->shader.output[i].name == TGSI_SEMANTIC_STENCIL)
280 exports_ps |= 1;
281 }
282 if (!exports_ps) {
283 /* always at least export 1 component per pixel */
284 exports_ps = 2;
285 }
286
287 spi_ps_in_control = S_0286D8_NUM_INTERP(shader->shader.nparam) |
288 S_0286D8_BC_OPTIMIZE_DISABLE(1);
289
290 si_pm4_set_reg(pm4, R_0286E0_SPI_BARYC_CNTL, spi_baryc_cntl);
291 spi_ps_input_ena = shader->spi_ps_input_ena;
292 /* we need to enable at least one of them, otherwise we hang the GPU */
293 assert(G_0286CC_PERSP_SAMPLE_ENA(spi_ps_input_ena) ||
294 G_0286CC_PERSP_CENTER_ENA(spi_ps_input_ena) ||
295 G_0286CC_PERSP_CENTROID_ENA(spi_ps_input_ena) ||
296 G_0286CC_PERSP_PULL_MODEL_ENA(spi_ps_input_ena) ||
297 G_0286CC_LINEAR_SAMPLE_ENA(spi_ps_input_ena) ||
298 G_0286CC_LINEAR_CENTER_ENA(spi_ps_input_ena) ||
299 G_0286CC_LINEAR_CENTROID_ENA(spi_ps_input_ena) ||
300 G_0286CC_LINE_STIPPLE_TEX_ENA(spi_ps_input_ena));
301
302 si_pm4_set_reg(pm4, R_0286CC_SPI_PS_INPUT_ENA, spi_ps_input_ena);
303 si_pm4_set_reg(pm4, R_0286D0_SPI_PS_INPUT_ADDR, spi_ps_input_ena);
304 si_pm4_set_reg(pm4, R_0286D8_SPI_PS_IN_CONTROL, spi_ps_in_control);
305
306 if (G_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(db_shader_control))
307 spi_shader_z_format = V_028710_SPI_SHADER_32_GR;
308 else if (G_02880C_Z_EXPORT_ENABLE(db_shader_control))
309 spi_shader_z_format = V_028710_SPI_SHADER_32_R;
310 else
311 spi_shader_z_format = 0;
312 si_pm4_set_reg(pm4, R_028710_SPI_SHADER_Z_FORMAT, spi_shader_z_format);
313 si_pm4_set_reg(pm4, R_028714_SPI_SHADER_COL_FORMAT,
314 shader->spi_shader_col_format);
315 si_pm4_set_reg(pm4, R_02823C_CB_SHADER_MASK, shader->cb_shader_mask);
316
317 va = r600_resource_va(ctx->screen, (void *)shader->bo);
318 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ);
319 si_pm4_set_reg(pm4, R_00B020_SPI_SHADER_PGM_LO_PS, va >> 8);
320 si_pm4_set_reg(pm4, R_00B024_SPI_SHADER_PGM_HI_PS, va >> 40);
321
322 num_user_sgprs = SI_PS_NUM_USER_SGPR;
323 num_sgprs = shader->num_sgprs;
324 /* One SGPR after user SGPRs is pre-loaded with {prim_mask, lds_offset} */
325 if ((num_user_sgprs + 1) > num_sgprs) {
326 /* Last 2 reserved SGPRs are used for VCC */
327 num_sgprs = num_user_sgprs + 1 + 2;
328 }
329 assert(num_sgprs <= 104);
330
331 si_pm4_set_reg(pm4, R_00B028_SPI_SHADER_PGM_RSRC1_PS,
332 S_00B028_VGPRS((shader->num_vgprs - 1) / 4) |
333 S_00B028_SGPRS((num_sgprs - 1) / 8));
334 si_pm4_set_reg(pm4, R_00B02C_SPI_SHADER_PGM_RSRC2_PS,
335 S_00B02C_EXTRA_LDS_SIZE(shader->lds_size) |
336 S_00B02C_USER_SGPR(num_user_sgprs));
337
338 si_pm4_set_reg(pm4, R_02880C_DB_SHADER_CONTROL, db_shader_control);
339
340 shader->cb0_is_integer = sctx->fb_cb0_is_integer;
341 shader->sprite_coord_enable = sctx->sprite_coord_enable;
342 sctx->b.flags |= R600_CONTEXT_INV_SHADER_CACHE;
343 }
344
345 /*
346 * Drawing
347 */
348
349 static unsigned si_conv_pipe_prim(unsigned pprim)
350 {
351 static const unsigned prim_conv[] = {
352 [PIPE_PRIM_POINTS] = V_008958_DI_PT_POINTLIST,
353 [PIPE_PRIM_LINES] = V_008958_DI_PT_LINELIST,
354 [PIPE_PRIM_LINE_LOOP] = V_008958_DI_PT_LINELOOP,
355 [PIPE_PRIM_LINE_STRIP] = V_008958_DI_PT_LINESTRIP,
356 [PIPE_PRIM_TRIANGLES] = V_008958_DI_PT_TRILIST,
357 [PIPE_PRIM_TRIANGLE_STRIP] = V_008958_DI_PT_TRISTRIP,
358 [PIPE_PRIM_TRIANGLE_FAN] = V_008958_DI_PT_TRIFAN,
359 [PIPE_PRIM_QUADS] = V_008958_DI_PT_QUADLIST,
360 [PIPE_PRIM_QUAD_STRIP] = V_008958_DI_PT_QUADSTRIP,
361 [PIPE_PRIM_POLYGON] = V_008958_DI_PT_POLYGON,
362 [PIPE_PRIM_LINES_ADJACENCY] = V_008958_DI_PT_LINELIST_ADJ,
363 [PIPE_PRIM_LINE_STRIP_ADJACENCY] = V_008958_DI_PT_LINESTRIP_ADJ,
364 [PIPE_PRIM_TRIANGLES_ADJACENCY] = V_008958_DI_PT_TRILIST_ADJ,
365 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY] = V_008958_DI_PT_TRISTRIP_ADJ
366 };
367 unsigned result = prim_conv[pprim];
368 if (result == ~0) {
369 R600_ERR("unsupported primitive type %d\n", pprim);
370 }
371 return result;
372 }
373
374 static unsigned si_conv_prim_to_gs_out(unsigned mode)
375 {
376 static const int prim_conv[] = {
377 [PIPE_PRIM_POINTS] = V_028A6C_OUTPRIM_TYPE_POINTLIST,
378 [PIPE_PRIM_LINES] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
379 [PIPE_PRIM_LINE_LOOP] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
380 [PIPE_PRIM_LINE_STRIP] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
381 [PIPE_PRIM_TRIANGLES] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
382 [PIPE_PRIM_TRIANGLE_STRIP] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
383 [PIPE_PRIM_TRIANGLE_FAN] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
384 [PIPE_PRIM_QUADS] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
385 [PIPE_PRIM_QUAD_STRIP] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
386 [PIPE_PRIM_POLYGON] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
387 [PIPE_PRIM_LINES_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
388 [PIPE_PRIM_LINE_STRIP_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
389 [PIPE_PRIM_TRIANGLES_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
390 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
391 };
392 assert(mode < Elements(prim_conv));
393
394 return prim_conv[mode];
395 }
396
397 static bool si_update_draw_info_state(struct si_context *sctx,
398 const struct pipe_draw_info *info,
399 const struct pipe_index_buffer *ib)
400 {
401 struct si_pm4_state *pm4 = si_pm4_alloc_state(sctx);
402 struct si_shader *vs = si_get_vs_state(sctx);
403 unsigned prim = si_conv_pipe_prim(info->mode);
404 unsigned gs_out_prim =
405 si_conv_prim_to_gs_out(sctx->gs_shader ?
406 sctx->gs_shader->current->shader.gs_output_prim :
407 info->mode);
408 unsigned ls_mask = 0;
409
410 if (pm4 == NULL)
411 return false;
412
413 if (prim == ~0) {
414 FREE(pm4);
415 return false;
416 }
417
418 if (sctx->b.chip_class >= CIK) {
419 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
420 bool wd_switch_on_eop = prim == V_008958_DI_PT_POLYGON ||
421 prim == V_008958_DI_PT_LINELOOP ||
422 prim == V_008958_DI_PT_TRIFAN ||
423 prim == V_008958_DI_PT_TRISTRIP_ADJ ||
424 info->primitive_restart ||
425 (rs ? rs->line_stipple_enable : false);
426 /* If the WD switch is false, the IA switch must be false too. */
427 bool ia_switch_on_eop = wd_switch_on_eop;
428
429 si_pm4_set_reg(pm4, R_028AA8_IA_MULTI_VGT_PARAM,
430 S_028AA8_SWITCH_ON_EOP(ia_switch_on_eop) |
431 S_028AA8_PARTIAL_VS_WAVE_ON(1) |
432 S_028AA8_PRIMGROUP_SIZE(63) |
433 S_028AA8_WD_SWITCH_ON_EOP(wd_switch_on_eop));
434 si_pm4_set_reg(pm4, R_028B74_VGT_DISPATCH_DRAW_INDEX,
435 ib->index_size == 4 ? 0xFC000000 : 0xFC00);
436
437 si_pm4_set_reg(pm4, R_030908_VGT_PRIMITIVE_TYPE, prim);
438 } else {
439 si_pm4_set_reg(pm4, R_008958_VGT_PRIMITIVE_TYPE, prim);
440 }
441
442 si_pm4_set_reg(pm4, R_028A6C_VGT_GS_OUT_PRIM_TYPE, gs_out_prim);
443 si_pm4_set_reg(pm4, R_028408_VGT_INDX_OFFSET,
444 info->indexed ? info->index_bias : info->start);
445 si_pm4_set_reg(pm4, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, info->restart_index);
446 si_pm4_set_reg(pm4, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, info->primitive_restart);
447 si_pm4_set_reg(pm4, SI_SGPR_START_INSTANCE * 4 +
448 (sctx->gs_shader ? R_00B330_SPI_SHADER_USER_DATA_ES_0 :
449 R_00B130_SPI_SHADER_USER_DATA_VS_0),
450 info->start_instance);
451
452 if (prim == V_008958_DI_PT_LINELIST)
453 ls_mask = 1;
454 else if (prim == V_008958_DI_PT_LINESTRIP)
455 ls_mask = 2;
456 si_pm4_set_reg(pm4, R_028A0C_PA_SC_LINE_STIPPLE,
457 S_028A0C_AUTO_RESET_CNTL(ls_mask) |
458 sctx->pa_sc_line_stipple);
459
460 if (info->mode == PIPE_PRIM_QUADS || info->mode == PIPE_PRIM_QUAD_STRIP || info->mode == PIPE_PRIM_POLYGON) {
461 si_pm4_set_reg(pm4, R_028814_PA_SU_SC_MODE_CNTL,
462 S_028814_PROVOKING_VTX_LAST(1) | sctx->pa_su_sc_mode_cntl);
463 } else {
464 si_pm4_set_reg(pm4, R_028814_PA_SU_SC_MODE_CNTL, sctx->pa_su_sc_mode_cntl);
465 }
466 si_pm4_set_reg(pm4, R_02881C_PA_CL_VS_OUT_CNTL,
467 S_02881C_USE_VTX_POINT_SIZE(vs->vs_out_point_size) |
468 S_02881C_USE_VTX_EDGE_FLAG(vs->vs_out_edgeflag) |
469 S_02881C_USE_VTX_RENDER_TARGET_INDX(vs->vs_out_layer) |
470 S_02881C_VS_OUT_CCDIST0_VEC_ENA((vs->clip_dist_write & 0x0F) != 0) |
471 S_02881C_VS_OUT_CCDIST1_VEC_ENA((vs->clip_dist_write & 0xF0) != 0) |
472 S_02881C_VS_OUT_MISC_VEC_ENA(vs->vs_out_misc_write) |
473 (sctx->queued.named.rasterizer->clip_plane_enable &
474 vs->clip_dist_write));
475 si_pm4_set_reg(pm4, R_028810_PA_CL_CLIP_CNTL,
476 sctx->queued.named.rasterizer->pa_cl_clip_cntl |
477 (vs->clip_dist_write ? 0 :
478 sctx->queued.named.rasterizer->clip_plane_enable & 0x3F));
479
480 si_pm4_set_state(sctx, draw_info, pm4);
481 return true;
482 }
483
484 static void si_update_spi_map(struct si_context *sctx)
485 {
486 struct si_shader *ps = &sctx->ps_shader->current->shader;
487 struct si_shader *vs = si_get_vs_state(sctx);
488 struct si_pm4_state *pm4 = si_pm4_alloc_state(sctx);
489 unsigned i, j, tmp;
490
491 for (i = 0; i < ps->ninput; i++) {
492 unsigned name = ps->input[i].name;
493 unsigned param_offset = ps->input[i].param_offset;
494
495 if (name == TGSI_SEMANTIC_POSITION)
496 /* Read from preloaded VGPRs, not parameters */
497 continue;
498
499 bcolor:
500 tmp = 0;
501
502 if (ps->input[i].interpolate == TGSI_INTERPOLATE_CONSTANT ||
503 (ps->input[i].interpolate == TGSI_INTERPOLATE_COLOR &&
504 sctx->ps_shader->current->key.ps.flatshade)) {
505 tmp |= S_028644_FLAT_SHADE(1);
506 }
507
508 if (name == TGSI_SEMANTIC_GENERIC &&
509 sctx->sprite_coord_enable & (1 << ps->input[i].sid)) {
510 tmp |= S_028644_PT_SPRITE_TEX(1);
511 }
512
513 for (j = 0; j < vs->noutput; j++) {
514 if (name == vs->output[j].name &&
515 ps->input[i].sid == vs->output[j].sid) {
516 tmp |= S_028644_OFFSET(vs->output[j].param_offset);
517 break;
518 }
519 }
520
521 if (j == vs->noutput) {
522 /* No corresponding output found, load defaults into input */
523 tmp |= S_028644_OFFSET(0x20);
524 }
525
526 si_pm4_set_reg(pm4,
527 R_028644_SPI_PS_INPUT_CNTL_0 + param_offset * 4,
528 tmp);
529
530 if (name == TGSI_SEMANTIC_COLOR &&
531 sctx->ps_shader->current->key.ps.color_two_side) {
532 name = TGSI_SEMANTIC_BCOLOR;
533 param_offset++;
534 goto bcolor;
535 }
536 }
537
538 si_pm4_set_state(sctx, spi, pm4);
539 }
540
541 /* Initialize state related to ESGS / GSVS ring buffers */
542 static void si_init_gs_rings(struct si_context *sctx)
543 {
544 unsigned size = 128 * 1024;
545
546 assert(!sctx->gs_rings);
547 sctx->gs_rings = si_pm4_alloc_state(sctx);
548
549 sctx->esgs_ring.buffer =
550 pipe_buffer_create(sctx->b.b.screen, PIPE_BIND_CUSTOM,
551 PIPE_USAGE_STATIC, size);
552 sctx->esgs_ring.buffer_size = size;
553
554 size = 64 * 1024 * 1024;
555 sctx->gsvs_ring.buffer =
556 pipe_buffer_create(sctx->b.b.screen, PIPE_BIND_CUSTOM,
557 PIPE_USAGE_STATIC, size);
558 sctx->gsvs_ring.buffer_size = size;
559
560 if (sctx->b.chip_class >= CIK) {
561 si_pm4_set_reg(sctx->gs_rings, R_030900_VGT_ESGS_RING_SIZE,
562 sctx->esgs_ring.buffer_size / 256);
563 si_pm4_set_reg(sctx->gs_rings, R_030904_VGT_GSVS_RING_SIZE,
564 sctx->gsvs_ring.buffer_size / 256);
565 } else {
566 si_pm4_set_reg(sctx->gs_rings, R_0088C8_VGT_ESGS_RING_SIZE,
567 sctx->esgs_ring.buffer_size / 256);
568 si_pm4_set_reg(sctx->gs_rings, R_0088CC_VGT_GSVS_RING_SIZE,
569 sctx->gsvs_ring.buffer_size / 256);
570 }
571
572 si_set_ring_buffer(&sctx->b.b, SI_SHADER_EXPORT, 0, &sctx->esgs_ring,
573 0, sctx->esgs_ring.buffer_size, true, true, 4, 64);
574 si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_GEOMETRY, 0, &sctx->esgs_ring,
575 0, sctx->esgs_ring.buffer_size, false, false, 0, 0);
576 si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_VERTEX, 0, &sctx->gsvs_ring,
577 0, sctx->gsvs_ring.buffer_size, false, false, 0, 0);
578 }
579
580 static void si_update_derived_state(struct si_context *sctx)
581 {
582 struct pipe_context * ctx = (struct pipe_context*)sctx;
583
584 if (!sctx->blitter->running) {
585 /* Flush depth textures which need to be flushed. */
586 for (int i = 0; i < SI_NUM_SHADERS; i++) {
587 if (sctx->samplers[i].depth_texture_mask) {
588 si_flush_depth_textures(sctx, &sctx->samplers[i]);
589 }
590 if (sctx->samplers[i].compressed_colortex_mask) {
591 si_decompress_color_textures(sctx, &sctx->samplers[i]);
592 }
593 }
594 }
595
596 if (sctx->gs_shader) {
597 si_shader_select(ctx, sctx->gs_shader);
598
599 if (!sctx->gs_shader->current->pm4) {
600 si_pipe_shader_gs(ctx, sctx->gs_shader->current);
601 si_pipe_shader_vs(ctx,
602 sctx->gs_shader->current->gs_copy_shader);
603 }
604
605 si_pm4_bind_state(sctx, gs, sctx->gs_shader->current->pm4);
606 si_pm4_bind_state(sctx, vs, sctx->gs_shader->current->gs_copy_shader->pm4);
607
608 sctx->b.streamout.stride_in_dw = sctx->gs_shader->so.stride;
609
610 si_shader_select(ctx, sctx->vs_shader);
611
612 if (!sctx->vs_shader->current->pm4)
613 si_pipe_shader_es(ctx, sctx->vs_shader->current);
614
615 si_pm4_bind_state(sctx, es, sctx->vs_shader->current->pm4);
616
617 if (!sctx->gs_rings)
618 si_init_gs_rings(sctx);
619 if (sctx->emitted.named.gs_rings != sctx->gs_rings)
620 sctx->b.flags |= R600_CONTEXT_VGT_FLUSH;
621 si_pm4_bind_state(sctx, gs_rings, sctx->gs_rings);
622
623 si_set_ring_buffer(ctx, PIPE_SHADER_GEOMETRY, 1, &sctx->gsvs_ring,
624 sctx->gs_shader->current->shader.gs_max_out_vertices *
625 sctx->gs_shader->current->shader.noutput * 16,
626 64, true, true, 4, 16);
627
628 if (!sctx->gs_on) {
629 sctx->gs_on = si_pm4_alloc_state(sctx);
630
631 si_pm4_set_reg(sctx->gs_on, R_028B54_VGT_SHADER_STAGES_EN,
632 S_028B54_ES_EN(V_028B54_ES_STAGE_REAL) |
633 S_028B54_GS_EN(1) |
634 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER));
635 }
636 si_pm4_bind_state(sctx, gs_onoff, sctx->gs_on);
637 } else {
638 si_shader_select(ctx, sctx->vs_shader);
639
640 if (!sctx->vs_shader->current->pm4)
641 si_pipe_shader_vs(ctx, sctx->vs_shader->current);
642
643 si_pm4_bind_state(sctx, vs, sctx->vs_shader->current->pm4);
644
645 sctx->b.streamout.stride_in_dw = sctx->vs_shader->so.stride;
646
647 if (!sctx->gs_off) {
648 sctx->gs_off = si_pm4_alloc_state(sctx);
649
650 si_pm4_set_reg(sctx->gs_off, R_028A40_VGT_GS_MODE, 0);
651 si_pm4_set_reg(sctx->gs_off, R_028B54_VGT_SHADER_STAGES_EN, 0);
652 }
653 si_pm4_bind_state(sctx, gs_onoff, sctx->gs_off);
654 si_pm4_bind_state(sctx, gs_rings, NULL);
655 si_pm4_bind_state(sctx, gs, NULL);
656 si_pm4_bind_state(sctx, es, NULL);
657 }
658
659 si_shader_select(ctx, sctx->ps_shader);
660
661 if (!sctx->ps_shader->current->pm4 ||
662 sctx->ps_shader->current->cb0_is_integer != sctx->fb_cb0_is_integer)
663 si_pipe_shader_ps(ctx, sctx->ps_shader->current);
664
665 si_pm4_bind_state(sctx, ps, sctx->ps_shader->current->pm4);
666
667 if (si_pm4_state_changed(sctx, ps) || si_pm4_state_changed(sctx, vs)) {
668 /* XXX: Emitting the PS state even when only the VS changed
669 * fixes random failures with piglit glsl-max-varyings.
670 * Not sure why...
671 */
672 sctx->emitted.named.ps = NULL;
673 si_update_spi_map(sctx);
674 }
675 }
676
677 static void si_vertex_buffer_update(struct si_context *sctx)
678 {
679 struct pipe_context *ctx = &sctx->b.b;
680 struct si_pm4_state *pm4 = si_pm4_alloc_state(sctx);
681 bool bound[PIPE_MAX_ATTRIBS] = {};
682 unsigned i, count;
683 uint64_t va;
684
685 sctx->b.flags |= R600_CONTEXT_INV_TEX_CACHE;
686
687 count = sctx->vertex_elements->count;
688 assert(count <= 256 / 4);
689
690 si_pm4_sh_data_begin(pm4);
691 for (i = 0 ; i < count; i++) {
692 struct pipe_vertex_element *ve = &sctx->vertex_elements->elements[i];
693 struct pipe_vertex_buffer *vb;
694 struct r600_resource *rbuffer;
695 unsigned offset;
696
697 if (ve->vertex_buffer_index >= sctx->nr_vertex_buffers)
698 continue;
699
700 vb = &sctx->vertex_buffer[ve->vertex_buffer_index];
701 rbuffer = (struct r600_resource*)vb->buffer;
702 if (rbuffer == NULL)
703 continue;
704
705 offset = 0;
706 offset += vb->buffer_offset;
707 offset += ve->src_offset;
708
709 va = r600_resource_va(ctx->screen, (void*)rbuffer);
710 va += offset;
711
712 /* Fill in T# buffer resource description */
713 si_pm4_sh_data_add(pm4, va & 0xFFFFFFFF);
714 si_pm4_sh_data_add(pm4, (S_008F04_BASE_ADDRESS_HI(va >> 32) |
715 S_008F04_STRIDE(vb->stride)));
716 if (vb->stride)
717 /* Round up by rounding down and adding 1 */
718 si_pm4_sh_data_add(pm4,
719 (vb->buffer->width0 - offset -
720 util_format_get_blocksize(ve->src_format)) /
721 vb->stride + 1);
722 else
723 si_pm4_sh_data_add(pm4, vb->buffer->width0 - offset);
724 si_pm4_sh_data_add(pm4, sctx->vertex_elements->rsrc_word3[i]);
725
726 if (!bound[ve->vertex_buffer_index]) {
727 si_pm4_add_bo(pm4, rbuffer, RADEON_USAGE_READ);
728 bound[ve->vertex_buffer_index] = true;
729 }
730 }
731 si_pm4_sh_data_end(pm4, sctx->gs_shader ?
732 R_00B330_SPI_SHADER_USER_DATA_ES_0 :
733 R_00B130_SPI_SHADER_USER_DATA_VS_0,
734 SI_SGPR_VERTEX_BUFFER);
735 si_pm4_set_state(sctx, vertex_buffers, pm4);
736 }
737
738 static void si_state_draw(struct si_context *sctx,
739 const struct pipe_draw_info *info,
740 const struct pipe_index_buffer *ib)
741 {
742 struct si_pm4_state *pm4 = si_pm4_alloc_state(sctx);
743
744 if (pm4 == NULL)
745 return;
746
747 /* queries need some special values
748 * (this is non-zero if any query is active) */
749 if (sctx->b.num_occlusion_queries > 0) {
750 if (sctx->b.chip_class >= CIK) {
751 si_pm4_set_reg(pm4, R_028004_DB_COUNT_CONTROL,
752 S_028004_PERFECT_ZPASS_COUNTS(1) |
753 S_028004_SAMPLE_RATE(sctx->fb_log_samples) |
754 S_028004_ZPASS_ENABLE(1) |
755 S_028004_SLICE_EVEN_ENABLE(1) |
756 S_028004_SLICE_ODD_ENABLE(1));
757 } else {
758 si_pm4_set_reg(pm4, R_028004_DB_COUNT_CONTROL,
759 S_028004_PERFECT_ZPASS_COUNTS(1) |
760 S_028004_SAMPLE_RATE(sctx->fb_log_samples));
761 }
762 }
763
764 if (info->count_from_stream_output) {
765 struct r600_so_target *t =
766 (struct r600_so_target*)info->count_from_stream_output;
767 uint64_t va = r600_resource_va(&sctx->screen->b.b,
768 &t->buf_filled_size->b.b);
769 va += t->buf_filled_size_offset;
770
771 si_pm4_set_reg(pm4, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE,
772 t->stride_in_dw);
773
774 si_pm4_cmd_begin(pm4, PKT3_COPY_DATA);
775 si_pm4_cmd_add(pm4,
776 COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
777 COPY_DATA_DST_SEL(COPY_DATA_REG) |
778 COPY_DATA_WR_CONFIRM);
779 si_pm4_cmd_add(pm4, va); /* src address lo */
780 si_pm4_cmd_add(pm4, va >> 32UL); /* src address hi */
781 si_pm4_cmd_add(pm4, R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE >> 2);
782 si_pm4_cmd_add(pm4, 0); /* unused */
783 si_pm4_add_bo(pm4, t->buf_filled_size, RADEON_USAGE_READ);
784 si_pm4_cmd_end(pm4, true);
785 }
786
787 /* draw packet */
788 si_pm4_cmd_begin(pm4, PKT3_INDEX_TYPE);
789 if (ib->index_size == 4) {
790 si_pm4_cmd_add(pm4, V_028A7C_VGT_INDEX_32 | (SI_BIG_ENDIAN ?
791 V_028A7C_VGT_DMA_SWAP_32_BIT : 0));
792 } else {
793 si_pm4_cmd_add(pm4, V_028A7C_VGT_INDEX_16 | (SI_BIG_ENDIAN ?
794 V_028A7C_VGT_DMA_SWAP_16_BIT : 0));
795 }
796 si_pm4_cmd_end(pm4, sctx->b.predicate_drawing);
797
798 si_pm4_cmd_begin(pm4, PKT3_NUM_INSTANCES);
799 si_pm4_cmd_add(pm4, info->instance_count);
800 si_pm4_cmd_end(pm4, sctx->b.predicate_drawing);
801
802 if (info->indexed) {
803 uint32_t max_size = (ib->buffer->width0 - ib->offset) /
804 sctx->index_buffer.index_size;
805 uint64_t va;
806 va = r600_resource_va(&sctx->screen->b.b, ib->buffer);
807 va += ib->offset;
808
809 si_pm4_add_bo(pm4, (struct r600_resource *)ib->buffer, RADEON_USAGE_READ);
810 si_cmd_draw_index_2(pm4, max_size, va, info->count,
811 V_0287F0_DI_SRC_SEL_DMA,
812 sctx->b.predicate_drawing);
813 } else {
814 uint32_t initiator = V_0287F0_DI_SRC_SEL_AUTO_INDEX;
815 initiator |= S_0287F0_USE_OPAQUE(!!info->count_from_stream_output);
816 si_cmd_draw_index_auto(pm4, info->count, initiator, sctx->b.predicate_drawing);
817 }
818
819 si_pm4_set_state(sctx, draw, pm4);
820 }
821
822 void si_emit_cache_flush(struct r600_common_context *sctx, struct r600_atom *atom)
823 {
824 struct radeon_winsys_cs *cs = sctx->rings.gfx.cs;
825 uint32_t cp_coher_cntl = 0;
826
827 /* XXX SI flushes both ICACHE and KCACHE if either flag is set.
828 * XXX CIK shouldn't have this issue. Test CIK before separating the flags
829 * XXX to ensure there is no regression. Also find out if there is another
830 * XXX way to flush either ICACHE or KCACHE but not both for SI. */
831 if (sctx->flags & (R600_CONTEXT_INV_SHADER_CACHE |
832 R600_CONTEXT_INV_CONST_CACHE)) {
833 cp_coher_cntl |= S_0085F0_SH_ICACHE_ACTION_ENA(1) |
834 S_0085F0_SH_KCACHE_ACTION_ENA(1);
835 }
836 if (sctx->flags & (R600_CONTEXT_INV_TEX_CACHE |
837 R600_CONTEXT_STREAMOUT_FLUSH)) {
838 cp_coher_cntl |= S_0085F0_TC_ACTION_ENA(1) |
839 S_0085F0_TCL1_ACTION_ENA(1);
840 }
841 if (sctx->flags & R600_CONTEXT_FLUSH_AND_INV_CB) {
842 cp_coher_cntl |= S_0085F0_CB_ACTION_ENA(1) |
843 S_0085F0_CB0_DEST_BASE_ENA(1) |
844 S_0085F0_CB1_DEST_BASE_ENA(1) |
845 S_0085F0_CB2_DEST_BASE_ENA(1) |
846 S_0085F0_CB3_DEST_BASE_ENA(1) |
847 S_0085F0_CB4_DEST_BASE_ENA(1) |
848 S_0085F0_CB5_DEST_BASE_ENA(1) |
849 S_0085F0_CB6_DEST_BASE_ENA(1) |
850 S_0085F0_CB7_DEST_BASE_ENA(1);
851 }
852 if (sctx->flags & R600_CONTEXT_FLUSH_AND_INV_DB) {
853 cp_coher_cntl |= S_0085F0_DB_ACTION_ENA(1) |
854 S_0085F0_DB_DEST_BASE_ENA(1);
855 }
856
857 if (cp_coher_cntl) {
858 if (sctx->chip_class >= CIK) {
859 radeon_emit(cs, PKT3(PKT3_ACQUIRE_MEM, 5, 0));
860 radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */
861 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
862 radeon_emit(cs, 0xff); /* CP_COHER_SIZE_HI */
863 radeon_emit(cs, 0); /* CP_COHER_BASE */
864 radeon_emit(cs, 0); /* CP_COHER_BASE_HI */
865 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
866 } else {
867 radeon_emit(cs, PKT3(PKT3_SURFACE_SYNC, 3, 0));
868 radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */
869 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
870 radeon_emit(cs, 0); /* CP_COHER_BASE */
871 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
872 }
873 }
874
875 if (sctx->flags & R600_CONTEXT_FLUSH_AND_INV_CB_META) {
876 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
877 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_META) | EVENT_INDEX(0));
878 }
879 if (sctx->flags & R600_CONTEXT_FLUSH_AND_INV_DB_META) {
880 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
881 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_DB_META) | EVENT_INDEX(0));
882 }
883
884 if (sctx->flags & (R600_CONTEXT_WAIT_3D_IDLE |
885 R600_CONTEXT_PS_PARTIAL_FLUSH)) {
886 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
887 radeon_emit(cs, EVENT_TYPE(V_028A90_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
888 } else if (sctx->flags & R600_CONTEXT_STREAMOUT_FLUSH) {
889 /* Needed if streamout buffers are going to be used as a source. */
890 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
891 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
892 }
893
894 if (sctx->flags & R600_CONTEXT_VGT_FLUSH) {
895 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
896 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
897 }
898
899 sctx->flags = 0;
900 }
901
902 const struct r600_atom si_atom_cache_flush = { si_emit_cache_flush, 13 }; /* number of CS dwords */
903
904 void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info)
905 {
906 struct si_context *sctx = (struct si_context *)ctx;
907 struct pipe_index_buffer ib = {};
908 uint32_t i;
909
910 if (!info->count && (info->indexed || !info->count_from_stream_output))
911 return;
912
913 if (!sctx->ps_shader || !sctx->vs_shader)
914 return;
915
916 si_update_derived_state(sctx);
917 si_vertex_buffer_update(sctx);
918
919 if (info->indexed) {
920 /* Initialize the index buffer struct. */
921 pipe_resource_reference(&ib.buffer, sctx->index_buffer.buffer);
922 ib.user_buffer = sctx->index_buffer.user_buffer;
923 ib.index_size = sctx->index_buffer.index_size;
924 ib.offset = sctx->index_buffer.offset + info->start * ib.index_size;
925
926 /* Translate or upload, if needed. */
927 if (ib.index_size == 1) {
928 struct pipe_resource *out_buffer = NULL;
929 unsigned out_offset;
930 void *ptr;
931
932 u_upload_alloc(sctx->b.uploader, 0, info->count * 2,
933 &out_offset, &out_buffer, &ptr);
934
935 util_shorten_ubyte_elts_to_userptr(
936 &sctx->b.b, &ib, 0, ib.offset, info->count, ptr);
937
938 pipe_resource_reference(&ib.buffer, NULL);
939 ib.user_buffer = NULL;
940 ib.buffer = out_buffer;
941 ib.offset = out_offset;
942 ib.index_size = 2;
943 }
944
945 if (ib.user_buffer && !ib.buffer) {
946 u_upload_data(sctx->b.uploader, 0, info->count * ib.index_size,
947 ib.user_buffer, &ib.offset, &ib.buffer);
948 }
949 }
950
951 if (!si_update_draw_info_state(sctx, info, &ib))
952 return;
953
954 si_state_draw(sctx, info, &ib);
955
956 sctx->pm4_dirty_cdwords += si_pm4_dirty_dw(sctx);
957
958 /* Check flush flags. */
959 if (sctx->b.flags)
960 sctx->atoms.cache_flush->dirty = true;
961
962 si_need_cs_space(sctx, 0, TRUE);
963
964 /* Emit states. */
965 for (i = 0; i < SI_NUM_ATOMS(sctx); i++) {
966 if (sctx->atoms.array[i]->dirty) {
967 sctx->atoms.array[i]->emit(&sctx->b, sctx->atoms.array[i]);
968 sctx->atoms.array[i]->dirty = false;
969 }
970 }
971
972 si_pm4_emit_dirty(sctx);
973 sctx->pm4_dirty_cdwords = 0;
974
975 #if SI_TRACE_CS
976 if (sctx->screen->b.trace_bo) {
977 si_trace_emit(sctx);
978 }
979 #endif
980
981 /* Set the depth buffer as dirty. */
982 if (sctx->framebuffer.zsbuf) {
983 struct pipe_surface *surf = sctx->framebuffer.zsbuf;
984 struct r600_texture *rtex = (struct r600_texture *)surf->texture;
985
986 rtex->dirty_level_mask |= 1 << surf->u.tex.level;
987 }
988 if (sctx->fb_compressed_cb_mask) {
989 struct pipe_surface *surf;
990 struct r600_texture *rtex;
991 unsigned mask = sctx->fb_compressed_cb_mask;
992
993 do {
994 unsigned i = u_bit_scan(&mask);
995 surf = sctx->framebuffer.cbufs[i];
996 rtex = (struct r600_texture*)surf->texture;
997
998 rtex->dirty_level_mask |= 1 << surf->u.tex.level;
999 } while (mask);
1000 }
1001
1002 pipe_resource_reference(&ib.buffer, NULL);
1003 sctx->b.num_draw_calls++;
1004 }