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radeonsi: remove si.h
[mesa.git] / src / gallium / drivers / radeonsi / si_state_draw.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Christian König <christian.koenig@amd.com>
25 */
26
27 #include "util/u_memory.h"
28 #include "util/u_framebuffer.h"
29 #include "util/u_blitter.h"
30 #include "util/u_index_modify.h"
31 #include "util/u_upload_mgr.h"
32 #include "tgsi/tgsi_parse.h"
33 #include "si_pipe.h"
34 #include "si_shader.h"
35 #include "si_state.h"
36 #include "../radeon/r600_cs.h"
37 #include "sid.h"
38
39 /*
40 * Shaders
41 */
42
43 static void si_pipe_shader_vs(struct pipe_context *ctx, struct si_pipe_shader *shader)
44 {
45 struct si_context *sctx = (struct si_context *)ctx;
46 struct si_pm4_state *pm4;
47 unsigned num_sgprs, num_user_sgprs;
48 unsigned nparams, i, vgpr_comp_cnt;
49 uint64_t va;
50
51 si_pm4_delete_state(sctx, vs, shader->pm4);
52 pm4 = shader->pm4 = si_pm4_alloc_state(sctx);
53
54 if (pm4 == NULL)
55 return;
56
57 /* Certain attributes (position, psize, etc.) don't count as params.
58 * VS is required to export at least one param and r600_shader_from_tgsi()
59 * takes care of adding a dummy export.
60 */
61 for (nparams = 0, i = 0 ; i < shader->shader.noutput; i++) {
62 switch (shader->shader.output[i].name) {
63 case TGSI_SEMANTIC_CLIPVERTEX:
64 case TGSI_SEMANTIC_POSITION:
65 case TGSI_SEMANTIC_PSIZE:
66 break;
67 default:
68 nparams++;
69 }
70 }
71 if (nparams < 1)
72 nparams = 1;
73
74 si_pm4_set_reg(pm4, R_0286C4_SPI_VS_OUT_CONFIG,
75 S_0286C4_VS_EXPORT_COUNT(nparams - 1));
76
77 si_pm4_set_reg(pm4, R_02870C_SPI_SHADER_POS_FORMAT,
78 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
79 S_02870C_POS1_EXPORT_FORMAT(shader->shader.nr_pos_exports > 1 ?
80 V_02870C_SPI_SHADER_4COMP :
81 V_02870C_SPI_SHADER_NONE) |
82 S_02870C_POS2_EXPORT_FORMAT(shader->shader.nr_pos_exports > 2 ?
83 V_02870C_SPI_SHADER_4COMP :
84 V_02870C_SPI_SHADER_NONE) |
85 S_02870C_POS3_EXPORT_FORMAT(shader->shader.nr_pos_exports > 3 ?
86 V_02870C_SPI_SHADER_4COMP :
87 V_02870C_SPI_SHADER_NONE));
88
89 va = r600_resource_va(ctx->screen, (void *)shader->bo);
90 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ);
91 si_pm4_set_reg(pm4, R_00B120_SPI_SHADER_PGM_LO_VS, va >> 8);
92 si_pm4_set_reg(pm4, R_00B124_SPI_SHADER_PGM_HI_VS, va >> 40);
93
94 num_user_sgprs = SI_VS_NUM_USER_SGPR;
95 num_sgprs = shader->num_sgprs;
96 if (num_user_sgprs > num_sgprs) {
97 /* Last 2 reserved SGPRs are used for VCC */
98 num_sgprs = num_user_sgprs + 2;
99 }
100 assert(num_sgprs <= 104);
101
102 vgpr_comp_cnt = shader->shader.uses_instanceid ? 3 : 0;
103
104 si_pm4_set_reg(pm4, R_00B128_SPI_SHADER_PGM_RSRC1_VS,
105 S_00B128_VGPRS((shader->num_vgprs - 1) / 4) |
106 S_00B128_SGPRS((num_sgprs - 1) / 8) |
107 S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt));
108 si_pm4_set_reg(pm4, R_00B12C_SPI_SHADER_PGM_RSRC2_VS,
109 S_00B12C_USER_SGPR(num_user_sgprs) |
110 S_00B12C_SO_BASE0_EN(!!shader->selector->so.stride[0]) |
111 S_00B12C_SO_BASE1_EN(!!shader->selector->so.stride[1]) |
112 S_00B12C_SO_BASE2_EN(!!shader->selector->so.stride[2]) |
113 S_00B12C_SO_BASE3_EN(!!shader->selector->so.stride[3]) |
114 S_00B12C_SO_EN(!!shader->selector->so.num_outputs));
115
116 si_pm4_bind_state(sctx, vs, shader->pm4);
117 sctx->b.flags |= R600_CONTEXT_INV_SHADER_CACHE;
118 }
119
120 static void si_pipe_shader_ps(struct pipe_context *ctx, struct si_pipe_shader *shader)
121 {
122 struct si_context *sctx = (struct si_context *)ctx;
123 struct si_pm4_state *pm4;
124 unsigned i, exports_ps, spi_ps_in_control, db_shader_control;
125 unsigned num_sgprs, num_user_sgprs;
126 unsigned spi_baryc_cntl = 0, spi_ps_input_ena, spi_shader_z_format;
127 uint64_t va;
128
129 si_pm4_delete_state(sctx, ps, shader->pm4);
130 pm4 = shader->pm4 = si_pm4_alloc_state(sctx);
131
132 if (pm4 == NULL)
133 return;
134
135 db_shader_control = S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z) |
136 S_02880C_ALPHA_TO_MASK_DISABLE(sctx->fb_cb0_is_integer);
137
138 for (i = 0; i < shader->shader.ninput; i++) {
139 switch (shader->shader.input[i].name) {
140 case TGSI_SEMANTIC_POSITION:
141 if (shader->shader.input[i].centroid) {
142 /* SPI_BARYC_CNTL.POS_FLOAT_LOCATION
143 * Possible vaules:
144 * 0 -> Position = pixel center (default)
145 * 1 -> Position = pixel centroid
146 * 2 -> Position = iterated sample number XXX:
147 * What does this mean?
148 */
149 spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(1);
150 }
151 /* Fall through */
152 case TGSI_SEMANTIC_FACE:
153 continue;
154 }
155 }
156
157 for (i = 0; i < shader->shader.noutput; i++) {
158 if (shader->shader.output[i].name == TGSI_SEMANTIC_POSITION)
159 db_shader_control |= S_02880C_Z_EXPORT_ENABLE(1);
160 if (shader->shader.output[i].name == TGSI_SEMANTIC_STENCIL)
161 db_shader_control |= S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(1);
162 }
163 if (shader->shader.uses_kill || shader->key.ps.alpha_func != PIPE_FUNC_ALWAYS)
164 db_shader_control |= S_02880C_KILL_ENABLE(1);
165
166 exports_ps = 0;
167 for (i = 0; i < shader->shader.noutput; i++) {
168 if (shader->shader.output[i].name == TGSI_SEMANTIC_POSITION ||
169 shader->shader.output[i].name == TGSI_SEMANTIC_STENCIL)
170 exports_ps |= 1;
171 }
172 if (!exports_ps) {
173 /* always at least export 1 component per pixel */
174 exports_ps = 2;
175 }
176
177 spi_ps_in_control = S_0286D8_NUM_INTERP(shader->shader.ninterp) |
178 S_0286D8_BC_OPTIMIZE_DISABLE(1);
179
180 si_pm4_set_reg(pm4, R_0286E0_SPI_BARYC_CNTL, spi_baryc_cntl);
181 spi_ps_input_ena = shader->spi_ps_input_ena;
182 /* we need to enable at least one of them, otherwise we hang the GPU */
183 assert(G_0286CC_PERSP_SAMPLE_ENA(spi_ps_input_ena) ||
184 G_0286CC_PERSP_CENTER_ENA(spi_ps_input_ena) ||
185 G_0286CC_PERSP_CENTROID_ENA(spi_ps_input_ena) ||
186 G_0286CC_PERSP_PULL_MODEL_ENA(spi_ps_input_ena) ||
187 G_0286CC_LINEAR_SAMPLE_ENA(spi_ps_input_ena) ||
188 G_0286CC_LINEAR_CENTER_ENA(spi_ps_input_ena) ||
189 G_0286CC_LINEAR_CENTROID_ENA(spi_ps_input_ena) ||
190 G_0286CC_LINE_STIPPLE_TEX_ENA(spi_ps_input_ena));
191
192 si_pm4_set_reg(pm4, R_0286CC_SPI_PS_INPUT_ENA, spi_ps_input_ena);
193 si_pm4_set_reg(pm4, R_0286D0_SPI_PS_INPUT_ADDR, spi_ps_input_ena);
194 si_pm4_set_reg(pm4, R_0286D8_SPI_PS_IN_CONTROL, spi_ps_in_control);
195
196 if (G_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(db_shader_control))
197 spi_shader_z_format = V_028710_SPI_SHADER_32_GR;
198 else if (G_02880C_Z_EXPORT_ENABLE(db_shader_control))
199 spi_shader_z_format = V_028710_SPI_SHADER_32_R;
200 else
201 spi_shader_z_format = 0;
202 si_pm4_set_reg(pm4, R_028710_SPI_SHADER_Z_FORMAT, spi_shader_z_format);
203 si_pm4_set_reg(pm4, R_028714_SPI_SHADER_COL_FORMAT,
204 shader->spi_shader_col_format);
205 si_pm4_set_reg(pm4, R_02823C_CB_SHADER_MASK, shader->cb_shader_mask);
206
207 va = r600_resource_va(ctx->screen, (void *)shader->bo);
208 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ);
209 si_pm4_set_reg(pm4, R_00B020_SPI_SHADER_PGM_LO_PS, va >> 8);
210 si_pm4_set_reg(pm4, R_00B024_SPI_SHADER_PGM_HI_PS, va >> 40);
211
212 num_user_sgprs = SI_PS_NUM_USER_SGPR;
213 num_sgprs = shader->num_sgprs;
214 /* One SGPR after user SGPRs is pre-loaded with {prim_mask, lds_offset} */
215 if ((num_user_sgprs + 1) > num_sgprs) {
216 /* Last 2 reserved SGPRs are used for VCC */
217 num_sgprs = num_user_sgprs + 1 + 2;
218 }
219 assert(num_sgprs <= 104);
220
221 si_pm4_set_reg(pm4, R_00B028_SPI_SHADER_PGM_RSRC1_PS,
222 S_00B028_VGPRS((shader->num_vgprs - 1) / 4) |
223 S_00B028_SGPRS((num_sgprs - 1) / 8));
224 si_pm4_set_reg(pm4, R_00B02C_SPI_SHADER_PGM_RSRC2_PS,
225 S_00B02C_EXTRA_LDS_SIZE(shader->lds_size) |
226 S_00B02C_USER_SGPR(num_user_sgprs));
227
228 si_pm4_set_reg(pm4, R_02880C_DB_SHADER_CONTROL, db_shader_control);
229
230 shader->cb0_is_integer = sctx->fb_cb0_is_integer;
231 shader->sprite_coord_enable = sctx->sprite_coord_enable;
232 si_pm4_bind_state(sctx, ps, shader->pm4);
233 sctx->b.flags |= R600_CONTEXT_INV_SHADER_CACHE;
234 }
235
236 /*
237 * Drawing
238 */
239
240 static unsigned si_conv_pipe_prim(unsigned pprim)
241 {
242 static const unsigned prim_conv[] = {
243 [PIPE_PRIM_POINTS] = V_008958_DI_PT_POINTLIST,
244 [PIPE_PRIM_LINES] = V_008958_DI_PT_LINELIST,
245 [PIPE_PRIM_LINE_LOOP] = V_008958_DI_PT_LINELOOP,
246 [PIPE_PRIM_LINE_STRIP] = V_008958_DI_PT_LINESTRIP,
247 [PIPE_PRIM_TRIANGLES] = V_008958_DI_PT_TRILIST,
248 [PIPE_PRIM_TRIANGLE_STRIP] = V_008958_DI_PT_TRISTRIP,
249 [PIPE_PRIM_TRIANGLE_FAN] = V_008958_DI_PT_TRIFAN,
250 [PIPE_PRIM_QUADS] = V_008958_DI_PT_QUADLIST,
251 [PIPE_PRIM_QUAD_STRIP] = V_008958_DI_PT_QUADSTRIP,
252 [PIPE_PRIM_POLYGON] = V_008958_DI_PT_POLYGON,
253 [PIPE_PRIM_LINES_ADJACENCY] = ~0,
254 [PIPE_PRIM_LINE_STRIP_ADJACENCY] = ~0,
255 [PIPE_PRIM_TRIANGLES_ADJACENCY] = ~0,
256 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY] = ~0
257 };
258 unsigned result = prim_conv[pprim];
259 if (result == ~0) {
260 R600_ERR("unsupported primitive type %d\n", pprim);
261 }
262 return result;
263 }
264
265 static unsigned si_conv_prim_to_gs_out(unsigned mode)
266 {
267 static const int prim_conv[] = {
268 [PIPE_PRIM_POINTS] = V_028A6C_OUTPRIM_TYPE_POINTLIST,
269 [PIPE_PRIM_LINES] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
270 [PIPE_PRIM_LINE_LOOP] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
271 [PIPE_PRIM_LINE_STRIP] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
272 [PIPE_PRIM_TRIANGLES] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
273 [PIPE_PRIM_TRIANGLE_STRIP] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
274 [PIPE_PRIM_TRIANGLE_FAN] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
275 [PIPE_PRIM_QUADS] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
276 [PIPE_PRIM_QUAD_STRIP] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
277 [PIPE_PRIM_POLYGON] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
278 [PIPE_PRIM_LINES_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
279 [PIPE_PRIM_LINE_STRIP_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
280 [PIPE_PRIM_TRIANGLES_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
281 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
282 };
283 assert(mode < Elements(prim_conv));
284
285 return prim_conv[mode];
286 }
287
288 static bool si_update_draw_info_state(struct si_context *sctx,
289 const struct pipe_draw_info *info,
290 const struct pipe_index_buffer *ib)
291 {
292 struct si_pm4_state *pm4 = si_pm4_alloc_state(sctx);
293 struct si_shader *vs = &sctx->vs_shader->current->shader;
294 unsigned prim = si_conv_pipe_prim(info->mode);
295 unsigned gs_out_prim = si_conv_prim_to_gs_out(info->mode);
296 unsigned ls_mask = 0;
297
298 if (pm4 == NULL)
299 return false;
300
301 if (prim == ~0) {
302 FREE(pm4);
303 return false;
304 }
305
306 if (sctx->b.chip_class >= CIK) {
307 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
308 bool wd_switch_on_eop = prim == V_008958_DI_PT_POLYGON ||
309 prim == V_008958_DI_PT_LINELOOP ||
310 prim == V_008958_DI_PT_TRIFAN ||
311 prim == V_008958_DI_PT_TRISTRIP_ADJ ||
312 info->primitive_restart ||
313 (rs ? rs->line_stipple_enable : false);
314 /* If the WD switch is false, the IA switch must be false too. */
315 bool ia_switch_on_eop = wd_switch_on_eop;
316
317 si_pm4_set_reg(pm4, R_028AA8_IA_MULTI_VGT_PARAM,
318 S_028AA8_SWITCH_ON_EOP(ia_switch_on_eop) |
319 S_028AA8_PARTIAL_VS_WAVE_ON(1) |
320 S_028AA8_PRIMGROUP_SIZE(63) |
321 S_028AA8_WD_SWITCH_ON_EOP(wd_switch_on_eop));
322 si_pm4_set_reg(pm4, R_028B74_VGT_DISPATCH_DRAW_INDEX,
323 ib->index_size == 4 ? 0xFC000000 : 0xFC00);
324
325 si_pm4_set_reg(pm4, R_030908_VGT_PRIMITIVE_TYPE, prim);
326 } else {
327 si_pm4_set_reg(pm4, R_008958_VGT_PRIMITIVE_TYPE, prim);
328 }
329
330 si_pm4_set_reg(pm4, R_028A6C_VGT_GS_OUT_PRIM_TYPE, gs_out_prim);
331 si_pm4_set_reg(pm4, R_028408_VGT_INDX_OFFSET,
332 info->indexed ? info->index_bias : info->start);
333 si_pm4_set_reg(pm4, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, info->restart_index);
334 si_pm4_set_reg(pm4, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, info->primitive_restart);
335 si_pm4_set_reg(pm4, R_00B130_SPI_SHADER_USER_DATA_VS_0 + SI_SGPR_START_INSTANCE * 4,
336 info->start_instance);
337
338 if (prim == V_008958_DI_PT_LINELIST)
339 ls_mask = 1;
340 else if (prim == V_008958_DI_PT_LINESTRIP)
341 ls_mask = 2;
342 si_pm4_set_reg(pm4, R_028A0C_PA_SC_LINE_STIPPLE,
343 S_028A0C_AUTO_RESET_CNTL(ls_mask) |
344 sctx->pa_sc_line_stipple);
345
346 if (info->mode == PIPE_PRIM_QUADS || info->mode == PIPE_PRIM_QUAD_STRIP || info->mode == PIPE_PRIM_POLYGON) {
347 si_pm4_set_reg(pm4, R_028814_PA_SU_SC_MODE_CNTL,
348 S_028814_PROVOKING_VTX_LAST(1) | sctx->pa_su_sc_mode_cntl);
349 } else {
350 si_pm4_set_reg(pm4, R_028814_PA_SU_SC_MODE_CNTL, sctx->pa_su_sc_mode_cntl);
351 }
352 si_pm4_set_reg(pm4, R_02881C_PA_CL_VS_OUT_CNTL,
353 S_02881C_USE_VTX_POINT_SIZE(vs->vs_out_point_size) |
354 S_02881C_USE_VTX_EDGE_FLAG(vs->vs_out_edgeflag) |
355 S_02881C_USE_VTX_RENDER_TARGET_INDX(vs->vs_out_layer) |
356 S_02881C_VS_OUT_CCDIST0_VEC_ENA((vs->clip_dist_write & 0x0F) != 0) |
357 S_02881C_VS_OUT_CCDIST1_VEC_ENA((vs->clip_dist_write & 0xF0) != 0) |
358 S_02881C_VS_OUT_MISC_VEC_ENA(vs->vs_out_misc_write) |
359 (sctx->queued.named.rasterizer->clip_plane_enable &
360 vs->clip_dist_write));
361 si_pm4_set_reg(pm4, R_028810_PA_CL_CLIP_CNTL,
362 sctx->queued.named.rasterizer->pa_cl_clip_cntl |
363 (vs->clip_dist_write ? 0 :
364 sctx->queued.named.rasterizer->clip_plane_enable & 0x3F));
365
366 si_pm4_set_state(sctx, draw_info, pm4);
367 return true;
368 }
369
370 static void si_update_spi_map(struct si_context *sctx)
371 {
372 struct si_shader *ps = &sctx->ps_shader->current->shader;
373 struct si_shader *vs = &sctx->vs_shader->current->shader;
374 struct si_pm4_state *pm4 = si_pm4_alloc_state(sctx);
375 unsigned i, j, tmp;
376
377 for (i = 0; i < ps->ninput; i++) {
378 unsigned name = ps->input[i].name;
379 unsigned param_offset = ps->input[i].param_offset;
380
381 if (name == TGSI_SEMANTIC_POSITION)
382 /* Read from preloaded VGPRs, not parameters */
383 continue;
384
385 bcolor:
386 tmp = 0;
387
388 if (ps->input[i].interpolate == TGSI_INTERPOLATE_CONSTANT ||
389 (ps->input[i].interpolate == TGSI_INTERPOLATE_COLOR &&
390 sctx->ps_shader->current->key.ps.flatshade)) {
391 tmp |= S_028644_FLAT_SHADE(1);
392 }
393
394 if (name == TGSI_SEMANTIC_GENERIC &&
395 sctx->sprite_coord_enable & (1 << ps->input[i].sid)) {
396 tmp |= S_028644_PT_SPRITE_TEX(1);
397 }
398
399 for (j = 0; j < vs->noutput; j++) {
400 if (name == vs->output[j].name &&
401 ps->input[i].sid == vs->output[j].sid) {
402 tmp |= S_028644_OFFSET(vs->output[j].param_offset);
403 break;
404 }
405 }
406
407 if (j == vs->noutput) {
408 /* No corresponding output found, load defaults into input */
409 tmp |= S_028644_OFFSET(0x20);
410 }
411
412 si_pm4_set_reg(pm4,
413 R_028644_SPI_PS_INPUT_CNTL_0 + param_offset * 4,
414 tmp);
415
416 if (name == TGSI_SEMANTIC_COLOR &&
417 sctx->ps_shader->current->key.ps.color_two_side) {
418 name = TGSI_SEMANTIC_BCOLOR;
419 param_offset++;
420 goto bcolor;
421 }
422 }
423
424 si_pm4_set_state(sctx, spi, pm4);
425 }
426
427 static void si_update_derived_state(struct si_context *sctx)
428 {
429 struct pipe_context * ctx = (struct pipe_context*)sctx;
430 unsigned vs_dirty = 0, ps_dirty = 0;
431
432 if (!sctx->blitter->running) {
433 /* Flush depth textures which need to be flushed. */
434 for (int i = 0; i < SI_NUM_SHADERS; i++) {
435 if (sctx->samplers[i].depth_texture_mask) {
436 si_flush_depth_textures(sctx, &sctx->samplers[i]);
437 }
438 if (sctx->samplers[i].compressed_colortex_mask) {
439 si_decompress_color_textures(sctx, &sctx->samplers[i]);
440 }
441 }
442 }
443
444 si_shader_select(ctx, sctx->vs_shader, &vs_dirty);
445
446 if (!sctx->vs_shader->current->pm4) {
447 si_pipe_shader_vs(ctx, sctx->vs_shader->current);
448 vs_dirty = 0;
449 }
450
451 if (vs_dirty) {
452 si_pm4_bind_state(sctx, vs, sctx->vs_shader->current->pm4);
453 }
454
455
456 si_shader_select(ctx, sctx->ps_shader, &ps_dirty);
457
458 if (!sctx->ps_shader->current->pm4) {
459 si_pipe_shader_ps(ctx, sctx->ps_shader->current);
460 ps_dirty = 0;
461 }
462 if (sctx->ps_shader->current->cb0_is_integer != sctx->fb_cb0_is_integer) {
463 si_pipe_shader_ps(ctx, sctx->ps_shader->current);
464 ps_dirty = 0;
465 }
466
467 if (ps_dirty) {
468 si_pm4_bind_state(sctx, ps, sctx->ps_shader->current->pm4);
469 }
470
471 if (si_pm4_state_changed(sctx, ps) || si_pm4_state_changed(sctx, vs)) {
472 /* XXX: Emitting the PS state even when only the VS changed
473 * fixes random failures with piglit glsl-max-varyings.
474 * Not sure why...
475 */
476 sctx->emitted.named.ps = NULL;
477 si_update_spi_map(sctx);
478 }
479 }
480
481 static void si_vertex_buffer_update(struct si_context *sctx)
482 {
483 struct pipe_context *ctx = &sctx->b.b;
484 struct si_pm4_state *pm4 = si_pm4_alloc_state(sctx);
485 bool bound[PIPE_MAX_ATTRIBS] = {};
486 unsigned i, count;
487 uint64_t va;
488
489 sctx->b.flags |= R600_CONTEXT_INV_TEX_CACHE;
490
491 count = sctx->vertex_elements->count;
492 assert(count <= 256 / 4);
493
494 si_pm4_sh_data_begin(pm4);
495 for (i = 0 ; i < count; i++) {
496 struct pipe_vertex_element *ve = &sctx->vertex_elements->elements[i];
497 struct pipe_vertex_buffer *vb;
498 struct r600_resource *rbuffer;
499 unsigned offset;
500
501 if (ve->vertex_buffer_index >= sctx->nr_vertex_buffers)
502 continue;
503
504 vb = &sctx->vertex_buffer[ve->vertex_buffer_index];
505 rbuffer = (struct r600_resource*)vb->buffer;
506 if (rbuffer == NULL)
507 continue;
508
509 offset = 0;
510 offset += vb->buffer_offset;
511 offset += ve->src_offset;
512
513 va = r600_resource_va(ctx->screen, (void*)rbuffer);
514 va += offset;
515
516 /* Fill in T# buffer resource description */
517 si_pm4_sh_data_add(pm4, va & 0xFFFFFFFF);
518 si_pm4_sh_data_add(pm4, (S_008F04_BASE_ADDRESS_HI(va >> 32) |
519 S_008F04_STRIDE(vb->stride)));
520 if (vb->stride)
521 /* Round up by rounding down and adding 1 */
522 si_pm4_sh_data_add(pm4,
523 (vb->buffer->width0 - offset -
524 util_format_get_blocksize(ve->src_format)) /
525 vb->stride + 1);
526 else
527 si_pm4_sh_data_add(pm4, vb->buffer->width0 - offset);
528 si_pm4_sh_data_add(pm4, sctx->vertex_elements->rsrc_word3[i]);
529
530 if (!bound[ve->vertex_buffer_index]) {
531 si_pm4_add_bo(pm4, rbuffer, RADEON_USAGE_READ);
532 bound[ve->vertex_buffer_index] = true;
533 }
534 }
535 si_pm4_sh_data_end(pm4, R_00B130_SPI_SHADER_USER_DATA_VS_0, SI_SGPR_VERTEX_BUFFER);
536 si_pm4_set_state(sctx, vertex_buffers, pm4);
537 }
538
539 static void si_state_draw(struct si_context *sctx,
540 const struct pipe_draw_info *info,
541 const struct pipe_index_buffer *ib)
542 {
543 struct si_pm4_state *pm4 = si_pm4_alloc_state(sctx);
544
545 if (pm4 == NULL)
546 return;
547
548 /* queries need some special values
549 * (this is non-zero if any query is active) */
550 if (sctx->b.num_occlusion_queries > 0) {
551 if (sctx->b.chip_class >= CIK) {
552 si_pm4_set_reg(pm4, R_028004_DB_COUNT_CONTROL,
553 S_028004_PERFECT_ZPASS_COUNTS(1) |
554 S_028004_SAMPLE_RATE(sctx->fb_log_samples) |
555 S_028004_ZPASS_ENABLE(1) |
556 S_028004_SLICE_EVEN_ENABLE(1) |
557 S_028004_SLICE_ODD_ENABLE(1));
558 } else {
559 si_pm4_set_reg(pm4, R_028004_DB_COUNT_CONTROL,
560 S_028004_PERFECT_ZPASS_COUNTS(1) |
561 S_028004_SAMPLE_RATE(sctx->fb_log_samples));
562 }
563 }
564
565 if (info->count_from_stream_output) {
566 struct r600_so_target *t =
567 (struct r600_so_target*)info->count_from_stream_output;
568 uint64_t va = r600_resource_va(&sctx->screen->b.b,
569 &t->buf_filled_size->b.b);
570 va += t->buf_filled_size_offset;
571
572 si_pm4_set_reg(pm4, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE,
573 t->stride_in_dw);
574
575 si_pm4_cmd_begin(pm4, PKT3_COPY_DATA);
576 si_pm4_cmd_add(pm4,
577 COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
578 COPY_DATA_DST_SEL(COPY_DATA_REG) |
579 COPY_DATA_WR_CONFIRM);
580 si_pm4_cmd_add(pm4, va); /* src address lo */
581 si_pm4_cmd_add(pm4, va >> 32UL); /* src address hi */
582 si_pm4_cmd_add(pm4, R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE >> 2);
583 si_pm4_cmd_add(pm4, 0); /* unused */
584 si_pm4_add_bo(pm4, t->buf_filled_size, RADEON_USAGE_READ);
585 si_pm4_cmd_end(pm4, true);
586 }
587
588 /* draw packet */
589 si_pm4_cmd_begin(pm4, PKT3_INDEX_TYPE);
590 if (ib->index_size == 4) {
591 si_pm4_cmd_add(pm4, V_028A7C_VGT_INDEX_32 | (SI_BIG_ENDIAN ?
592 V_028A7C_VGT_DMA_SWAP_32_BIT : 0));
593 } else {
594 si_pm4_cmd_add(pm4, V_028A7C_VGT_INDEX_16 | (SI_BIG_ENDIAN ?
595 V_028A7C_VGT_DMA_SWAP_16_BIT : 0));
596 }
597 si_pm4_cmd_end(pm4, sctx->b.predicate_drawing);
598
599 si_pm4_cmd_begin(pm4, PKT3_NUM_INSTANCES);
600 si_pm4_cmd_add(pm4, info->instance_count);
601 si_pm4_cmd_end(pm4, sctx->b.predicate_drawing);
602
603 if (info->indexed) {
604 uint32_t max_size = (ib->buffer->width0 - ib->offset) /
605 sctx->index_buffer.index_size;
606 uint64_t va;
607 va = r600_resource_va(&sctx->screen->b.b, ib->buffer);
608 va += ib->offset;
609
610 si_pm4_add_bo(pm4, (struct r600_resource *)ib->buffer, RADEON_USAGE_READ);
611 si_cmd_draw_index_2(pm4, max_size, va, info->count,
612 V_0287F0_DI_SRC_SEL_DMA,
613 sctx->b.predicate_drawing);
614 } else {
615 uint32_t initiator = V_0287F0_DI_SRC_SEL_AUTO_INDEX;
616 initiator |= S_0287F0_USE_OPAQUE(!!info->count_from_stream_output);
617 si_cmd_draw_index_auto(pm4, info->count, initiator, sctx->b.predicate_drawing);
618 }
619
620 si_pm4_set_state(sctx, draw, pm4);
621 }
622
623 void si_emit_cache_flush(struct r600_common_context *sctx, struct r600_atom *atom)
624 {
625 struct radeon_winsys_cs *cs = sctx->rings.gfx.cs;
626 uint32_t cp_coher_cntl = 0;
627
628 /* XXX SI flushes both ICACHE and KCACHE if either flag is set.
629 * XXX CIK shouldn't have this issue. Test CIK before separating the flags
630 * XXX to ensure there is no regression. Also find out if there is another
631 * XXX way to flush either ICACHE or KCACHE but not both for SI. */
632 if (sctx->flags & (R600_CONTEXT_INV_SHADER_CACHE |
633 R600_CONTEXT_INV_CONST_CACHE)) {
634 cp_coher_cntl |= S_0085F0_SH_ICACHE_ACTION_ENA(1) |
635 S_0085F0_SH_KCACHE_ACTION_ENA(1);
636 }
637 if (sctx->flags & (R600_CONTEXT_INV_TEX_CACHE |
638 R600_CONTEXT_STREAMOUT_FLUSH)) {
639 cp_coher_cntl |= S_0085F0_TC_ACTION_ENA(1) |
640 S_0085F0_TCL1_ACTION_ENA(1);
641 }
642 if (sctx->flags & R600_CONTEXT_FLUSH_AND_INV_CB) {
643 cp_coher_cntl |= S_0085F0_CB_ACTION_ENA(1) |
644 S_0085F0_CB0_DEST_BASE_ENA(1) |
645 S_0085F0_CB1_DEST_BASE_ENA(1) |
646 S_0085F0_CB2_DEST_BASE_ENA(1) |
647 S_0085F0_CB3_DEST_BASE_ENA(1) |
648 S_0085F0_CB4_DEST_BASE_ENA(1) |
649 S_0085F0_CB5_DEST_BASE_ENA(1) |
650 S_0085F0_CB6_DEST_BASE_ENA(1) |
651 S_0085F0_CB7_DEST_BASE_ENA(1);
652 }
653 if (sctx->flags & R600_CONTEXT_FLUSH_AND_INV_DB) {
654 cp_coher_cntl |= S_0085F0_DB_ACTION_ENA(1) |
655 S_0085F0_DB_DEST_BASE_ENA(1);
656 }
657
658 if (cp_coher_cntl) {
659 if (sctx->chip_class >= CIK) {
660 radeon_emit(cs, PKT3(PKT3_ACQUIRE_MEM, 5, 0));
661 radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */
662 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
663 radeon_emit(cs, 0xff); /* CP_COHER_SIZE_HI */
664 radeon_emit(cs, 0); /* CP_COHER_BASE */
665 radeon_emit(cs, 0); /* CP_COHER_BASE_HI */
666 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
667 } else {
668 radeon_emit(cs, PKT3(PKT3_SURFACE_SYNC, 3, 0));
669 radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */
670 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
671 radeon_emit(cs, 0); /* CP_COHER_BASE */
672 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
673 }
674 }
675
676 if (sctx->flags & R600_CONTEXT_FLUSH_AND_INV_CB_META) {
677 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
678 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_META) | EVENT_INDEX(0));
679 }
680 if (sctx->flags & R600_CONTEXT_FLUSH_AND_INV_DB_META) {
681 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
682 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_DB_META) | EVENT_INDEX(0));
683 }
684
685 if (sctx->flags & (R600_CONTEXT_WAIT_3D_IDLE |
686 R600_CONTEXT_PS_PARTIAL_FLUSH)) {
687 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
688 radeon_emit(cs, EVENT_TYPE(V_028A90_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
689 } else if (sctx->flags & R600_CONTEXT_STREAMOUT_FLUSH) {
690 /* Needed if streamout buffers are going to be used as a source. */
691 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
692 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
693 }
694
695 sctx->flags = 0;
696 }
697
698 const struct r600_atom si_atom_cache_flush = { si_emit_cache_flush, 13 }; /* number of CS dwords */
699
700 void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info)
701 {
702 struct si_context *sctx = (struct si_context *)ctx;
703 struct pipe_index_buffer ib = {};
704 uint32_t i;
705
706 if (!info->count && (info->indexed || !info->count_from_stream_output))
707 return;
708
709 if (!sctx->ps_shader || !sctx->vs_shader)
710 return;
711
712 si_update_derived_state(sctx);
713 si_vertex_buffer_update(sctx);
714
715 if (info->indexed) {
716 /* Initialize the index buffer struct. */
717 pipe_resource_reference(&ib.buffer, sctx->index_buffer.buffer);
718 ib.user_buffer = sctx->index_buffer.user_buffer;
719 ib.index_size = sctx->index_buffer.index_size;
720 ib.offset = sctx->index_buffer.offset + info->start * ib.index_size;
721
722 /* Translate or upload, if needed. */
723 if (ib.index_size == 1) {
724 struct pipe_resource *out_buffer = NULL;
725 unsigned out_offset;
726 void *ptr;
727
728 u_upload_alloc(sctx->b.uploader, 0, info->count * 2,
729 &out_offset, &out_buffer, &ptr);
730
731 util_shorten_ubyte_elts_to_userptr(
732 &sctx->b.b, &ib, 0, ib.offset, info->count, ptr);
733
734 pipe_resource_reference(&ib.buffer, NULL);
735 ib.user_buffer = NULL;
736 ib.buffer = out_buffer;
737 ib.offset = out_offset;
738 ib.index_size = 2;
739 }
740
741 if (ib.user_buffer && !ib.buffer) {
742 u_upload_data(sctx->b.uploader, 0, info->count * ib.index_size,
743 ib.user_buffer, &ib.offset, &ib.buffer);
744 }
745 }
746
747 if (!si_update_draw_info_state(sctx, info, &ib))
748 return;
749
750 si_state_draw(sctx, info, &ib);
751
752 sctx->pm4_dirty_cdwords += si_pm4_dirty_dw(sctx);
753
754 /* Check flush flags. */
755 if (sctx->b.flags)
756 sctx->atoms.cache_flush->dirty = true;
757
758 si_need_cs_space(sctx, 0, TRUE);
759
760 /* Emit states. */
761 for (i = 0; i < SI_NUM_ATOMS(sctx); i++) {
762 if (sctx->atoms.array[i]->dirty) {
763 sctx->atoms.array[i]->emit(&sctx->b, sctx->atoms.array[i]);
764 sctx->atoms.array[i]->dirty = false;
765 }
766 }
767
768 si_pm4_emit_dirty(sctx);
769 sctx->pm4_dirty_cdwords = 0;
770
771 #if SI_TRACE_CS
772 if (sctx->screen->b.trace_bo) {
773 si_trace_emit(sctx);
774 }
775 #endif
776
777 /* Set the depth buffer as dirty. */
778 if (sctx->framebuffer.zsbuf) {
779 struct pipe_surface *surf = sctx->framebuffer.zsbuf;
780 struct r600_texture *rtex = (struct r600_texture *)surf->texture;
781
782 rtex->dirty_level_mask |= 1 << surf->u.tex.level;
783 }
784 if (sctx->fb_compressed_cb_mask) {
785 struct pipe_surface *surf;
786 struct r600_texture *rtex;
787 unsigned mask = sctx->fb_compressed_cb_mask;
788
789 do {
790 unsigned i = u_bit_scan(&mask);
791 surf = sctx->framebuffer.cbufs[i];
792 rtex = (struct r600_texture*)surf->texture;
793
794 rtex->dirty_level_mask |= 1 << surf->u.tex.level;
795 } while (mask);
796 }
797
798 pipe_resource_reference(&ib.buffer, NULL);
799 sctx->b.num_draw_calls++;
800 }