2 * Copyright 2012 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 * Christian König <christian.koenig@amd.com>
28 #include "si_shader.h"
29 #include "radeon/r600_cs.h"
32 #include "util/u_index_modify.h"
33 #include "util/u_upload_mgr.h"
34 #include "util/u_prim.h"
36 static void si_decompress_textures(struct si_context
*sctx
)
38 if (!sctx
->blitter
->running
) {
39 /* Flush depth textures which need to be flushed. */
40 for (int i
= 0; i
< SI_NUM_SHADERS
; i
++) {
41 if (sctx
->samplers
[i
].depth_texture_mask
) {
42 si_flush_depth_textures(sctx
, &sctx
->samplers
[i
]);
44 if (sctx
->samplers
[i
].compressed_colortex_mask
) {
45 si_decompress_color_textures(sctx
, &sctx
->samplers
[i
]);
51 static unsigned si_conv_pipe_prim(unsigned mode
)
53 static const unsigned prim_conv
[] = {
54 [PIPE_PRIM_POINTS
] = V_008958_DI_PT_POINTLIST
,
55 [PIPE_PRIM_LINES
] = V_008958_DI_PT_LINELIST
,
56 [PIPE_PRIM_LINE_LOOP
] = V_008958_DI_PT_LINELOOP
,
57 [PIPE_PRIM_LINE_STRIP
] = V_008958_DI_PT_LINESTRIP
,
58 [PIPE_PRIM_TRIANGLES
] = V_008958_DI_PT_TRILIST
,
59 [PIPE_PRIM_TRIANGLE_STRIP
] = V_008958_DI_PT_TRISTRIP
,
60 [PIPE_PRIM_TRIANGLE_FAN
] = V_008958_DI_PT_TRIFAN
,
61 [PIPE_PRIM_QUADS
] = V_008958_DI_PT_QUADLIST
,
62 [PIPE_PRIM_QUAD_STRIP
] = V_008958_DI_PT_QUADSTRIP
,
63 [PIPE_PRIM_POLYGON
] = V_008958_DI_PT_POLYGON
,
64 [PIPE_PRIM_LINES_ADJACENCY
] = V_008958_DI_PT_LINELIST_ADJ
,
65 [PIPE_PRIM_LINE_STRIP_ADJACENCY
] = V_008958_DI_PT_LINESTRIP_ADJ
,
66 [PIPE_PRIM_TRIANGLES_ADJACENCY
] = V_008958_DI_PT_TRILIST_ADJ
,
67 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY
] = V_008958_DI_PT_TRISTRIP_ADJ
,
68 [PIPE_PRIM_PATCHES
] = V_008958_DI_PT_PATCH
,
69 [R600_PRIM_RECTANGLE_LIST
] = V_008958_DI_PT_RECTLIST
71 assert(mode
< Elements(prim_conv
));
72 return prim_conv
[mode
];
75 static unsigned si_conv_prim_to_gs_out(unsigned mode
)
77 static const int prim_conv
[] = {
78 [PIPE_PRIM_POINTS
] = V_028A6C_OUTPRIM_TYPE_POINTLIST
,
79 [PIPE_PRIM_LINES
] = V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
80 [PIPE_PRIM_LINE_LOOP
] = V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
81 [PIPE_PRIM_LINE_STRIP
] = V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
82 [PIPE_PRIM_TRIANGLES
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
83 [PIPE_PRIM_TRIANGLE_STRIP
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
84 [PIPE_PRIM_TRIANGLE_FAN
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
85 [PIPE_PRIM_QUADS
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
86 [PIPE_PRIM_QUAD_STRIP
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
87 [PIPE_PRIM_POLYGON
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
88 [PIPE_PRIM_LINES_ADJACENCY
] = V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
89 [PIPE_PRIM_LINE_STRIP_ADJACENCY
] = V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
90 [PIPE_PRIM_TRIANGLES_ADJACENCY
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
91 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
92 [PIPE_PRIM_PATCHES
] = V_028A6C_OUTPRIM_TYPE_POINTLIST
,
93 [R600_PRIM_RECTANGLE_LIST
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
95 assert(mode
< Elements(prim_conv
));
97 return prim_conv
[mode
];
101 * This calculates the LDS size for tessellation shaders (VS, TCS, TES).
102 * LS.LDS_SIZE is shared by all 3 shader stages.
104 * The information about LDS and other non-compile-time parameters is then
105 * written to userdata SGPRs.
107 static void si_emit_derived_tess_state(struct si_context
*sctx
,
108 const struct pipe_draw_info
*info
,
109 unsigned *num_patches
)
111 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
112 struct si_shader_ctx_state
*ls
= &sctx
->vs_shader
;
113 /* The TES pointer will only be used for sctx->last_tcs.
114 * It would be wrong to think that TCS = TES. */
115 struct si_shader_selector
*tcs
=
116 sctx
->tcs_shader
.cso
? sctx
->tcs_shader
.cso
: sctx
->tes_shader
.cso
;
117 unsigned tes_sh_base
= sctx
->shader_userdata
.sh_base
[PIPE_SHADER_TESS_EVAL
];
118 unsigned num_tcs_input_cp
= info
->vertices_per_patch
;
119 unsigned num_tcs_output_cp
, num_tcs_inputs
, num_tcs_outputs
;
120 unsigned num_tcs_patch_outputs
;
121 unsigned input_vertex_size
, output_vertex_size
, pervertex_output_patch_size
;
122 unsigned input_patch_size
, output_patch_size
, output_patch0_offset
;
123 unsigned perpatch_output_offset
, lds_size
, ls_rsrc2
;
124 unsigned tcs_in_layout
, tcs_out_layout
, tcs_out_offsets
;
126 *num_patches
= 1; /* TODO: calculate this */
128 if (sctx
->last_ls
== ls
->current
&&
129 sctx
->last_tcs
== tcs
&&
130 sctx
->last_tes_sh_base
== tes_sh_base
&&
131 sctx
->last_num_tcs_input_cp
== num_tcs_input_cp
)
134 sctx
->last_ls
= ls
->current
;
135 sctx
->last_tcs
= tcs
;
136 sctx
->last_tes_sh_base
= tes_sh_base
;
137 sctx
->last_num_tcs_input_cp
= num_tcs_input_cp
;
139 /* This calculates how shader inputs and outputs among VS, TCS, and TES
140 * are laid out in LDS. */
141 num_tcs_inputs
= util_last_bit64(ls
->cso
->outputs_written
);
143 if (sctx
->tcs_shader
.cso
) {
144 num_tcs_outputs
= util_last_bit64(tcs
->outputs_written
);
145 num_tcs_output_cp
= tcs
->info
.properties
[TGSI_PROPERTY_TCS_VERTICES_OUT
];
146 num_tcs_patch_outputs
= util_last_bit64(tcs
->patch_outputs_written
);
148 /* No TCS. Route varyings from LS to TES. */
149 num_tcs_outputs
= num_tcs_inputs
;
150 num_tcs_output_cp
= num_tcs_input_cp
;
151 num_tcs_patch_outputs
= 2; /* TESSINNER + TESSOUTER */
154 input_vertex_size
= num_tcs_inputs
* 16;
155 output_vertex_size
= num_tcs_outputs
* 16;
157 input_patch_size
= num_tcs_input_cp
* input_vertex_size
;
159 pervertex_output_patch_size
= num_tcs_output_cp
* output_vertex_size
;
160 output_patch_size
= pervertex_output_patch_size
+ num_tcs_patch_outputs
* 16;
162 output_patch0_offset
= sctx
->tcs_shader
.cso
? input_patch_size
* *num_patches
: 0;
163 perpatch_output_offset
= output_patch0_offset
+ pervertex_output_patch_size
;
165 lds_size
= output_patch0_offset
+ output_patch_size
* *num_patches
;
166 ls_rsrc2
= ls
->current
->config
.rsrc2
;
168 if (sctx
->b
.chip_class
>= CIK
) {
169 assert(lds_size
<= 65536);
170 ls_rsrc2
|= S_00B52C_LDS_SIZE(align(lds_size
, 512) / 512);
172 assert(lds_size
<= 32768);
173 ls_rsrc2
|= S_00B52C_LDS_SIZE(align(lds_size
, 256) / 256);
176 /* Due to a hw bug, RSRC2_LS must be written twice with another
177 * LS register written in between. */
178 if (sctx
->b
.chip_class
== CIK
&& sctx
->b
.family
!= CHIP_HAWAII
)
179 radeon_set_sh_reg(cs
, R_00B52C_SPI_SHADER_PGM_RSRC2_LS
, ls_rsrc2
);
180 radeon_set_sh_reg_seq(cs
, R_00B528_SPI_SHADER_PGM_RSRC1_LS
, 2);
181 radeon_emit(cs
, ls
->current
->config
.rsrc1
);
182 radeon_emit(cs
, ls_rsrc2
);
184 /* Compute userdata SGPRs. */
185 assert(((input_vertex_size
/ 4) & ~0xff) == 0);
186 assert(((output_vertex_size
/ 4) & ~0xff) == 0);
187 assert(((input_patch_size
/ 4) & ~0x1fff) == 0);
188 assert(((output_patch_size
/ 4) & ~0x1fff) == 0);
189 assert(((output_patch0_offset
/ 16) & ~0xffff) == 0);
190 assert(((perpatch_output_offset
/ 16) & ~0xffff) == 0);
191 assert(num_tcs_input_cp
<= 32);
192 assert(num_tcs_output_cp
<= 32);
194 tcs_in_layout
= (input_patch_size
/ 4) |
195 ((input_vertex_size
/ 4) << 13);
196 tcs_out_layout
= (output_patch_size
/ 4) |
197 ((output_vertex_size
/ 4) << 13);
198 tcs_out_offsets
= (output_patch0_offset
/ 16) |
199 ((perpatch_output_offset
/ 16) << 16);
201 /* Set them for LS. */
202 radeon_set_sh_reg(cs
,
203 R_00B530_SPI_SHADER_USER_DATA_LS_0
+ SI_SGPR_LS_OUT_LAYOUT
* 4,
206 /* Set them for TCS. */
207 radeon_set_sh_reg_seq(cs
,
208 R_00B430_SPI_SHADER_USER_DATA_HS_0
+ SI_SGPR_TCS_OUT_OFFSETS
* 4, 3);
209 radeon_emit(cs
, tcs_out_offsets
);
210 radeon_emit(cs
, tcs_out_layout
| (num_tcs_input_cp
<< 26));
211 radeon_emit(cs
, tcs_in_layout
);
213 /* Set them for TES. */
214 radeon_set_sh_reg_seq(cs
, tes_sh_base
+ SI_SGPR_TCS_OUT_OFFSETS
* 4, 2);
215 radeon_emit(cs
, tcs_out_offsets
);
216 radeon_emit(cs
, tcs_out_layout
| (num_tcs_output_cp
<< 26));
219 static unsigned si_num_prims_for_vertices(const struct pipe_draw_info
*info
)
221 switch (info
->mode
) {
222 case PIPE_PRIM_PATCHES
:
223 return info
->count
/ info
->vertices_per_patch
;
224 case R600_PRIM_RECTANGLE_LIST
:
225 return info
->count
/ 3;
227 return u_prims_for_vertices(info
->mode
, info
->count
);
231 static unsigned si_get_ia_multi_vgt_param(struct si_context
*sctx
,
232 const struct pipe_draw_info
*info
,
233 unsigned num_patches
)
235 struct si_state_rasterizer
*rs
= sctx
->queued
.named
.rasterizer
;
236 unsigned prim
= info
->mode
;
237 unsigned primgroup_size
= 128; /* recommended without a GS */
238 unsigned max_primgroup_in_wave
= 2;
240 /* SWITCH_ON_EOP(0) is always preferable. */
241 bool wd_switch_on_eop
= false;
242 bool ia_switch_on_eop
= false;
243 bool ia_switch_on_eoi
= false;
244 bool partial_vs_wave
= false;
245 bool partial_es_wave
= false;
247 if (sctx
->gs_shader
.cso
)
248 primgroup_size
= 64; /* recommended with a GS */
250 if (sctx
->tes_shader
.cso
) {
251 unsigned num_cp_out
=
252 sctx
->tcs_shader
.cso
?
253 sctx
->tcs_shader
.cso
->info
.properties
[TGSI_PROPERTY_TCS_VERTICES_OUT
] :
254 info
->vertices_per_patch
;
255 unsigned max_size
= 256 / MAX2(info
->vertices_per_patch
, num_cp_out
);
257 primgroup_size
= MIN2(primgroup_size
, max_size
);
259 /* primgroup_size must be set to a multiple of NUM_PATCHES */
260 primgroup_size
= (primgroup_size
/ num_patches
) * num_patches
;
262 /* SWITCH_ON_EOI must be set if PrimID is used. */
263 if ((sctx
->tcs_shader
.cso
&& sctx
->tcs_shader
.cso
->info
.uses_primid
) ||
264 sctx
->tes_shader
.cso
->info
.uses_primid
)
265 ia_switch_on_eoi
= true;
267 /* Bug with tessellation and GS on Bonaire and older 2 SE chips. */
268 if ((sctx
->b
.family
== CHIP_TAHITI
||
269 sctx
->b
.family
== CHIP_PITCAIRN
||
270 sctx
->b
.family
== CHIP_BONAIRE
) &&
272 partial_vs_wave
= true;
275 /* This is a hardware requirement. */
276 if ((rs
&& rs
->line_stipple_enable
) ||
277 (sctx
->b
.screen
->debug_flags
& DBG_SWITCH_ON_EOP
)) {
278 ia_switch_on_eop
= true;
279 wd_switch_on_eop
= true;
282 if (sctx
->b
.chip_class
>= CIK
) {
283 /* WD_SWITCH_ON_EOP has no effect on GPUs with less than
284 * 4 shader engines. Set 1 to pass the assertion below.
285 * The other cases are hardware requirements. */
286 if (sctx
->b
.screen
->info
.max_se
< 4 ||
287 prim
== PIPE_PRIM_POLYGON
||
288 prim
== PIPE_PRIM_LINE_LOOP
||
289 prim
== PIPE_PRIM_TRIANGLE_FAN
||
290 prim
== PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY
||
291 info
->primitive_restart
||
292 info
->count_from_stream_output
)
293 wd_switch_on_eop
= true;
295 /* Hawaii hangs if instancing is enabled and WD_SWITCH_ON_EOP is 0.
296 * We don't know that for indirect drawing, so treat it as
297 * always problematic. */
298 if (sctx
->b
.family
== CHIP_HAWAII
&&
299 (info
->indirect
|| info
->instance_count
> 1))
300 wd_switch_on_eop
= true;
302 /* Required on CIK and later. */
303 if (sctx
->b
.screen
->info
.max_se
> 2 && !wd_switch_on_eop
)
304 ia_switch_on_eoi
= true;
306 /* Required by Hawaii and, for some special cases, by VI. */
307 if (ia_switch_on_eoi
&&
308 (sctx
->b
.family
== CHIP_HAWAII
||
309 (sctx
->b
.chip_class
== VI
&&
310 (sctx
->gs_shader
.cso
|| max_primgroup_in_wave
!= 2))))
311 partial_vs_wave
= true;
313 /* Instancing bug on Bonaire. */
314 if (sctx
->b
.family
== CHIP_BONAIRE
&& ia_switch_on_eoi
&&
315 (info
->indirect
|| info
->instance_count
> 1))
316 partial_vs_wave
= true;
318 /* If the WD switch is false, the IA switch must be false too. */
319 assert(wd_switch_on_eop
|| !ia_switch_on_eop
);
322 /* If SWITCH_ON_EOI is set, PARTIAL_ES_WAVE must be set too. */
323 if (ia_switch_on_eoi
)
324 partial_es_wave
= true;
326 /* GS requirement. */
327 if (SI_GS_PER_ES
/ primgroup_size
>= sctx
->screen
->gs_table_depth
- 3)
328 partial_es_wave
= true;
330 /* Hw bug with single-primitive instances and SWITCH_ON_EOI
331 * on multi-SE chips. */
332 if (sctx
->b
.screen
->info
.max_se
>= 2 && ia_switch_on_eoi
&&
334 (info
->instance_count
> 1 &&
335 si_num_prims_for_vertices(info
) <= 1)))
336 sctx
->b
.flags
|= SI_CONTEXT_VGT_FLUSH
;
338 return S_028AA8_SWITCH_ON_EOP(ia_switch_on_eop
) |
339 S_028AA8_SWITCH_ON_EOI(ia_switch_on_eoi
) |
340 S_028AA8_PARTIAL_VS_WAVE_ON(partial_vs_wave
) |
341 S_028AA8_PARTIAL_ES_WAVE_ON(partial_es_wave
) |
342 S_028AA8_PRIMGROUP_SIZE(primgroup_size
- 1) |
343 S_028AA8_WD_SWITCH_ON_EOP(sctx
->b
.chip_class
>= CIK
? wd_switch_on_eop
: 0) |
344 S_028AA8_MAX_PRIMGRP_IN_WAVE(sctx
->b
.chip_class
>= VI
?
345 max_primgroup_in_wave
: 0);
348 static unsigned si_get_ls_hs_config(struct si_context
*sctx
,
349 const struct pipe_draw_info
*info
,
350 unsigned num_patches
)
352 unsigned num_output_cp
;
354 if (!sctx
->tes_shader
.cso
)
357 num_output_cp
= sctx
->tcs_shader
.cso
?
358 sctx
->tcs_shader
.cso
->info
.properties
[TGSI_PROPERTY_TCS_VERTICES_OUT
] :
359 info
->vertices_per_patch
;
361 return S_028B58_NUM_PATCHES(num_patches
) |
362 S_028B58_HS_NUM_INPUT_CP(info
->vertices_per_patch
) |
363 S_028B58_HS_NUM_OUTPUT_CP(num_output_cp
);
366 static void si_emit_scratch_reloc(struct si_context
*sctx
)
368 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
370 if (!sctx
->emit_scratch_reloc
)
373 radeon_set_context_reg(cs
, R_0286E8_SPI_TMPRING_SIZE
,
374 sctx
->spi_tmpring_size
);
376 if (sctx
->scratch_buffer
) {
377 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
,
378 sctx
->scratch_buffer
, RADEON_USAGE_READWRITE
,
379 RADEON_PRIO_SCRATCH_BUFFER
);
382 sctx
->emit_scratch_reloc
= false;
385 /* rast_prim is the primitive type after GS. */
386 static void si_emit_rasterizer_prim_state(struct si_context
*sctx
)
388 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
389 unsigned rast_prim
= sctx
->current_rast_prim
;
390 struct si_state_rasterizer
*rs
= sctx
->emitted
.named
.rasterizer
;
392 /* Skip this if not rendering lines. */
393 if (rast_prim
!= PIPE_PRIM_LINES
&&
394 rast_prim
!= PIPE_PRIM_LINE_LOOP
&&
395 rast_prim
!= PIPE_PRIM_LINE_STRIP
&&
396 rast_prim
!= PIPE_PRIM_LINES_ADJACENCY
&&
397 rast_prim
!= PIPE_PRIM_LINE_STRIP_ADJACENCY
)
400 if (rast_prim
== sctx
->last_rast_prim
&&
401 rs
->pa_sc_line_stipple
== sctx
->last_sc_line_stipple
)
404 radeon_set_context_reg(cs
, R_028A0C_PA_SC_LINE_STIPPLE
,
405 rs
->pa_sc_line_stipple
|
406 S_028A0C_AUTO_RESET_CNTL(rast_prim
== PIPE_PRIM_LINES
? 1 :
407 rast_prim
== PIPE_PRIM_LINE_STRIP
? 2 : 0));
409 sctx
->last_rast_prim
= rast_prim
;
410 sctx
->last_sc_line_stipple
= rs
->pa_sc_line_stipple
;
413 static void si_emit_draw_registers(struct si_context
*sctx
,
414 const struct pipe_draw_info
*info
)
416 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
417 unsigned prim
= si_conv_pipe_prim(info
->mode
);
418 unsigned gs_out_prim
= si_conv_prim_to_gs_out(sctx
->current_rast_prim
);
419 unsigned ia_multi_vgt_param
, ls_hs_config
, num_patches
= 0;
421 if (sctx
->tes_shader
.cso
)
422 si_emit_derived_tess_state(sctx
, info
, &num_patches
);
424 ia_multi_vgt_param
= si_get_ia_multi_vgt_param(sctx
, info
, num_patches
);
425 ls_hs_config
= si_get_ls_hs_config(sctx
, info
, num_patches
);
428 if (prim
!= sctx
->last_prim
||
429 ia_multi_vgt_param
!= sctx
->last_multi_vgt_param
||
430 ls_hs_config
!= sctx
->last_ls_hs_config
) {
431 if (sctx
->b
.chip_class
>= CIK
) {
432 radeon_emit(cs
, PKT3(PKT3_DRAW_PREAMBLE
, 2, 0));
433 radeon_emit(cs
, prim
); /* VGT_PRIMITIVE_TYPE */
434 radeon_emit(cs
, ia_multi_vgt_param
); /* IA_MULTI_VGT_PARAM */
435 radeon_emit(cs
, ls_hs_config
); /* VGT_LS_HS_CONFIG */
437 radeon_set_config_reg(cs
, R_008958_VGT_PRIMITIVE_TYPE
, prim
);
438 radeon_set_context_reg(cs
, R_028AA8_IA_MULTI_VGT_PARAM
, ia_multi_vgt_param
);
439 radeon_set_context_reg(cs
, R_028B58_VGT_LS_HS_CONFIG
, ls_hs_config
);
441 sctx
->last_prim
= prim
;
442 sctx
->last_multi_vgt_param
= ia_multi_vgt_param
;
443 sctx
->last_ls_hs_config
= ls_hs_config
;
446 if (gs_out_prim
!= sctx
->last_gs_out_prim
) {
447 radeon_set_context_reg(cs
, R_028A6C_VGT_GS_OUT_PRIM_TYPE
, gs_out_prim
);
448 sctx
->last_gs_out_prim
= gs_out_prim
;
451 /* Primitive restart. */
452 if (info
->primitive_restart
!= sctx
->last_primitive_restart_en
) {
453 radeon_set_context_reg(cs
, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN
, info
->primitive_restart
);
454 sctx
->last_primitive_restart_en
= info
->primitive_restart
;
456 if (info
->primitive_restart
&&
457 (info
->restart_index
!= sctx
->last_restart_index
||
458 sctx
->last_restart_index
== SI_RESTART_INDEX_UNKNOWN
)) {
459 radeon_set_context_reg(cs
, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX
,
460 info
->restart_index
);
461 sctx
->last_restart_index
= info
->restart_index
;
466 static void si_emit_draw_packets(struct si_context
*sctx
,
467 const struct pipe_draw_info
*info
,
468 const struct pipe_index_buffer
*ib
)
470 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
471 unsigned sh_base_reg
= sctx
->shader_userdata
.sh_base
[PIPE_SHADER_VERTEX
];
472 bool render_cond_bit
= sctx
->b
.render_cond
&& !sctx
->b
.render_cond_force_off
;
474 if (info
->count_from_stream_output
) {
475 struct r600_so_target
*t
=
476 (struct r600_so_target
*)info
->count_from_stream_output
;
477 uint64_t va
= t
->buf_filled_size
->gpu_address
+
478 t
->buf_filled_size_offset
;
480 radeon_set_context_reg(cs
, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE
,
483 radeon_emit(cs
, PKT3(PKT3_COPY_DATA
, 4, 0));
484 radeon_emit(cs
, COPY_DATA_SRC_SEL(COPY_DATA_MEM
) |
485 COPY_DATA_DST_SEL(COPY_DATA_REG
) |
486 COPY_DATA_WR_CONFIRM
);
487 radeon_emit(cs
, va
); /* src address lo */
488 radeon_emit(cs
, va
>> 32); /* src address hi */
489 radeon_emit(cs
, R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE
>> 2);
490 radeon_emit(cs
, 0); /* unused */
492 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
,
493 t
->buf_filled_size
, RADEON_USAGE_READ
,
494 RADEON_PRIO_SO_FILLED_SIZE
);
499 radeon_emit(cs
, PKT3(PKT3_INDEX_TYPE
, 0, 0));
502 switch (ib
->index_size
) {
504 radeon_emit(cs
, V_028A7C_VGT_INDEX_8
);
507 radeon_emit(cs
, V_028A7C_VGT_INDEX_16
|
508 (SI_BIG_ENDIAN
&& sctx
->b
.chip_class
<= CIK
?
509 V_028A7C_VGT_DMA_SWAP_16_BIT
: 0));
512 radeon_emit(cs
, V_028A7C_VGT_INDEX_32
|
513 (SI_BIG_ENDIAN
&& sctx
->b
.chip_class
<= CIK
?
514 V_028A7C_VGT_DMA_SWAP_32_BIT
: 0));
517 assert(!"unreachable");
522 if (!info
->indirect
) {
525 radeon_emit(cs
, PKT3(PKT3_NUM_INSTANCES
, 0, 0));
526 radeon_emit(cs
, info
->instance_count
);
528 /* Base vertex and start instance. */
529 base_vertex
= info
->indexed
? info
->index_bias
: info
->start
;
531 if (base_vertex
!= sctx
->last_base_vertex
||
532 sctx
->last_base_vertex
== SI_BASE_VERTEX_UNKNOWN
||
533 info
->start_instance
!= sctx
->last_start_instance
||
534 sh_base_reg
!= sctx
->last_sh_base_reg
) {
535 radeon_set_sh_reg_seq(cs
, sh_base_reg
+ SI_SGPR_BASE_VERTEX
* 4, 2);
536 radeon_emit(cs
, base_vertex
);
537 radeon_emit(cs
, info
->start_instance
);
539 sctx
->last_base_vertex
= base_vertex
;
540 sctx
->last_start_instance
= info
->start_instance
;
541 sctx
->last_sh_base_reg
= sh_base_reg
;
544 si_invalidate_draw_sh_constants(sctx
);
546 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
,
547 (struct r600_resource
*)info
->indirect
,
548 RADEON_USAGE_READ
, RADEON_PRIO_DRAW_INDIRECT
);
552 uint32_t index_max_size
= (ib
->buffer
->width0
- ib
->offset
) /
554 uint64_t index_va
= r600_resource(ib
->buffer
)->gpu_address
+ ib
->offset
;
556 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
,
557 (struct r600_resource
*)ib
->buffer
,
558 RADEON_USAGE_READ
, RADEON_PRIO_INDEX_BUFFER
);
560 if (info
->indirect
) {
561 uint64_t indirect_va
= r600_resource(info
->indirect
)->gpu_address
;
563 assert(indirect_va
% 8 == 0);
564 assert(index_va
% 2 == 0);
565 assert(info
->indirect_offset
% 4 == 0);
567 radeon_emit(cs
, PKT3(PKT3_SET_BASE
, 2, 0));
569 radeon_emit(cs
, indirect_va
);
570 radeon_emit(cs
, indirect_va
>> 32);
572 radeon_emit(cs
, PKT3(PKT3_INDEX_BASE
, 1, 0));
573 radeon_emit(cs
, index_va
);
574 radeon_emit(cs
, index_va
>> 32);
576 radeon_emit(cs
, PKT3(PKT3_INDEX_BUFFER_SIZE
, 0, 0));
577 radeon_emit(cs
, index_max_size
);
579 radeon_emit(cs
, PKT3(PKT3_DRAW_INDEX_INDIRECT
, 3, render_cond_bit
));
580 radeon_emit(cs
, info
->indirect_offset
);
581 radeon_emit(cs
, (sh_base_reg
+ SI_SGPR_BASE_VERTEX
* 4 - SI_SH_REG_OFFSET
) >> 2);
582 radeon_emit(cs
, (sh_base_reg
+ SI_SGPR_START_INSTANCE
* 4 - SI_SH_REG_OFFSET
) >> 2);
583 radeon_emit(cs
, V_0287F0_DI_SRC_SEL_DMA
);
585 index_va
+= info
->start
* ib
->index_size
;
587 radeon_emit(cs
, PKT3(PKT3_DRAW_INDEX_2
, 4, render_cond_bit
));
588 radeon_emit(cs
, index_max_size
);
589 radeon_emit(cs
, index_va
);
590 radeon_emit(cs
, (index_va
>> 32UL) & 0xFF);
591 radeon_emit(cs
, info
->count
);
592 radeon_emit(cs
, V_0287F0_DI_SRC_SEL_DMA
);
595 if (info
->indirect
) {
596 uint64_t indirect_va
= r600_resource(info
->indirect
)->gpu_address
;
598 assert(indirect_va
% 8 == 0);
599 assert(info
->indirect_offset
% 4 == 0);
601 radeon_emit(cs
, PKT3(PKT3_SET_BASE
, 2, 0));
603 radeon_emit(cs
, indirect_va
);
604 radeon_emit(cs
, indirect_va
>> 32);
606 radeon_emit(cs
, PKT3(PKT3_DRAW_INDIRECT
, 3, render_cond_bit
));
607 radeon_emit(cs
, info
->indirect_offset
);
608 radeon_emit(cs
, (sh_base_reg
+ SI_SGPR_BASE_VERTEX
* 4 - SI_SH_REG_OFFSET
) >> 2);
609 radeon_emit(cs
, (sh_base_reg
+ SI_SGPR_START_INSTANCE
* 4 - SI_SH_REG_OFFSET
) >> 2);
610 radeon_emit(cs
, V_0287F0_DI_SRC_SEL_AUTO_INDEX
);
612 radeon_emit(cs
, PKT3(PKT3_DRAW_INDEX_AUTO
, 1, render_cond_bit
));
613 radeon_emit(cs
, info
->count
);
614 radeon_emit(cs
, V_0287F0_DI_SRC_SEL_AUTO_INDEX
|
615 S_0287F0_USE_OPAQUE(!!info
->count_from_stream_output
));
620 void si_emit_cache_flush(struct si_context
*si_ctx
, struct r600_atom
*atom
)
622 struct r600_common_context
*sctx
= &si_ctx
->b
;
623 struct radeon_winsys_cs
*cs
= sctx
->gfx
.cs
;
624 uint32_t cp_coher_cntl
= 0;
626 PKT3_SHADER_TYPE_S(!!(sctx
->flags
& SI_CONTEXT_FLAG_COMPUTE
));
628 /* SI has a bug that it always flushes ICACHE and KCACHE if either
629 * bit is set. An alternative way is to write SQC_CACHES, but that
630 * doesn't seem to work reliably. Since the bug doesn't affect
631 * correctness (it only does more work than necessary) and
632 * the performance impact is likely negligible, there is no plan
636 if (sctx
->flags
& SI_CONTEXT_INV_ICACHE
)
637 cp_coher_cntl
|= S_0085F0_SH_ICACHE_ACTION_ENA(1);
638 if (sctx
->flags
& SI_CONTEXT_INV_SMEM_L1
)
639 cp_coher_cntl
|= S_0085F0_SH_KCACHE_ACTION_ENA(1);
641 if (sctx
->flags
& SI_CONTEXT_INV_VMEM_L1
)
642 cp_coher_cntl
|= S_0085F0_TCL1_ACTION_ENA(1);
643 if (sctx
->flags
& SI_CONTEXT_INV_GLOBAL_L2
) {
644 cp_coher_cntl
|= S_0085F0_TC_ACTION_ENA(1);
646 /* TODO: this might not be needed. */
647 if (sctx
->chip_class
>= VI
)
648 cp_coher_cntl
|= S_0301F0_TC_WB_ACTION_ENA(1);
651 if (sctx
->flags
& SI_CONTEXT_FLUSH_AND_INV_CB
) {
652 cp_coher_cntl
|= S_0085F0_CB_ACTION_ENA(1) |
653 S_0085F0_CB0_DEST_BASE_ENA(1) |
654 S_0085F0_CB1_DEST_BASE_ENA(1) |
655 S_0085F0_CB2_DEST_BASE_ENA(1) |
656 S_0085F0_CB3_DEST_BASE_ENA(1) |
657 S_0085F0_CB4_DEST_BASE_ENA(1) |
658 S_0085F0_CB5_DEST_BASE_ENA(1) |
659 S_0085F0_CB6_DEST_BASE_ENA(1) |
660 S_0085F0_CB7_DEST_BASE_ENA(1);
662 /* Necessary for DCC */
663 if (sctx
->chip_class
>= VI
) {
664 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE_EOP
, 4, 0) | compute
);
665 radeon_emit(cs
, EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_DATA_TS
) |
673 if (sctx
->flags
& SI_CONTEXT_FLUSH_AND_INV_DB
) {
674 cp_coher_cntl
|= S_0085F0_DB_ACTION_ENA(1) |
675 S_0085F0_DB_DEST_BASE_ENA(1);
678 if (sctx
->flags
& SI_CONTEXT_FLUSH_AND_INV_CB_META
) {
679 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0) | compute
);
680 radeon_emit(cs
, EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_META
) | EVENT_INDEX(0));
682 if (sctx
->flags
& SI_CONTEXT_FLUSH_AND_INV_DB_META
) {
683 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0) | compute
);
684 radeon_emit(cs
, EVENT_TYPE(V_028A90_FLUSH_AND_INV_DB_META
) | EVENT_INDEX(0));
686 if (sctx
->flags
& SI_CONTEXT_FLUSH_WITH_INV_L2
) {
687 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0) | compute
);
688 radeon_emit(cs
, EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH
) | EVENT_INDEX(7) |
692 /* FLUSH_AND_INV events must be emitted before PS_PARTIAL_FLUSH.
693 * Otherwise, clearing CMASK (CB meta) with CP DMA isn't reliable.
695 * I think the reason is that FLUSH_AND_INV is only added to a queue
696 * and it is PS_PARTIAL_FLUSH that waits for it to complete.
698 if (sctx
->flags
& SI_CONTEXT_PS_PARTIAL_FLUSH
) {
699 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0) | compute
);
700 radeon_emit(cs
, EVENT_TYPE(V_028A90_PS_PARTIAL_FLUSH
) | EVENT_INDEX(4));
701 } else if (sctx
->flags
& SI_CONTEXT_VS_PARTIAL_FLUSH
) {
702 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0) | compute
);
703 radeon_emit(cs
, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH
) | EVENT_INDEX(4));
705 if (sctx
->flags
& SI_CONTEXT_CS_PARTIAL_FLUSH
) {
706 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0) | compute
);
707 radeon_emit(cs
, EVENT_TYPE(V_028A90_CS_PARTIAL_FLUSH
| EVENT_INDEX(4)));
709 if (sctx
->flags
& SI_CONTEXT_VGT_FLUSH
) {
710 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0) | compute
);
711 radeon_emit(cs
, EVENT_TYPE(V_028A90_VGT_FLUSH
) | EVENT_INDEX(0));
713 if (sctx
->flags
& SI_CONTEXT_VGT_STREAMOUT_SYNC
) {
714 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0) | compute
);
715 radeon_emit(cs
, EVENT_TYPE(V_028A90_VGT_STREAMOUT_SYNC
) | EVENT_INDEX(0));
718 /* SURFACE_SYNC must be emitted after partial flushes.
719 * It looks like SURFACE_SYNC flushes caches immediately and doesn't
720 * wait for any engines. This should be last.
723 if (sctx
->chip_class
>= CIK
) {
724 radeon_emit(cs
, PKT3(PKT3_ACQUIRE_MEM
, 5, 0) | compute
);
725 radeon_emit(cs
, cp_coher_cntl
); /* CP_COHER_CNTL */
726 radeon_emit(cs
, 0xffffffff); /* CP_COHER_SIZE */
727 radeon_emit(cs
, 0xff); /* CP_COHER_SIZE_HI */
728 radeon_emit(cs
, 0); /* CP_COHER_BASE */
729 radeon_emit(cs
, 0); /* CP_COHER_BASE_HI */
730 radeon_emit(cs
, 0x0000000A); /* POLL_INTERVAL */
732 radeon_emit(cs
, PKT3(PKT3_SURFACE_SYNC
, 3, 0) | compute
);
733 radeon_emit(cs
, cp_coher_cntl
); /* CP_COHER_CNTL */
734 radeon_emit(cs
, 0xffffffff); /* CP_COHER_SIZE */
735 radeon_emit(cs
, 0); /* CP_COHER_BASE */
736 radeon_emit(cs
, 0x0000000A); /* POLL_INTERVAL */
743 static void si_get_draw_start_count(struct si_context
*sctx
,
744 const struct pipe_draw_info
*info
,
745 unsigned *start
, unsigned *count
)
747 if (info
->indirect
) {
748 struct r600_resource
*indirect
=
749 (struct r600_resource
*)info
->indirect
;
750 int *data
= r600_buffer_map_sync_with_rings(&sctx
->b
,
751 indirect
, PIPE_TRANSFER_READ
);
752 data
+= info
->indirect_offset
/sizeof(int);
756 *start
= info
->start
;
757 *count
= info
->count
;
761 void si_draw_vbo(struct pipe_context
*ctx
, const struct pipe_draw_info
*info
)
763 struct si_context
*sctx
= (struct si_context
*)ctx
;
764 struct si_state_rasterizer
*rs
= sctx
->queued
.named
.rasterizer
;
765 struct pipe_index_buffer ib
= {};
768 if (!info
->count
&& !info
->indirect
&&
769 (info
->indexed
|| !info
->count_from_stream_output
))
772 if (!sctx
->vs_shader
.cso
) {
776 if (!sctx
->ps_shader
.cso
&& (!rs
|| !rs
->rasterizer_discard
)) {
780 if (!!sctx
->tes_shader
.cso
!= (info
->mode
== PIPE_PRIM_PATCHES
)) {
785 si_decompress_textures(sctx
);
787 /* Set the rasterization primitive type.
789 * This must be done after si_decompress_textures, which can call
790 * draw_vbo recursively, and before si_update_shaders, which uses
791 * current_rast_prim for this draw_vbo call. */
792 if (sctx
->gs_shader
.cso
)
793 sctx
->current_rast_prim
= sctx
->gs_shader
.cso
->gs_output_prim
;
794 else if (sctx
->tes_shader
.cso
)
795 sctx
->current_rast_prim
=
796 sctx
->tes_shader
.cso
->info
.properties
[TGSI_PROPERTY_TES_PRIM_MODE
];
798 sctx
->current_rast_prim
= info
->mode
;
800 if (!si_update_shaders(sctx
) ||
801 !si_upload_shader_descriptors(sctx
))
805 /* Initialize the index buffer struct. */
806 pipe_resource_reference(&ib
.buffer
, sctx
->index_buffer
.buffer
);
807 ib
.user_buffer
= sctx
->index_buffer
.user_buffer
;
808 ib
.index_size
= sctx
->index_buffer
.index_size
;
809 ib
.offset
= sctx
->index_buffer
.offset
;
811 /* Translate or upload, if needed. */
812 /* 8-bit indices are supported on VI. */
813 if (sctx
->b
.chip_class
<= CIK
&& ib
.index_size
== 1) {
814 struct pipe_resource
*out_buffer
= NULL
;
815 unsigned out_offset
, start
, count
, start_offset
;
818 si_get_draw_start_count(sctx
, info
, &start
, &count
);
819 start_offset
= start
* ib
.index_size
;
821 u_upload_alloc(sctx
->b
.uploader
, start_offset
, count
* 2, 256,
822 &out_offset
, &out_buffer
, &ptr
);
824 pipe_resource_reference(&ib
.buffer
, NULL
);
828 util_shorten_ubyte_elts_to_userptr(&sctx
->b
.b
, &ib
, 0,
829 ib
.offset
+ start_offset
,
832 pipe_resource_reference(&ib
.buffer
, NULL
);
833 ib
.user_buffer
= NULL
;
834 ib
.buffer
= out_buffer
;
835 /* info->start will be added by the drawing code */
836 ib
.offset
= out_offset
- start_offset
;
838 } else if (ib
.user_buffer
&& !ib
.buffer
) {
839 unsigned start
, count
, start_offset
;
841 si_get_draw_start_count(sctx
, info
, &start
, &count
);
842 start_offset
= start
* ib
.index_size
;
844 u_upload_data(sctx
->b
.uploader
, start_offset
, count
* ib
.index_size
,
845 256, (char*)ib
.user_buffer
+ start_offset
,
846 &ib
.offset
, &ib
.buffer
);
849 /* info->start will be added by the drawing code */
850 ib
.offset
-= start_offset
;
854 /* VI reads index buffers through TC L2. */
855 if (info
->indexed
&& sctx
->b
.chip_class
<= CIK
&&
856 r600_resource(ib
.buffer
)->TC_L2_dirty
) {
857 sctx
->b
.flags
|= SI_CONTEXT_INV_GLOBAL_L2
;
858 r600_resource(ib
.buffer
)->TC_L2_dirty
= false;
861 /* Check flush flags. */
863 si_mark_atom_dirty(sctx
, sctx
->atoms
.s
.cache_flush
);
865 si_need_cs_space(sctx
);
868 mask
= sctx
->dirty_atoms
;
870 struct r600_atom
*atom
= sctx
->atoms
.array
[u_bit_scan(&mask
)];
872 atom
->emit(&sctx
->b
, atom
);
874 sctx
->dirty_atoms
= 0;
876 si_pm4_emit_dirty(sctx
);
877 si_emit_scratch_reloc(sctx
);
878 si_emit_rasterizer_prim_state(sctx
);
879 si_emit_draw_registers(sctx
, info
);
880 si_emit_draw_packets(sctx
, info
, &ib
);
885 /* Workaround for a VGT hang when streamout is enabled.
886 * It must be done after drawing. */
887 if ((sctx
->b
.family
== CHIP_HAWAII
||
888 sctx
->b
.family
== CHIP_TONGA
||
889 sctx
->b
.family
== CHIP_FIJI
) &&
890 (sctx
->b
.streamout
.streamout_enabled
||
891 sctx
->b
.streamout
.prims_gen_query_enabled
)) {
892 sctx
->b
.flags
|= SI_CONTEXT_VGT_STREAMOUT_SYNC
;
895 /* Set the depth buffer as dirty. */
896 if (sctx
->framebuffer
.state
.zsbuf
) {
897 struct pipe_surface
*surf
= sctx
->framebuffer
.state
.zsbuf
;
898 struct r600_texture
*rtex
= (struct r600_texture
*)surf
->texture
;
900 rtex
->dirty_level_mask
|= 1 << surf
->u
.tex
.level
;
902 if (rtex
->surface
.flags
& RADEON_SURF_SBUFFER
)
903 rtex
->stencil_dirty_level_mask
|= 1 << surf
->u
.tex
.level
;
905 if (sctx
->framebuffer
.compressed_cb_mask
) {
906 struct pipe_surface
*surf
;
907 struct r600_texture
*rtex
;
908 unsigned mask
= sctx
->framebuffer
.compressed_cb_mask
;
911 unsigned i
= u_bit_scan(&mask
);
912 surf
= sctx
->framebuffer
.state
.cbufs
[i
];
913 rtex
= (struct r600_texture
*)surf
->texture
;
915 rtex
->dirty_level_mask
|= 1 << surf
->u
.tex
.level
;
919 pipe_resource_reference(&ib
.buffer
, NULL
);
920 sctx
->b
.num_draw_calls
++;
923 void si_trace_emit(struct si_context
*sctx
)
925 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
928 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
, sctx
->trace_buf
,
929 RADEON_USAGE_READWRITE
, RADEON_PRIO_TRACE
);
930 radeon_emit(cs
, PKT3(PKT3_WRITE_DATA
, 3, 0));
931 radeon_emit(cs
, S_370_DST_SEL(V_370_MEMORY_SYNC
) |
932 S_370_WR_CONFIRM(1) |
933 S_370_ENGINE_SEL(V_370_ME
));
934 radeon_emit(cs
, sctx
->trace_buf
->gpu_address
);
935 radeon_emit(cs
, sctx
->trace_buf
->gpu_address
>> 32);
936 radeon_emit(cs
, sctx
->trace_id
);
937 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
938 radeon_emit(cs
, SI_ENCODE_TRACE_POINT(sctx
->trace_id
));