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[mesa.git] / src / gallium / drivers / radeonsi / si_state_draw.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24 #include "si_pipe.h"
25 #include "radeon/r600_cs.h"
26 #include "sid.h"
27 #include "gfx9d.h"
28
29 #include "util/u_index_modify.h"
30 #include "util/u_log.h"
31 #include "util/u_upload_mgr.h"
32 #include "util/u_prim.h"
33
34 #include "ac_debug.h"
35
36 static unsigned si_conv_pipe_prim(unsigned mode)
37 {
38 static const unsigned prim_conv[] = {
39 [PIPE_PRIM_POINTS] = V_008958_DI_PT_POINTLIST,
40 [PIPE_PRIM_LINES] = V_008958_DI_PT_LINELIST,
41 [PIPE_PRIM_LINE_LOOP] = V_008958_DI_PT_LINELOOP,
42 [PIPE_PRIM_LINE_STRIP] = V_008958_DI_PT_LINESTRIP,
43 [PIPE_PRIM_TRIANGLES] = V_008958_DI_PT_TRILIST,
44 [PIPE_PRIM_TRIANGLE_STRIP] = V_008958_DI_PT_TRISTRIP,
45 [PIPE_PRIM_TRIANGLE_FAN] = V_008958_DI_PT_TRIFAN,
46 [PIPE_PRIM_QUADS] = V_008958_DI_PT_QUADLIST,
47 [PIPE_PRIM_QUAD_STRIP] = V_008958_DI_PT_QUADSTRIP,
48 [PIPE_PRIM_POLYGON] = V_008958_DI_PT_POLYGON,
49 [PIPE_PRIM_LINES_ADJACENCY] = V_008958_DI_PT_LINELIST_ADJ,
50 [PIPE_PRIM_LINE_STRIP_ADJACENCY] = V_008958_DI_PT_LINESTRIP_ADJ,
51 [PIPE_PRIM_TRIANGLES_ADJACENCY] = V_008958_DI_PT_TRILIST_ADJ,
52 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY] = V_008958_DI_PT_TRISTRIP_ADJ,
53 [PIPE_PRIM_PATCHES] = V_008958_DI_PT_PATCH,
54 [R600_PRIM_RECTANGLE_LIST] = V_008958_DI_PT_RECTLIST
55 };
56 assert(mode < ARRAY_SIZE(prim_conv));
57 return prim_conv[mode];
58 }
59
60 static unsigned si_conv_prim_to_gs_out(unsigned mode)
61 {
62 static const int prim_conv[] = {
63 [PIPE_PRIM_POINTS] = V_028A6C_OUTPRIM_TYPE_POINTLIST,
64 [PIPE_PRIM_LINES] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
65 [PIPE_PRIM_LINE_LOOP] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
66 [PIPE_PRIM_LINE_STRIP] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
67 [PIPE_PRIM_TRIANGLES] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
68 [PIPE_PRIM_TRIANGLE_STRIP] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
69 [PIPE_PRIM_TRIANGLE_FAN] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
70 [PIPE_PRIM_QUADS] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
71 [PIPE_PRIM_QUAD_STRIP] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
72 [PIPE_PRIM_POLYGON] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
73 [PIPE_PRIM_LINES_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
74 [PIPE_PRIM_LINE_STRIP_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
75 [PIPE_PRIM_TRIANGLES_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
76 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
77 [PIPE_PRIM_PATCHES] = V_028A6C_OUTPRIM_TYPE_POINTLIST,
78 [R600_PRIM_RECTANGLE_LIST] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
79 };
80 assert(mode < ARRAY_SIZE(prim_conv));
81
82 return prim_conv[mode];
83 }
84
85 /**
86 * This calculates the LDS size for tessellation shaders (VS, TCS, TES).
87 * LS.LDS_SIZE is shared by all 3 shader stages.
88 *
89 * The information about LDS and other non-compile-time parameters is then
90 * written to userdata SGPRs.
91 */
92 static void si_emit_derived_tess_state(struct si_context *sctx,
93 const struct pipe_draw_info *info,
94 unsigned *num_patches)
95 {
96 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
97 struct si_shader *ls_current;
98 struct si_shader_selector *ls;
99 /* The TES pointer will only be used for sctx->last_tcs.
100 * It would be wrong to think that TCS = TES. */
101 struct si_shader_selector *tcs =
102 sctx->tcs_shader.cso ? sctx->tcs_shader.cso : sctx->tes_shader.cso;
103 unsigned tess_uses_primid = sctx->ia_multi_vgt_param_key.u.tess_uses_prim_id;
104 bool has_primid_instancing_bug = sctx->b.chip_class == SI &&
105 sctx->b.screen->info.max_se == 1;
106 unsigned tes_sh_base = sctx->shader_pointers.sh_base[PIPE_SHADER_TESS_EVAL];
107 unsigned num_tcs_input_cp = info->vertices_per_patch;
108 unsigned num_tcs_output_cp, num_tcs_inputs, num_tcs_outputs;
109 unsigned num_tcs_patch_outputs;
110 unsigned input_vertex_size, output_vertex_size, pervertex_output_patch_size;
111 unsigned input_patch_size, output_patch_size, output_patch0_offset;
112 unsigned perpatch_output_offset, lds_size;
113 unsigned tcs_in_layout, tcs_out_layout, tcs_out_offsets;
114 unsigned offchip_layout, hardware_lds_size, ls_hs_config;
115
116 /* Since GFX9 has merged LS-HS in the TCS state, set LS = TCS. */
117 if (sctx->b.chip_class >= GFX9) {
118 if (sctx->tcs_shader.cso)
119 ls_current = sctx->tcs_shader.current;
120 else
121 ls_current = sctx->fixed_func_tcs_shader.current;
122
123 ls = ls_current->key.part.tcs.ls;
124 } else {
125 ls_current = sctx->vs_shader.current;
126 ls = sctx->vs_shader.cso;
127 }
128
129 if (sctx->last_ls == ls_current &&
130 sctx->last_tcs == tcs &&
131 sctx->last_tes_sh_base == tes_sh_base &&
132 sctx->last_num_tcs_input_cp == num_tcs_input_cp &&
133 (!has_primid_instancing_bug ||
134 (sctx->last_tess_uses_primid == tess_uses_primid))) {
135 *num_patches = sctx->last_num_patches;
136 return;
137 }
138
139 sctx->last_ls = ls_current;
140 sctx->last_tcs = tcs;
141 sctx->last_tes_sh_base = tes_sh_base;
142 sctx->last_num_tcs_input_cp = num_tcs_input_cp;
143 sctx->last_tess_uses_primid = tess_uses_primid;
144
145 /* This calculates how shader inputs and outputs among VS, TCS, and TES
146 * are laid out in LDS. */
147 num_tcs_inputs = util_last_bit64(ls->outputs_written);
148
149 if (sctx->tcs_shader.cso) {
150 num_tcs_outputs = util_last_bit64(tcs->outputs_written);
151 num_tcs_output_cp = tcs->info.properties[TGSI_PROPERTY_TCS_VERTICES_OUT];
152 num_tcs_patch_outputs = util_last_bit64(tcs->patch_outputs_written);
153 } else {
154 /* No TCS. Route varyings from LS to TES. */
155 num_tcs_outputs = num_tcs_inputs;
156 num_tcs_output_cp = num_tcs_input_cp;
157 num_tcs_patch_outputs = 2; /* TESSINNER + TESSOUTER */
158 }
159
160 input_vertex_size = num_tcs_inputs * 16;
161 output_vertex_size = num_tcs_outputs * 16;
162
163 input_patch_size = num_tcs_input_cp * input_vertex_size;
164
165 pervertex_output_patch_size = num_tcs_output_cp * output_vertex_size;
166 output_patch_size = pervertex_output_patch_size + num_tcs_patch_outputs * 16;
167
168 /* Ensure that we only need one wave per SIMD so we don't need to check
169 * resource usage. Also ensures that the number of tcs in and out
170 * vertices per threadgroup are at most 256.
171 */
172 *num_patches = 64 / MAX2(num_tcs_input_cp, num_tcs_output_cp) * 4;
173
174 /* Make sure that the data fits in LDS. This assumes the shaders only
175 * use LDS for the inputs and outputs.
176 *
177 * While CIK can use 64K per threadgroup, there is a hang on Stoney
178 * with 2 CUs if we use more than 32K. The closed Vulkan driver also
179 * uses 32K at most on all GCN chips.
180 */
181 hardware_lds_size = 32768;
182 *num_patches = MIN2(*num_patches, hardware_lds_size / (input_patch_size +
183 output_patch_size));
184
185 /* Make sure the output data fits in the offchip buffer */
186 *num_patches = MIN2(*num_patches,
187 (sctx->screen->tess_offchip_block_dw_size * 4) /
188 output_patch_size);
189
190 /* Not necessary for correctness, but improves performance. The
191 * specific value is taken from the proprietary driver.
192 */
193 *num_patches = MIN2(*num_patches, 40);
194
195 if (sctx->b.chip_class == SI) {
196 /* SI bug workaround, related to power management. Limit LS-HS
197 * threadgroups to only one wave.
198 */
199 unsigned one_wave = 64 / MAX2(num_tcs_input_cp, num_tcs_output_cp);
200 *num_patches = MIN2(*num_patches, one_wave);
201 }
202
203 /* The VGT HS block increments the patch ID unconditionally
204 * within a single threadgroup. This results in incorrect
205 * patch IDs when instanced draws are used.
206 *
207 * The intended solution is to restrict threadgroups to
208 * a single instance by setting SWITCH_ON_EOI, which
209 * should cause IA to split instances up. However, this
210 * doesn't work correctly on SI when there is no other
211 * SE to switch to.
212 */
213 if (has_primid_instancing_bug && tess_uses_primid)
214 *num_patches = 1;
215
216 sctx->last_num_patches = *num_patches;
217
218 output_patch0_offset = input_patch_size * *num_patches;
219 perpatch_output_offset = output_patch0_offset + pervertex_output_patch_size;
220
221 /* Compute userdata SGPRs. */
222 assert(((input_vertex_size / 4) & ~0xff) == 0);
223 assert(((output_vertex_size / 4) & ~0xff) == 0);
224 assert(((input_patch_size / 4) & ~0x1fff) == 0);
225 assert(((output_patch_size / 4) & ~0x1fff) == 0);
226 assert(((output_patch0_offset / 16) & ~0xffff) == 0);
227 assert(((perpatch_output_offset / 16) & ~0xffff) == 0);
228 assert(num_tcs_input_cp <= 32);
229 assert(num_tcs_output_cp <= 32);
230
231 tcs_in_layout = S_VS_STATE_LS_OUT_PATCH_SIZE(input_patch_size / 4) |
232 S_VS_STATE_LS_OUT_VERTEX_SIZE(input_vertex_size / 4);
233 tcs_out_layout = output_patch_size / 4;
234 tcs_out_offsets = (output_patch0_offset / 16) |
235 ((perpatch_output_offset / 16) << 16);
236 offchip_layout = *num_patches |
237 (num_tcs_output_cp << 6) |
238 (pervertex_output_patch_size * *num_patches << 12);
239
240 /* Compute the LDS size. */
241 lds_size = output_patch0_offset + output_patch_size * *num_patches;
242
243 if (sctx->b.chip_class >= CIK) {
244 assert(lds_size <= 65536);
245 lds_size = align(lds_size, 512) / 512;
246 } else {
247 assert(lds_size <= 32768);
248 lds_size = align(lds_size, 256) / 256;
249 }
250
251 /* Set SI_SGPR_VS_STATE_BITS. */
252 sctx->current_vs_state &= C_VS_STATE_LS_OUT_PATCH_SIZE &
253 C_VS_STATE_LS_OUT_VERTEX_SIZE;
254 sctx->current_vs_state |= tcs_in_layout;
255
256 if (sctx->b.chip_class >= GFX9) {
257 unsigned hs_rsrc2 = ls_current->config.rsrc2 |
258 S_00B42C_LDS_SIZE(lds_size);
259
260 radeon_set_sh_reg(cs, R_00B42C_SPI_SHADER_PGM_RSRC2_HS, hs_rsrc2);
261
262 /* Set userdata SGPRs for merged LS-HS. */
263 radeon_set_sh_reg_seq(cs,
264 R_00B430_SPI_SHADER_USER_DATA_LS_0 +
265 GFX9_SGPR_TCS_OFFCHIP_LAYOUT * 4, 3);
266 radeon_emit(cs, offchip_layout);
267 radeon_emit(cs, tcs_out_offsets);
268 radeon_emit(cs, tcs_out_layout | (num_tcs_input_cp << 26));
269 } else {
270 unsigned ls_rsrc2 = ls_current->config.rsrc2;
271
272 si_multiwave_lds_size_workaround(sctx->screen, &lds_size);
273 ls_rsrc2 |= S_00B52C_LDS_SIZE(lds_size);
274
275 /* Due to a hw bug, RSRC2_LS must be written twice with another
276 * LS register written in between. */
277 if (sctx->b.chip_class == CIK && sctx->b.family != CHIP_HAWAII)
278 radeon_set_sh_reg(cs, R_00B52C_SPI_SHADER_PGM_RSRC2_LS, ls_rsrc2);
279 radeon_set_sh_reg_seq(cs, R_00B528_SPI_SHADER_PGM_RSRC1_LS, 2);
280 radeon_emit(cs, ls_current->config.rsrc1);
281 radeon_emit(cs, ls_rsrc2);
282
283 /* Set userdata SGPRs for TCS. */
284 radeon_set_sh_reg_seq(cs,
285 R_00B430_SPI_SHADER_USER_DATA_HS_0 + GFX6_SGPR_TCS_OFFCHIP_LAYOUT * 4, 4);
286 radeon_emit(cs, offchip_layout);
287 radeon_emit(cs, tcs_out_offsets);
288 radeon_emit(cs, tcs_out_layout | (num_tcs_input_cp << 26));
289 radeon_emit(cs, tcs_in_layout);
290 }
291
292 /* Set userdata SGPRs for TES. */
293 radeon_set_sh_reg_seq(cs, tes_sh_base + SI_SGPR_TES_OFFCHIP_LAYOUT * 4, 2);
294 radeon_emit(cs, offchip_layout);
295 radeon_emit(cs, r600_resource(sctx->tess_offchip_ring)->gpu_address >> 16);
296
297 ls_hs_config = S_028B58_NUM_PATCHES(*num_patches) |
298 S_028B58_HS_NUM_INPUT_CP(num_tcs_input_cp) |
299 S_028B58_HS_NUM_OUTPUT_CP(num_tcs_output_cp);
300
301 if (sctx->b.chip_class >= CIK)
302 radeon_set_context_reg_idx(cs, R_028B58_VGT_LS_HS_CONFIG, 2,
303 ls_hs_config);
304 else
305 radeon_set_context_reg(cs, R_028B58_VGT_LS_HS_CONFIG,
306 ls_hs_config);
307 }
308
309 static unsigned si_num_prims_for_vertices(const struct pipe_draw_info *info)
310 {
311 switch (info->mode) {
312 case PIPE_PRIM_PATCHES:
313 return info->count / info->vertices_per_patch;
314 case R600_PRIM_RECTANGLE_LIST:
315 return info->count / 3;
316 default:
317 return u_prims_for_vertices(info->mode, info->count);
318 }
319 }
320
321 static unsigned
322 si_get_init_multi_vgt_param(struct si_screen *sscreen,
323 union si_vgt_param_key *key)
324 {
325 STATIC_ASSERT(sizeof(union si_vgt_param_key) == 4);
326 unsigned max_primgroup_in_wave = 2;
327
328 /* SWITCH_ON_EOP(0) is always preferable. */
329 bool wd_switch_on_eop = false;
330 bool ia_switch_on_eop = false;
331 bool ia_switch_on_eoi = false;
332 bool partial_vs_wave = false;
333 bool partial_es_wave = false;
334
335 if (key->u.uses_tess) {
336 /* SWITCH_ON_EOI must be set if PrimID is used. */
337 if (key->u.tess_uses_prim_id)
338 ia_switch_on_eoi = true;
339
340 /* Bug with tessellation and GS on Bonaire and older 2 SE chips. */
341 if ((sscreen->b.family == CHIP_TAHITI ||
342 sscreen->b.family == CHIP_PITCAIRN ||
343 sscreen->b.family == CHIP_BONAIRE) &&
344 key->u.uses_gs)
345 partial_vs_wave = true;
346
347 /* Needed for 028B6C_DISTRIBUTION_MODE != 0 */
348 if (sscreen->has_distributed_tess) {
349 if (key->u.uses_gs) {
350 if (sscreen->b.chip_class <= VI)
351 partial_es_wave = true;
352
353 /* GPU hang workaround. */
354 if (sscreen->b.family == CHIP_TONGA ||
355 sscreen->b.family == CHIP_FIJI ||
356 sscreen->b.family == CHIP_POLARIS10 ||
357 sscreen->b.family == CHIP_POLARIS11 ||
358 sscreen->b.family == CHIP_POLARIS12)
359 partial_vs_wave = true;
360 } else {
361 partial_vs_wave = true;
362 }
363 }
364 }
365
366 /* This is a hardware requirement. */
367 if (key->u.line_stipple_enabled ||
368 (sscreen->b.debug_flags & DBG(SWITCH_ON_EOP))) {
369 ia_switch_on_eop = true;
370 wd_switch_on_eop = true;
371 }
372
373 if (sscreen->b.chip_class >= CIK) {
374 /* WD_SWITCH_ON_EOP has no effect on GPUs with less than
375 * 4 shader engines. Set 1 to pass the assertion below.
376 * The other cases are hardware requirements.
377 *
378 * Polaris supports primitive restart with WD_SWITCH_ON_EOP=0
379 * for points, line strips, and tri strips.
380 */
381 if (sscreen->b.info.max_se < 4 ||
382 key->u.prim == PIPE_PRIM_POLYGON ||
383 key->u.prim == PIPE_PRIM_LINE_LOOP ||
384 key->u.prim == PIPE_PRIM_TRIANGLE_FAN ||
385 key->u.prim == PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY ||
386 (key->u.primitive_restart &&
387 (sscreen->b.family < CHIP_POLARIS10 ||
388 (key->u.prim != PIPE_PRIM_POINTS &&
389 key->u.prim != PIPE_PRIM_LINE_STRIP &&
390 key->u.prim != PIPE_PRIM_TRIANGLE_STRIP))) ||
391 key->u.count_from_stream_output)
392 wd_switch_on_eop = true;
393
394 /* Hawaii hangs if instancing is enabled and WD_SWITCH_ON_EOP is 0.
395 * We don't know that for indirect drawing, so treat it as
396 * always problematic. */
397 if (sscreen->b.family == CHIP_HAWAII &&
398 key->u.uses_instancing)
399 wd_switch_on_eop = true;
400
401 /* Performance recommendation for 4 SE Gfx7-8 parts if
402 * instances are smaller than a primgroup.
403 * Assume indirect draws always use small instances.
404 * This is needed for good VS wave utilization.
405 */
406 if (sscreen->b.chip_class <= VI &&
407 sscreen->b.info.max_se == 4 &&
408 key->u.multi_instances_smaller_than_primgroup)
409 wd_switch_on_eop = true;
410
411 /* Required on CIK and later. */
412 if (sscreen->b.info.max_se > 2 && !wd_switch_on_eop)
413 ia_switch_on_eoi = true;
414
415 /* Required by Hawaii and, for some special cases, by VI. */
416 if (ia_switch_on_eoi &&
417 (sscreen->b.family == CHIP_HAWAII ||
418 (sscreen->b.chip_class == VI &&
419 (key->u.uses_gs || max_primgroup_in_wave != 2))))
420 partial_vs_wave = true;
421
422 /* Instancing bug on Bonaire. */
423 if (sscreen->b.family == CHIP_BONAIRE && ia_switch_on_eoi &&
424 key->u.uses_instancing)
425 partial_vs_wave = true;
426
427 /* If the WD switch is false, the IA switch must be false too. */
428 assert(wd_switch_on_eop || !ia_switch_on_eop);
429 }
430
431 /* If SWITCH_ON_EOI is set, PARTIAL_ES_WAVE must be set too. */
432 if (sscreen->b.chip_class <= VI && ia_switch_on_eoi)
433 partial_es_wave = true;
434
435 return S_028AA8_SWITCH_ON_EOP(ia_switch_on_eop) |
436 S_028AA8_SWITCH_ON_EOI(ia_switch_on_eoi) |
437 S_028AA8_PARTIAL_VS_WAVE_ON(partial_vs_wave) |
438 S_028AA8_PARTIAL_ES_WAVE_ON(partial_es_wave) |
439 S_028AA8_WD_SWITCH_ON_EOP(sscreen->b.chip_class >= CIK ? wd_switch_on_eop : 0) |
440 /* The following field was moved to VGT_SHADER_STAGES_EN in GFX9. */
441 S_028AA8_MAX_PRIMGRP_IN_WAVE(sscreen->b.chip_class == VI ?
442 max_primgroup_in_wave : 0) |
443 S_030960_EN_INST_OPT_BASIC(sscreen->b.chip_class >= GFX9) |
444 S_030960_EN_INST_OPT_ADV(sscreen->b.chip_class >= GFX9);
445 }
446
447 void si_init_ia_multi_vgt_param_table(struct si_context *sctx)
448 {
449 for (int prim = 0; prim <= R600_PRIM_RECTANGLE_LIST; prim++)
450 for (int uses_instancing = 0; uses_instancing < 2; uses_instancing++)
451 for (int multi_instances = 0; multi_instances < 2; multi_instances++)
452 for (int primitive_restart = 0; primitive_restart < 2; primitive_restart++)
453 for (int count_from_so = 0; count_from_so < 2; count_from_so++)
454 for (int line_stipple = 0; line_stipple < 2; line_stipple++)
455 for (int uses_tess = 0; uses_tess < 2; uses_tess++)
456 for (int tess_uses_primid = 0; tess_uses_primid < 2; tess_uses_primid++)
457 for (int uses_gs = 0; uses_gs < 2; uses_gs++) {
458 union si_vgt_param_key key;
459
460 key.index = 0;
461 key.u.prim = prim;
462 key.u.uses_instancing = uses_instancing;
463 key.u.multi_instances_smaller_than_primgroup = multi_instances;
464 key.u.primitive_restart = primitive_restart;
465 key.u.count_from_stream_output = count_from_so;
466 key.u.line_stipple_enabled = line_stipple;
467 key.u.uses_tess = uses_tess;
468 key.u.tess_uses_prim_id = tess_uses_primid;
469 key.u.uses_gs = uses_gs;
470
471 sctx->ia_multi_vgt_param[key.index] =
472 si_get_init_multi_vgt_param(sctx->screen, &key);
473 }
474 }
475
476 static unsigned si_get_ia_multi_vgt_param(struct si_context *sctx,
477 const struct pipe_draw_info *info,
478 unsigned num_patches)
479 {
480 union si_vgt_param_key key = sctx->ia_multi_vgt_param_key;
481 unsigned primgroup_size;
482 unsigned ia_multi_vgt_param;
483
484 if (sctx->tes_shader.cso) {
485 primgroup_size = num_patches; /* must be a multiple of NUM_PATCHES */
486 } else if (sctx->gs_shader.cso) {
487 primgroup_size = 64; /* recommended with a GS */
488 } else {
489 primgroup_size = 128; /* recommended without a GS and tess */
490 }
491
492 key.u.prim = info->mode;
493 key.u.uses_instancing = info->indirect || info->instance_count > 1;
494 key.u.multi_instances_smaller_than_primgroup =
495 info->indirect ||
496 (info->instance_count > 1 &&
497 (info->count_from_stream_output ||
498 si_num_prims_for_vertices(info) < primgroup_size));
499 key.u.primitive_restart = info->primitive_restart;
500 key.u.count_from_stream_output = info->count_from_stream_output != NULL;
501
502 ia_multi_vgt_param = sctx->ia_multi_vgt_param[key.index] |
503 S_028AA8_PRIMGROUP_SIZE(primgroup_size - 1);
504
505 if (sctx->gs_shader.cso) {
506 /* GS requirement. */
507 if (sctx->b.chip_class <= VI &&
508 SI_GS_PER_ES / primgroup_size >= sctx->screen->gs_table_depth - 3)
509 ia_multi_vgt_param |= S_028AA8_PARTIAL_ES_WAVE_ON(1);
510
511 /* GS hw bug with single-primitive instances and SWITCH_ON_EOI.
512 * The hw doc says all multi-SE chips are affected, but Vulkan
513 * only applies it to Hawaii. Do what Vulkan does.
514 */
515 if (sctx->b.family == CHIP_HAWAII &&
516 G_028AA8_SWITCH_ON_EOI(ia_multi_vgt_param) &&
517 (info->indirect ||
518 (info->instance_count > 1 &&
519 (info->count_from_stream_output ||
520 si_num_prims_for_vertices(info) <= 1))))
521 sctx->b.flags |= SI_CONTEXT_VGT_FLUSH;
522 }
523
524 return ia_multi_vgt_param;
525 }
526
527 /* rast_prim is the primitive type after GS. */
528 static void si_emit_rasterizer_prim_state(struct si_context *sctx)
529 {
530 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
531 enum pipe_prim_type rast_prim = sctx->current_rast_prim;
532 struct si_state_rasterizer *rs = sctx->emitted.named.rasterizer;
533
534 /* Skip this if not rendering lines. */
535 if (rast_prim != PIPE_PRIM_LINES &&
536 rast_prim != PIPE_PRIM_LINE_LOOP &&
537 rast_prim != PIPE_PRIM_LINE_STRIP &&
538 rast_prim != PIPE_PRIM_LINES_ADJACENCY &&
539 rast_prim != PIPE_PRIM_LINE_STRIP_ADJACENCY)
540 return;
541
542 if (rast_prim == sctx->last_rast_prim &&
543 rs->pa_sc_line_stipple == sctx->last_sc_line_stipple)
544 return;
545
546 /* For lines, reset the stipple pattern at each primitive. Otherwise,
547 * reset the stipple pattern at each packet (line strips, line loops).
548 */
549 radeon_set_context_reg(cs, R_028A0C_PA_SC_LINE_STIPPLE,
550 rs->pa_sc_line_stipple |
551 S_028A0C_AUTO_RESET_CNTL(rast_prim == PIPE_PRIM_LINES ? 1 : 2));
552
553 sctx->last_rast_prim = rast_prim;
554 sctx->last_sc_line_stipple = rs->pa_sc_line_stipple;
555 }
556
557 static void si_emit_vs_state(struct si_context *sctx,
558 const struct pipe_draw_info *info)
559 {
560 sctx->current_vs_state &= C_VS_STATE_INDEXED;
561 sctx->current_vs_state |= S_VS_STATE_INDEXED(!!info->index_size);
562
563 if (sctx->num_vs_blit_sgprs) {
564 /* Re-emit the state after we leave u_blitter. */
565 sctx->last_vs_state = ~0;
566 return;
567 }
568
569 if (sctx->current_vs_state != sctx->last_vs_state) {
570 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
571
572 radeon_set_sh_reg(cs,
573 sctx->shader_pointers.sh_base[PIPE_SHADER_VERTEX] +
574 SI_SGPR_VS_STATE_BITS * 4,
575 sctx->current_vs_state);
576
577 sctx->last_vs_state = sctx->current_vs_state;
578 }
579 }
580
581 static void si_emit_draw_registers(struct si_context *sctx,
582 const struct pipe_draw_info *info,
583 unsigned num_patches)
584 {
585 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
586 unsigned prim = si_conv_pipe_prim(info->mode);
587 unsigned gs_out_prim = si_conv_prim_to_gs_out(sctx->current_rast_prim);
588 unsigned ia_multi_vgt_param;
589
590 ia_multi_vgt_param = si_get_ia_multi_vgt_param(sctx, info, num_patches);
591
592 /* Draw state. */
593 if (ia_multi_vgt_param != sctx->last_multi_vgt_param) {
594 if (sctx->b.chip_class >= GFX9)
595 radeon_set_uconfig_reg_idx(cs, R_030960_IA_MULTI_VGT_PARAM, 4, ia_multi_vgt_param);
596 else if (sctx->b.chip_class >= CIK)
597 radeon_set_context_reg_idx(cs, R_028AA8_IA_MULTI_VGT_PARAM, 1, ia_multi_vgt_param);
598 else
599 radeon_set_context_reg(cs, R_028AA8_IA_MULTI_VGT_PARAM, ia_multi_vgt_param);
600
601 sctx->last_multi_vgt_param = ia_multi_vgt_param;
602 }
603 if (prim != sctx->last_prim) {
604 if (sctx->b.chip_class >= CIK)
605 radeon_set_uconfig_reg_idx(cs, R_030908_VGT_PRIMITIVE_TYPE, 1, prim);
606 else
607 radeon_set_config_reg(cs, R_008958_VGT_PRIMITIVE_TYPE, prim);
608
609 sctx->last_prim = prim;
610 }
611
612 if (gs_out_prim != sctx->last_gs_out_prim) {
613 radeon_set_context_reg(cs, R_028A6C_VGT_GS_OUT_PRIM_TYPE, gs_out_prim);
614 sctx->last_gs_out_prim = gs_out_prim;
615 }
616
617 /* Primitive restart. */
618 if (info->primitive_restart != sctx->last_primitive_restart_en) {
619 if (sctx->b.chip_class >= GFX9)
620 radeon_set_uconfig_reg(cs, R_03092C_VGT_MULTI_PRIM_IB_RESET_EN,
621 info->primitive_restart);
622 else
623 radeon_set_context_reg(cs, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN,
624 info->primitive_restart);
625
626 sctx->last_primitive_restart_en = info->primitive_restart;
627
628 }
629 if (info->primitive_restart &&
630 (info->restart_index != sctx->last_restart_index ||
631 sctx->last_restart_index == SI_RESTART_INDEX_UNKNOWN)) {
632 radeon_set_context_reg(cs, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
633 info->restart_index);
634 sctx->last_restart_index = info->restart_index;
635 }
636 }
637
638 static void si_emit_draw_packets(struct si_context *sctx,
639 const struct pipe_draw_info *info,
640 struct pipe_resource *indexbuf,
641 unsigned index_size,
642 unsigned index_offset)
643 {
644 struct pipe_draw_indirect_info *indirect = info->indirect;
645 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
646 unsigned sh_base_reg = sctx->shader_pointers.sh_base[PIPE_SHADER_VERTEX];
647 bool render_cond_bit = sctx->b.render_cond && !sctx->b.render_cond_force_off;
648 uint32_t index_max_size = 0;
649 uint64_t index_va = 0;
650
651 if (info->count_from_stream_output) {
652 struct si_streamout_target *t =
653 (struct si_streamout_target*)info->count_from_stream_output;
654 uint64_t va = t->buf_filled_size->gpu_address +
655 t->buf_filled_size_offset;
656
657 radeon_set_context_reg(cs, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE,
658 t->stride_in_dw);
659
660 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
661 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
662 COPY_DATA_DST_SEL(COPY_DATA_REG) |
663 COPY_DATA_WR_CONFIRM);
664 radeon_emit(cs, va); /* src address lo */
665 radeon_emit(cs, va >> 32); /* src address hi */
666 radeon_emit(cs, R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE >> 2);
667 radeon_emit(cs, 0); /* unused */
668
669 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
670 t->buf_filled_size, RADEON_USAGE_READ,
671 RADEON_PRIO_SO_FILLED_SIZE);
672 }
673
674 /* draw packet */
675 if (index_size) {
676 if (index_size != sctx->last_index_size) {
677 unsigned index_type;
678
679 /* index type */
680 switch (index_size) {
681 case 1:
682 index_type = V_028A7C_VGT_INDEX_8;
683 break;
684 case 2:
685 index_type = V_028A7C_VGT_INDEX_16 |
686 (SI_BIG_ENDIAN && sctx->b.chip_class <= CIK ?
687 V_028A7C_VGT_DMA_SWAP_16_BIT : 0);
688 break;
689 case 4:
690 index_type = V_028A7C_VGT_INDEX_32 |
691 (SI_BIG_ENDIAN && sctx->b.chip_class <= CIK ?
692 V_028A7C_VGT_DMA_SWAP_32_BIT : 0);
693 break;
694 default:
695 assert(!"unreachable");
696 return;
697 }
698
699 if (sctx->b.chip_class >= GFX9) {
700 radeon_set_uconfig_reg_idx(cs, R_03090C_VGT_INDEX_TYPE,
701 2, index_type);
702 } else {
703 radeon_emit(cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
704 radeon_emit(cs, index_type);
705 }
706
707 sctx->last_index_size = index_size;
708 }
709
710 index_max_size = (indexbuf->width0 - index_offset) /
711 index_size;
712 index_va = r600_resource(indexbuf)->gpu_address + index_offset;
713
714 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
715 (struct r600_resource *)indexbuf,
716 RADEON_USAGE_READ, RADEON_PRIO_INDEX_BUFFER);
717 } else {
718 /* On CI and later, non-indexed draws overwrite VGT_INDEX_TYPE,
719 * so the state must be re-emitted before the next indexed draw.
720 */
721 if (sctx->b.chip_class >= CIK)
722 sctx->last_index_size = -1;
723 }
724
725 if (indirect) {
726 uint64_t indirect_va = r600_resource(indirect->buffer)->gpu_address;
727
728 assert(indirect_va % 8 == 0);
729
730 si_invalidate_draw_sh_constants(sctx);
731
732 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
733 radeon_emit(cs, 1);
734 radeon_emit(cs, indirect_va);
735 radeon_emit(cs, indirect_va >> 32);
736
737 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
738 (struct r600_resource *)indirect->buffer,
739 RADEON_USAGE_READ, RADEON_PRIO_DRAW_INDIRECT);
740
741 unsigned di_src_sel = index_size ? V_0287F0_DI_SRC_SEL_DMA
742 : V_0287F0_DI_SRC_SEL_AUTO_INDEX;
743
744 assert(indirect->offset % 4 == 0);
745
746 if (index_size) {
747 radeon_emit(cs, PKT3(PKT3_INDEX_BASE, 1, 0));
748 radeon_emit(cs, index_va);
749 radeon_emit(cs, index_va >> 32);
750
751 radeon_emit(cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
752 radeon_emit(cs, index_max_size);
753 }
754
755 if (!sctx->screen->has_draw_indirect_multi) {
756 radeon_emit(cs, PKT3(index_size ? PKT3_DRAW_INDEX_INDIRECT
757 : PKT3_DRAW_INDIRECT,
758 3, render_cond_bit));
759 radeon_emit(cs, indirect->offset);
760 radeon_emit(cs, (sh_base_reg + SI_SGPR_BASE_VERTEX * 4 - SI_SH_REG_OFFSET) >> 2);
761 radeon_emit(cs, (sh_base_reg + SI_SGPR_START_INSTANCE * 4 - SI_SH_REG_OFFSET) >> 2);
762 radeon_emit(cs, di_src_sel);
763 } else {
764 uint64_t count_va = 0;
765
766 if (indirect->indirect_draw_count) {
767 struct r600_resource *params_buf =
768 (struct r600_resource *)indirect->indirect_draw_count;
769
770 radeon_add_to_buffer_list(
771 &sctx->b, &sctx->b.gfx, params_buf,
772 RADEON_USAGE_READ, RADEON_PRIO_DRAW_INDIRECT);
773
774 count_va = params_buf->gpu_address + indirect->indirect_draw_count_offset;
775 }
776
777 radeon_emit(cs, PKT3(index_size ? PKT3_DRAW_INDEX_INDIRECT_MULTI :
778 PKT3_DRAW_INDIRECT_MULTI,
779 8, render_cond_bit));
780 radeon_emit(cs, indirect->offset);
781 radeon_emit(cs, (sh_base_reg + SI_SGPR_BASE_VERTEX * 4 - SI_SH_REG_OFFSET) >> 2);
782 radeon_emit(cs, (sh_base_reg + SI_SGPR_START_INSTANCE * 4 - SI_SH_REG_OFFSET) >> 2);
783 radeon_emit(cs, ((sh_base_reg + SI_SGPR_DRAWID * 4 - SI_SH_REG_OFFSET) >> 2) |
784 S_2C3_DRAW_INDEX_ENABLE(1) |
785 S_2C3_COUNT_INDIRECT_ENABLE(!!indirect->indirect_draw_count));
786 radeon_emit(cs, indirect->draw_count);
787 radeon_emit(cs, count_va);
788 radeon_emit(cs, count_va >> 32);
789 radeon_emit(cs, indirect->stride);
790 radeon_emit(cs, di_src_sel);
791 }
792 } else {
793 int base_vertex;
794
795 radeon_emit(cs, PKT3(PKT3_NUM_INSTANCES, 0, 0));
796 radeon_emit(cs, info->instance_count);
797
798 /* Base vertex and start instance. */
799 base_vertex = index_size ? info->index_bias : info->start;
800
801 if (sctx->num_vs_blit_sgprs) {
802 /* Re-emit draw constants after we leave u_blitter. */
803 si_invalidate_draw_sh_constants(sctx);
804
805 /* Blit VS doesn't use BASE_VERTEX, START_INSTANCE, and DRAWID. */
806 radeon_set_sh_reg_seq(cs, sh_base_reg + SI_SGPR_VS_BLIT_DATA * 4,
807 sctx->num_vs_blit_sgprs);
808 radeon_emit_array(cs, sctx->vs_blit_sh_data,
809 sctx->num_vs_blit_sgprs);
810 } else if (base_vertex != sctx->last_base_vertex ||
811 sctx->last_base_vertex == SI_BASE_VERTEX_UNKNOWN ||
812 info->start_instance != sctx->last_start_instance ||
813 info->drawid != sctx->last_drawid ||
814 sh_base_reg != sctx->last_sh_base_reg) {
815 radeon_set_sh_reg_seq(cs, sh_base_reg + SI_SGPR_BASE_VERTEX * 4, 3);
816 radeon_emit(cs, base_vertex);
817 radeon_emit(cs, info->start_instance);
818 radeon_emit(cs, info->drawid);
819
820 sctx->last_base_vertex = base_vertex;
821 sctx->last_start_instance = info->start_instance;
822 sctx->last_drawid = info->drawid;
823 sctx->last_sh_base_reg = sh_base_reg;
824 }
825
826 if (index_size) {
827 index_va += info->start * index_size;
828
829 radeon_emit(cs, PKT3(PKT3_DRAW_INDEX_2, 4, render_cond_bit));
830 radeon_emit(cs, index_max_size);
831 radeon_emit(cs, index_va);
832 radeon_emit(cs, index_va >> 32);
833 radeon_emit(cs, info->count);
834 radeon_emit(cs, V_0287F0_DI_SRC_SEL_DMA);
835 } else {
836 radeon_emit(cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, render_cond_bit));
837 radeon_emit(cs, info->count);
838 radeon_emit(cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
839 S_0287F0_USE_OPAQUE(!!info->count_from_stream_output));
840 }
841 }
842 }
843
844 static void si_emit_surface_sync(struct r600_common_context *rctx,
845 unsigned cp_coher_cntl)
846 {
847 struct radeon_winsys_cs *cs = rctx->gfx.cs;
848
849 if (rctx->chip_class >= GFX9) {
850 /* Flush caches and wait for the caches to assert idle. */
851 radeon_emit(cs, PKT3(PKT3_ACQUIRE_MEM, 5, 0));
852 radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */
853 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
854 radeon_emit(cs, 0xffffff); /* CP_COHER_SIZE_HI */
855 radeon_emit(cs, 0); /* CP_COHER_BASE */
856 radeon_emit(cs, 0); /* CP_COHER_BASE_HI */
857 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
858 } else {
859 /* ACQUIRE_MEM is only required on a compute ring. */
860 radeon_emit(cs, PKT3(PKT3_SURFACE_SYNC, 3, 0));
861 radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */
862 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
863 radeon_emit(cs, 0); /* CP_COHER_BASE */
864 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
865 }
866 }
867
868 void si_emit_cache_flush(struct si_context *sctx)
869 {
870 struct r600_common_context *rctx = &sctx->b;
871 struct radeon_winsys_cs *cs = rctx->gfx.cs;
872 uint32_t cp_coher_cntl = 0;
873 uint32_t flush_cb_db = rctx->flags & (SI_CONTEXT_FLUSH_AND_INV_CB |
874 SI_CONTEXT_FLUSH_AND_INV_DB);
875
876 if (rctx->flags & SI_CONTEXT_FLUSH_AND_INV_CB)
877 sctx->b.num_cb_cache_flushes++;
878 if (rctx->flags & SI_CONTEXT_FLUSH_AND_INV_DB)
879 sctx->b.num_db_cache_flushes++;
880
881 /* SI has a bug that it always flushes ICACHE and KCACHE if either
882 * bit is set. An alternative way is to write SQC_CACHES, but that
883 * doesn't seem to work reliably. Since the bug doesn't affect
884 * correctness (it only does more work than necessary) and
885 * the performance impact is likely negligible, there is no plan
886 * to add a workaround for it.
887 */
888
889 if (rctx->flags & SI_CONTEXT_INV_ICACHE)
890 cp_coher_cntl |= S_0085F0_SH_ICACHE_ACTION_ENA(1);
891 if (rctx->flags & SI_CONTEXT_INV_SMEM_L1)
892 cp_coher_cntl |= S_0085F0_SH_KCACHE_ACTION_ENA(1);
893
894 if (rctx->chip_class <= VI) {
895 if (rctx->flags & SI_CONTEXT_FLUSH_AND_INV_CB) {
896 cp_coher_cntl |= S_0085F0_CB_ACTION_ENA(1) |
897 S_0085F0_CB0_DEST_BASE_ENA(1) |
898 S_0085F0_CB1_DEST_BASE_ENA(1) |
899 S_0085F0_CB2_DEST_BASE_ENA(1) |
900 S_0085F0_CB3_DEST_BASE_ENA(1) |
901 S_0085F0_CB4_DEST_BASE_ENA(1) |
902 S_0085F0_CB5_DEST_BASE_ENA(1) |
903 S_0085F0_CB6_DEST_BASE_ENA(1) |
904 S_0085F0_CB7_DEST_BASE_ENA(1);
905
906 /* Necessary for DCC */
907 if (rctx->chip_class == VI)
908 si_gfx_write_event_eop(rctx, V_028A90_FLUSH_AND_INV_CB_DATA_TS,
909 0, EOP_DATA_SEL_DISCARD, NULL,
910 0, 0, R600_NOT_QUERY);
911 }
912 if (rctx->flags & SI_CONTEXT_FLUSH_AND_INV_DB)
913 cp_coher_cntl |= S_0085F0_DB_ACTION_ENA(1) |
914 S_0085F0_DB_DEST_BASE_ENA(1);
915 }
916
917 if (rctx->flags & SI_CONTEXT_FLUSH_AND_INV_CB) {
918 /* Flush CMASK/FMASK/DCC. SURFACE_SYNC will wait for idle. */
919 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
920 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_META) | EVENT_INDEX(0));
921 }
922 if (rctx->flags & (SI_CONTEXT_FLUSH_AND_INV_DB |
923 SI_CONTEXT_FLUSH_AND_INV_DB_META)) {
924 /* Flush HTILE. SURFACE_SYNC will wait for idle. */
925 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
926 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_DB_META) | EVENT_INDEX(0));
927 }
928
929 /* Wait for shader engines to go idle.
930 * VS and PS waits are unnecessary if SURFACE_SYNC is going to wait
931 * for everything including CB/DB cache flushes.
932 */
933 if (!flush_cb_db) {
934 if (rctx->flags & SI_CONTEXT_PS_PARTIAL_FLUSH) {
935 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
936 radeon_emit(cs, EVENT_TYPE(V_028A90_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
937 /* Only count explicit shader flushes, not implicit ones
938 * done by SURFACE_SYNC.
939 */
940 rctx->num_vs_flushes++;
941 rctx->num_ps_flushes++;
942 } else if (rctx->flags & SI_CONTEXT_VS_PARTIAL_FLUSH) {
943 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
944 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
945 rctx->num_vs_flushes++;
946 }
947 }
948
949 if (rctx->flags & SI_CONTEXT_CS_PARTIAL_FLUSH &&
950 sctx->compute_is_busy) {
951 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
952 radeon_emit(cs, EVENT_TYPE(V_028A90_CS_PARTIAL_FLUSH | EVENT_INDEX(4)));
953 rctx->num_cs_flushes++;
954 sctx->compute_is_busy = false;
955 }
956
957 /* VGT state synchronization. */
958 if (rctx->flags & SI_CONTEXT_VGT_FLUSH) {
959 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
960 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
961 }
962 if (rctx->flags & SI_CONTEXT_VGT_STREAMOUT_SYNC) {
963 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
964 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_STREAMOUT_SYNC) | EVENT_INDEX(0));
965 }
966
967 /* GFX9: Wait for idle if we're flushing CB or DB. ACQUIRE_MEM doesn't
968 * wait for idle on GFX9. We have to use a TS event.
969 */
970 if (sctx->b.chip_class >= GFX9 && flush_cb_db) {
971 uint64_t va;
972 unsigned tc_flags, cb_db_event;
973
974 /* Set the CB/DB flush event. */
975 switch (flush_cb_db) {
976 case SI_CONTEXT_FLUSH_AND_INV_CB:
977 cb_db_event = V_028A90_FLUSH_AND_INV_CB_DATA_TS;
978 break;
979 case SI_CONTEXT_FLUSH_AND_INV_DB:
980 cb_db_event = V_028A90_FLUSH_AND_INV_DB_DATA_TS;
981 break;
982 default:
983 /* both CB & DB */
984 cb_db_event = V_028A90_CACHE_FLUSH_AND_INV_TS_EVENT;
985 }
986
987 /* These are the only allowed combinations. If you need to
988 * do multiple operations at once, do them separately.
989 * All operations that invalidate L2 also seem to invalidate
990 * metadata. Volatile (VOL) and WC flushes are not listed here.
991 *
992 * TC | TC_WB = writeback & invalidate L2 & L1
993 * TC | TC_WB | TC_NC = writeback & invalidate L2 for MTYPE == NC
994 * TC_WB | TC_NC = writeback L2 for MTYPE == NC
995 * TC | TC_NC = invalidate L2 for MTYPE == NC
996 * TC | TC_MD = writeback & invalidate L2 metadata (DCC, etc.)
997 * TCL1 = invalidate L1
998 */
999 tc_flags = 0;
1000
1001 if (rctx->flags & SI_CONTEXT_INV_L2_METADATA) {
1002 tc_flags = EVENT_TC_ACTION_ENA |
1003 EVENT_TC_MD_ACTION_ENA;
1004 }
1005
1006 /* Ideally flush TC together with CB/DB. */
1007 if (rctx->flags & SI_CONTEXT_INV_GLOBAL_L2) {
1008 /* Writeback and invalidate everything in L2 & L1. */
1009 tc_flags = EVENT_TC_ACTION_ENA |
1010 EVENT_TC_WB_ACTION_ENA;
1011
1012 /* Clear the flags. */
1013 rctx->flags &= ~(SI_CONTEXT_INV_GLOBAL_L2 |
1014 SI_CONTEXT_WRITEBACK_GLOBAL_L2 |
1015 SI_CONTEXT_INV_VMEM_L1);
1016 sctx->b.num_L2_invalidates++;
1017 }
1018
1019 /* Do the flush (enqueue the event and wait for it). */
1020 va = sctx->wait_mem_scratch->gpu_address;
1021 sctx->wait_mem_number++;
1022
1023 si_gfx_write_event_eop(rctx, cb_db_event, tc_flags,
1024 EOP_DATA_SEL_VALUE_32BIT,
1025 sctx->wait_mem_scratch, va,
1026 sctx->wait_mem_number, R600_NOT_QUERY);
1027 si_gfx_wait_fence(rctx, va, sctx->wait_mem_number, 0xffffffff);
1028 }
1029
1030 /* Make sure ME is idle (it executes most packets) before continuing.
1031 * This prevents read-after-write hazards between PFP and ME.
1032 */
1033 if (cp_coher_cntl ||
1034 (rctx->flags & (SI_CONTEXT_CS_PARTIAL_FLUSH |
1035 SI_CONTEXT_INV_VMEM_L1 |
1036 SI_CONTEXT_INV_GLOBAL_L2 |
1037 SI_CONTEXT_WRITEBACK_GLOBAL_L2))) {
1038 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1039 radeon_emit(cs, 0);
1040 }
1041
1042 /* SI-CI-VI only:
1043 * When one of the CP_COHER_CNTL.DEST_BASE flags is set, SURFACE_SYNC
1044 * waits for idle, so it should be last. SURFACE_SYNC is done in PFP.
1045 *
1046 * cp_coher_cntl should contain all necessary flags except TC flags
1047 * at this point.
1048 *
1049 * SI-CIK don't support L2 write-back.
1050 */
1051 if (rctx->flags & SI_CONTEXT_INV_GLOBAL_L2 ||
1052 (rctx->chip_class <= CIK &&
1053 (rctx->flags & SI_CONTEXT_WRITEBACK_GLOBAL_L2))) {
1054 /* Invalidate L1 & L2. (L1 is always invalidated on SI)
1055 * WB must be set on VI+ when TC_ACTION is set.
1056 */
1057 si_emit_surface_sync(rctx, cp_coher_cntl |
1058 S_0085F0_TC_ACTION_ENA(1) |
1059 S_0085F0_TCL1_ACTION_ENA(1) |
1060 S_0301F0_TC_WB_ACTION_ENA(rctx->chip_class >= VI));
1061 cp_coher_cntl = 0;
1062 sctx->b.num_L2_invalidates++;
1063 } else {
1064 /* L1 invalidation and L2 writeback must be done separately,
1065 * because both operations can't be done together.
1066 */
1067 if (rctx->flags & SI_CONTEXT_WRITEBACK_GLOBAL_L2) {
1068 /* WB = write-back
1069 * NC = apply to non-coherent MTYPEs
1070 * (i.e. MTYPE <= 1, which is what we use everywhere)
1071 *
1072 * WB doesn't work without NC.
1073 */
1074 si_emit_surface_sync(rctx, cp_coher_cntl |
1075 S_0301F0_TC_WB_ACTION_ENA(1) |
1076 S_0301F0_TC_NC_ACTION_ENA(1));
1077 cp_coher_cntl = 0;
1078 sctx->b.num_L2_writebacks++;
1079 }
1080 if (rctx->flags & SI_CONTEXT_INV_VMEM_L1) {
1081 /* Invalidate per-CU VMEM L1. */
1082 si_emit_surface_sync(rctx, cp_coher_cntl |
1083 S_0085F0_TCL1_ACTION_ENA(1));
1084 cp_coher_cntl = 0;
1085 }
1086 }
1087
1088 /* If TC flushes haven't cleared this... */
1089 if (cp_coher_cntl)
1090 si_emit_surface_sync(rctx, cp_coher_cntl);
1091
1092 if (rctx->flags & R600_CONTEXT_START_PIPELINE_STATS) {
1093 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1094 radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_START) |
1095 EVENT_INDEX(0));
1096 } else if (rctx->flags & R600_CONTEXT_STOP_PIPELINE_STATS) {
1097 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1098 radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_STOP) |
1099 EVENT_INDEX(0));
1100 }
1101
1102 rctx->flags = 0;
1103 }
1104
1105 static void si_get_draw_start_count(struct si_context *sctx,
1106 const struct pipe_draw_info *info,
1107 unsigned *start, unsigned *count)
1108 {
1109 struct pipe_draw_indirect_info *indirect = info->indirect;
1110
1111 if (indirect) {
1112 unsigned indirect_count;
1113 struct pipe_transfer *transfer;
1114 unsigned begin, end;
1115 unsigned map_size;
1116 unsigned *data;
1117
1118 if (indirect->indirect_draw_count) {
1119 data = pipe_buffer_map_range(&sctx->b.b,
1120 indirect->indirect_draw_count,
1121 indirect->indirect_draw_count_offset,
1122 sizeof(unsigned),
1123 PIPE_TRANSFER_READ, &transfer);
1124
1125 indirect_count = *data;
1126
1127 pipe_buffer_unmap(&sctx->b.b, transfer);
1128 } else {
1129 indirect_count = indirect->draw_count;
1130 }
1131
1132 if (!indirect_count) {
1133 *start = *count = 0;
1134 return;
1135 }
1136
1137 map_size = (indirect_count - 1) * indirect->stride + 3 * sizeof(unsigned);
1138 data = pipe_buffer_map_range(&sctx->b.b, indirect->buffer,
1139 indirect->offset, map_size,
1140 PIPE_TRANSFER_READ, &transfer);
1141
1142 begin = UINT_MAX;
1143 end = 0;
1144
1145 for (unsigned i = 0; i < indirect_count; ++i) {
1146 unsigned count = data[0];
1147 unsigned start = data[2];
1148
1149 if (count > 0) {
1150 begin = MIN2(begin, start);
1151 end = MAX2(end, start + count);
1152 }
1153
1154 data += indirect->stride / sizeof(unsigned);
1155 }
1156
1157 pipe_buffer_unmap(&sctx->b.b, transfer);
1158
1159 if (begin < end) {
1160 *start = begin;
1161 *count = end - begin;
1162 } else {
1163 *start = *count = 0;
1164 }
1165 } else {
1166 *start = info->start;
1167 *count = info->count;
1168 }
1169 }
1170
1171 static void si_emit_all_states(struct si_context *sctx, const struct pipe_draw_info *info,
1172 unsigned skip_atom_mask)
1173 {
1174 /* Emit state atoms. */
1175 unsigned mask = sctx->dirty_atoms & ~skip_atom_mask;
1176 while (mask) {
1177 struct r600_atom *atom = sctx->atoms.array[u_bit_scan(&mask)];
1178
1179 atom->emit(&sctx->b, atom);
1180 }
1181 sctx->dirty_atoms &= skip_atom_mask;
1182
1183 /* Emit states. */
1184 mask = sctx->dirty_states;
1185 while (mask) {
1186 unsigned i = u_bit_scan(&mask);
1187 struct si_pm4_state *state = sctx->queued.array[i];
1188
1189 if (!state || sctx->emitted.array[i] == state)
1190 continue;
1191
1192 si_pm4_emit(sctx, state);
1193 sctx->emitted.array[i] = state;
1194 }
1195 sctx->dirty_states = 0;
1196
1197 /* Emit draw states. */
1198 unsigned num_patches = 0;
1199
1200 si_emit_rasterizer_prim_state(sctx);
1201 if (sctx->tes_shader.cso)
1202 si_emit_derived_tess_state(sctx, info, &num_patches);
1203 si_emit_vs_state(sctx, info);
1204 si_emit_draw_registers(sctx, info, num_patches);
1205 }
1206
1207 void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info)
1208 {
1209 struct si_context *sctx = (struct si_context *)ctx;
1210 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
1211 struct pipe_resource *indexbuf = info->index.resource;
1212 unsigned dirty_tex_counter;
1213 enum pipe_prim_type rast_prim;
1214 unsigned index_size = info->index_size;
1215 unsigned index_offset = info->indirect ? info->start * index_size : 0;
1216
1217 if (likely(!info->indirect)) {
1218 /* SI-CI treat instance_count==0 as instance_count==1. There is
1219 * no workaround for indirect draws, but we can at least skip
1220 * direct draws.
1221 */
1222 if (unlikely(!info->instance_count))
1223 return;
1224
1225 /* Handle count == 0. */
1226 if (unlikely(!info->count &&
1227 (index_size || !info->count_from_stream_output)))
1228 return;
1229 }
1230
1231 if (unlikely(!sctx->vs_shader.cso)) {
1232 assert(0);
1233 return;
1234 }
1235 if (unlikely(!sctx->ps_shader.cso && (!rs || !rs->rasterizer_discard))) {
1236 assert(0);
1237 return;
1238 }
1239 if (unlikely(!!sctx->tes_shader.cso != (info->mode == PIPE_PRIM_PATCHES))) {
1240 assert(0);
1241 return;
1242 }
1243
1244 /* Recompute and re-emit the texture resource states if needed. */
1245 dirty_tex_counter = p_atomic_read(&sctx->b.screen->dirty_tex_counter);
1246 if (unlikely(dirty_tex_counter != sctx->b.last_dirty_tex_counter)) {
1247 sctx->b.last_dirty_tex_counter = dirty_tex_counter;
1248 sctx->framebuffer.dirty_cbufs |=
1249 ((1 << sctx->framebuffer.state.nr_cbufs) - 1);
1250 sctx->framebuffer.dirty_zsbuf = true;
1251 si_mark_atom_dirty(sctx, &sctx->framebuffer.atom);
1252 si_update_all_texture_descriptors(sctx);
1253 }
1254
1255 si_decompress_textures(sctx, u_bit_consecutive(0, SI_NUM_GRAPHICS_SHADERS));
1256
1257 /* Set the rasterization primitive type.
1258 *
1259 * This must be done after si_decompress_textures, which can call
1260 * draw_vbo recursively, and before si_update_shaders, which uses
1261 * current_rast_prim for this draw_vbo call. */
1262 if (sctx->gs_shader.cso)
1263 rast_prim = sctx->gs_shader.cso->gs_output_prim;
1264 else if (sctx->tes_shader.cso) {
1265 if (sctx->tes_shader.cso->info.properties[TGSI_PROPERTY_TES_POINT_MODE])
1266 rast_prim = PIPE_PRIM_POINTS;
1267 else
1268 rast_prim = sctx->tes_shader.cso->info.properties[TGSI_PROPERTY_TES_PRIM_MODE];
1269 } else
1270 rast_prim = info->mode;
1271
1272 if (rast_prim != sctx->current_rast_prim) {
1273 bool old_is_poly = sctx->current_rast_prim >= PIPE_PRIM_TRIANGLES;
1274 bool new_is_poly = rast_prim >= PIPE_PRIM_TRIANGLES;
1275 if (old_is_poly != new_is_poly) {
1276 sctx->scissors.dirty_mask = (1 << SI_MAX_VIEWPORTS) - 1;
1277 si_mark_atom_dirty(sctx, &sctx->scissors.atom);
1278 }
1279
1280 sctx->current_rast_prim = rast_prim;
1281 sctx->do_update_shaders = true;
1282 }
1283
1284 if (sctx->tes_shader.cso &&
1285 (sctx->b.family == CHIP_VEGA10 || sctx->b.family == CHIP_RAVEN)) {
1286 /* Determine whether the LS VGPR fix should be applied.
1287 *
1288 * It is only required when num input CPs > num output CPs,
1289 * which cannot happen with the fixed function TCS. We should
1290 * also update this bit when switching from TCS to fixed
1291 * function TCS.
1292 */
1293 struct si_shader_selector *tcs = sctx->tcs_shader.cso;
1294 bool ls_vgpr_fix =
1295 tcs &&
1296 info->vertices_per_patch >
1297 tcs->info.properties[TGSI_PROPERTY_TCS_VERTICES_OUT];
1298
1299 if (ls_vgpr_fix != sctx->ls_vgpr_fix) {
1300 sctx->ls_vgpr_fix = ls_vgpr_fix;
1301 sctx->do_update_shaders = true;
1302 }
1303 }
1304
1305 if (sctx->gs_shader.cso) {
1306 /* Determine whether the GS triangle strip adjacency fix should
1307 * be applied. Rotate every other triangle if
1308 * - triangle strips with adjacency are fed to the GS and
1309 * - primitive restart is disabled (the rotation doesn't help
1310 * when the restart occurs after an odd number of triangles).
1311 */
1312 bool gs_tri_strip_adj_fix =
1313 !sctx->tes_shader.cso &&
1314 info->mode == PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY &&
1315 !info->primitive_restart;
1316
1317 if (gs_tri_strip_adj_fix != sctx->gs_tri_strip_adj_fix) {
1318 sctx->gs_tri_strip_adj_fix = gs_tri_strip_adj_fix;
1319 sctx->do_update_shaders = true;
1320 }
1321 }
1322
1323 if (sctx->do_update_shaders && !si_update_shaders(sctx))
1324 return;
1325
1326 if (index_size) {
1327 /* Translate or upload, if needed. */
1328 /* 8-bit indices are supported on VI. */
1329 if (sctx->b.chip_class <= CIK && index_size == 1) {
1330 unsigned start, count, start_offset, size, offset;
1331 void *ptr;
1332
1333 si_get_draw_start_count(sctx, info, &start, &count);
1334 start_offset = start * 2;
1335 size = count * 2;
1336
1337 indexbuf = NULL;
1338 u_upload_alloc(ctx->stream_uploader, start_offset,
1339 size,
1340 si_optimal_tcc_alignment(sctx, size),
1341 &offset, &indexbuf, &ptr);
1342 if (!indexbuf)
1343 return;
1344
1345 util_shorten_ubyte_elts_to_userptr(&sctx->b.b, info, 0, 0,
1346 index_offset + start,
1347 count, ptr);
1348
1349 /* info->start will be added by the drawing code */
1350 index_offset = offset - start_offset;
1351 index_size = 2;
1352 } else if (info->has_user_indices) {
1353 unsigned start_offset;
1354
1355 assert(!info->indirect);
1356 start_offset = info->start * index_size;
1357
1358 indexbuf = NULL;
1359 u_upload_data(ctx->stream_uploader, start_offset,
1360 info->count * index_size,
1361 sctx->screen->b.info.tcc_cache_line_size,
1362 (char*)info->index.user + start_offset,
1363 &index_offset, &indexbuf);
1364 if (!indexbuf)
1365 return;
1366
1367 /* info->start will be added by the drawing code */
1368 index_offset -= start_offset;
1369 } else if (sctx->b.chip_class <= CIK &&
1370 r600_resource(indexbuf)->TC_L2_dirty) {
1371 /* VI reads index buffers through TC L2, so it doesn't
1372 * need this. */
1373 sctx->b.flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
1374 r600_resource(indexbuf)->TC_L2_dirty = false;
1375 }
1376 }
1377
1378 if (info->indirect) {
1379 struct pipe_draw_indirect_info *indirect = info->indirect;
1380
1381 /* Add the buffer size for memory checking in need_cs_space. */
1382 r600_context_add_resource_size(ctx, indirect->buffer);
1383
1384 /* Indirect buffers use TC L2 on GFX9, but not older hw. */
1385 if (sctx->b.chip_class <= VI) {
1386 if (r600_resource(indirect->buffer)->TC_L2_dirty) {
1387 sctx->b.flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
1388 r600_resource(indirect->buffer)->TC_L2_dirty = false;
1389 }
1390
1391 if (indirect->indirect_draw_count &&
1392 r600_resource(indirect->indirect_draw_count)->TC_L2_dirty) {
1393 sctx->b.flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
1394 r600_resource(indirect->indirect_draw_count)->TC_L2_dirty = false;
1395 }
1396 }
1397 }
1398
1399 si_need_cs_space(sctx);
1400
1401 /* Since we've called r600_context_add_resource_size for vertex buffers,
1402 * this must be called after si_need_cs_space, because we must let
1403 * need_cs_space flush before we add buffers to the buffer list.
1404 */
1405 if (!si_upload_vertex_buffer_descriptors(sctx))
1406 return;
1407
1408 /* Vega10/Raven scissor bug workaround. This must be done before VPORT
1409 * scissor registers are changed. There is also a more efficient but
1410 * more involved alternative workaround.
1411 */
1412 if ((sctx->b.family == CHIP_VEGA10 || sctx->b.family == CHIP_RAVEN) &&
1413 si_is_atom_dirty(sctx, &sctx->scissors.atom)) {
1414 sctx->b.flags |= SI_CONTEXT_PS_PARTIAL_FLUSH;
1415 si_emit_cache_flush(sctx);
1416 }
1417
1418 /* Use optimal packet order based on whether we need to sync the pipeline. */
1419 if (unlikely(sctx->b.flags & (SI_CONTEXT_FLUSH_AND_INV_CB |
1420 SI_CONTEXT_FLUSH_AND_INV_DB |
1421 SI_CONTEXT_PS_PARTIAL_FLUSH |
1422 SI_CONTEXT_CS_PARTIAL_FLUSH))) {
1423 /* If we have to wait for idle, set all states first, so that all
1424 * SET packets are processed in parallel with previous draw calls.
1425 * Then upload descriptors, set shader pointers, and draw, and
1426 * prefetch at the end. This ensures that the time the CUs
1427 * are idle is very short. (there are only SET_SH packets between
1428 * the wait and the draw)
1429 */
1430 struct r600_atom *shader_pointers = &sctx->shader_pointers.atom;
1431 unsigned masked_atoms = 1u << shader_pointers->id;
1432
1433 if (unlikely(sctx->b.flags & R600_CONTEXT_FLUSH_FOR_RENDER_COND))
1434 masked_atoms |= 1u << sctx->b.render_cond_atom.id;
1435
1436 /* Emit all states except shader pointers and render condition. */
1437 si_emit_all_states(sctx, info, masked_atoms);
1438 si_emit_cache_flush(sctx);
1439
1440 /* <-- CUs are idle here. */
1441 if (!si_upload_graphics_shader_descriptors(sctx))
1442 return;
1443
1444 /* Set shader pointers after descriptors are uploaded. */
1445 if (si_is_atom_dirty(sctx, shader_pointers))
1446 shader_pointers->emit(&sctx->b, NULL);
1447 if (si_is_atom_dirty(sctx, &sctx->b.render_cond_atom))
1448 sctx->b.render_cond_atom.emit(&sctx->b, NULL);
1449 sctx->dirty_atoms = 0;
1450
1451 si_emit_draw_packets(sctx, info, indexbuf, index_size, index_offset);
1452 /* <-- CUs are busy here. */
1453
1454 /* Start prefetches after the draw has been started. Both will run
1455 * in parallel, but starting the draw first is more important.
1456 */
1457 if (sctx->b.chip_class >= CIK && sctx->prefetch_L2_mask)
1458 cik_emit_prefetch_L2(sctx);
1459 } else {
1460 /* If we don't wait for idle, start prefetches first, then set
1461 * states, and draw at the end.
1462 */
1463 if (sctx->b.flags)
1464 si_emit_cache_flush(sctx);
1465
1466 if (sctx->b.chip_class >= CIK && sctx->prefetch_L2_mask)
1467 cik_emit_prefetch_L2(sctx);
1468
1469 if (!si_upload_graphics_shader_descriptors(sctx))
1470 return;
1471
1472 si_emit_all_states(sctx, info, 0);
1473 si_emit_draw_packets(sctx, info, indexbuf, index_size, index_offset);
1474 }
1475
1476 if (unlikely(sctx->current_saved_cs)) {
1477 si_trace_emit(sctx);
1478 si_log_draw_state(sctx, sctx->b.log);
1479 }
1480
1481 /* Workaround for a VGT hang when streamout is enabled.
1482 * It must be done after drawing. */
1483 if ((sctx->b.family == CHIP_HAWAII ||
1484 sctx->b.family == CHIP_TONGA ||
1485 sctx->b.family == CHIP_FIJI) &&
1486 si_get_strmout_en(sctx)) {
1487 sctx->b.flags |= SI_CONTEXT_VGT_STREAMOUT_SYNC;
1488 }
1489
1490 if (unlikely(sctx->decompression_enabled)) {
1491 sctx->b.num_decompress_calls++;
1492 } else {
1493 sctx->b.num_draw_calls++;
1494 if (sctx->framebuffer.state.nr_cbufs > 1)
1495 sctx->b.num_mrt_draw_calls++;
1496 if (info->primitive_restart)
1497 sctx->b.num_prim_restart_calls++;
1498 if (G_0286E8_WAVESIZE(sctx->spi_tmpring_size))
1499 sctx->b.num_spill_draw_calls++;
1500 }
1501 if (index_size && indexbuf != info->index.resource)
1502 pipe_resource_reference(&indexbuf, NULL);
1503 }
1504
1505 void si_draw_rectangle(struct blitter_context *blitter,
1506 void *vertex_elements_cso,
1507 blitter_get_vs_func get_vs,
1508 int x1, int y1, int x2, int y2,
1509 float depth, unsigned num_instances,
1510 enum blitter_attrib_type type,
1511 const union blitter_attrib *attrib)
1512 {
1513 struct pipe_context *pipe = util_blitter_get_pipe(blitter);
1514 struct si_context *sctx = (struct si_context*)pipe;
1515
1516 /* Pack position coordinates as signed int16. */
1517 sctx->vs_blit_sh_data[0] = (uint32_t)(x1 & 0xffff) |
1518 ((uint32_t)(y1 & 0xffff) << 16);
1519 sctx->vs_blit_sh_data[1] = (uint32_t)(x2 & 0xffff) |
1520 ((uint32_t)(y2 & 0xffff) << 16);
1521 sctx->vs_blit_sh_data[2] = fui(depth);
1522
1523 switch (type) {
1524 case UTIL_BLITTER_ATTRIB_COLOR:
1525 memcpy(&sctx->vs_blit_sh_data[3], attrib->color,
1526 sizeof(float)*4);
1527 break;
1528 case UTIL_BLITTER_ATTRIB_TEXCOORD_XY:
1529 case UTIL_BLITTER_ATTRIB_TEXCOORD_XYZW:
1530 memcpy(&sctx->vs_blit_sh_data[3], &attrib->texcoord,
1531 sizeof(attrib->texcoord));
1532 break;
1533 case UTIL_BLITTER_ATTRIB_NONE:;
1534 }
1535
1536 pipe->bind_vs_state(pipe, si_get_blit_vs(sctx, type, num_instances));
1537
1538 struct pipe_draw_info info = {};
1539 info.mode = R600_PRIM_RECTANGLE_LIST;
1540 info.count = 3;
1541 info.instance_count = num_instances;
1542
1543 /* Don't set per-stage shader pointers for VS. */
1544 sctx->shader_pointers_dirty &= ~SI_DESCS_SHADER_MASK(VERTEX);
1545 sctx->vertex_buffer_pointer_dirty = false;
1546
1547 si_draw_vbo(pipe, &info);
1548 }
1549
1550 void si_trace_emit(struct si_context *sctx)
1551 {
1552 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
1553 uint64_t va = sctx->current_saved_cs->trace_buf->gpu_address;
1554 uint32_t trace_id = ++sctx->current_saved_cs->trace_id;
1555
1556 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
1557 radeon_emit(cs, S_370_DST_SEL(V_370_MEMORY_SYNC) |
1558 S_370_WR_CONFIRM(1) |
1559 S_370_ENGINE_SEL(V_370_ME));
1560 radeon_emit(cs, va);
1561 radeon_emit(cs, va >> 32);
1562 radeon_emit(cs, trace_id);
1563 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1564 radeon_emit(cs, AC_ENCODE_TRACE_POINT(trace_id));
1565
1566 if (sctx->b.log)
1567 u_log_flush(sctx->b.log);
1568 }