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radeonsi: fix missing include for Elements.
[mesa.git] / src / gallium / drivers / radeonsi / si_state_draw.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Christian König <christian.koenig@amd.com>
25 */
26
27 #include "si_pipe.h"
28 #include "si_shader.h"
29 #include "radeon/r600_cs.h"
30 #include "sid.h"
31
32 #include "util/u_index_modify.h"
33 #include "util/u_upload_mgr.h"
34 #include "util/u_prim.h"
35 #include "util/u_memory.h"
36
37 static unsigned si_conv_pipe_prim(unsigned mode)
38 {
39 static const unsigned prim_conv[] = {
40 [PIPE_PRIM_POINTS] = V_008958_DI_PT_POINTLIST,
41 [PIPE_PRIM_LINES] = V_008958_DI_PT_LINELIST,
42 [PIPE_PRIM_LINE_LOOP] = V_008958_DI_PT_LINELOOP,
43 [PIPE_PRIM_LINE_STRIP] = V_008958_DI_PT_LINESTRIP,
44 [PIPE_PRIM_TRIANGLES] = V_008958_DI_PT_TRILIST,
45 [PIPE_PRIM_TRIANGLE_STRIP] = V_008958_DI_PT_TRISTRIP,
46 [PIPE_PRIM_TRIANGLE_FAN] = V_008958_DI_PT_TRIFAN,
47 [PIPE_PRIM_QUADS] = V_008958_DI_PT_QUADLIST,
48 [PIPE_PRIM_QUAD_STRIP] = V_008958_DI_PT_QUADSTRIP,
49 [PIPE_PRIM_POLYGON] = V_008958_DI_PT_POLYGON,
50 [PIPE_PRIM_LINES_ADJACENCY] = V_008958_DI_PT_LINELIST_ADJ,
51 [PIPE_PRIM_LINE_STRIP_ADJACENCY] = V_008958_DI_PT_LINESTRIP_ADJ,
52 [PIPE_PRIM_TRIANGLES_ADJACENCY] = V_008958_DI_PT_TRILIST_ADJ,
53 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY] = V_008958_DI_PT_TRISTRIP_ADJ,
54 [PIPE_PRIM_PATCHES] = V_008958_DI_PT_PATCH,
55 [R600_PRIM_RECTANGLE_LIST] = V_008958_DI_PT_RECTLIST
56 };
57 assert(mode < Elements(prim_conv));
58 return prim_conv[mode];
59 }
60
61 static unsigned si_conv_prim_to_gs_out(unsigned mode)
62 {
63 static const int prim_conv[] = {
64 [PIPE_PRIM_POINTS] = V_028A6C_OUTPRIM_TYPE_POINTLIST,
65 [PIPE_PRIM_LINES] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
66 [PIPE_PRIM_LINE_LOOP] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
67 [PIPE_PRIM_LINE_STRIP] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
68 [PIPE_PRIM_TRIANGLES] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
69 [PIPE_PRIM_TRIANGLE_STRIP] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
70 [PIPE_PRIM_TRIANGLE_FAN] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
71 [PIPE_PRIM_QUADS] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
72 [PIPE_PRIM_QUAD_STRIP] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
73 [PIPE_PRIM_POLYGON] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
74 [PIPE_PRIM_LINES_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
75 [PIPE_PRIM_LINE_STRIP_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
76 [PIPE_PRIM_TRIANGLES_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
77 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
78 [PIPE_PRIM_PATCHES] = V_028A6C_OUTPRIM_TYPE_POINTLIST,
79 [R600_PRIM_RECTANGLE_LIST] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
80 };
81 assert(mode < Elements(prim_conv));
82
83 return prim_conv[mode];
84 }
85
86 /**
87 * This calculates the LDS size for tessellation shaders (VS, TCS, TES).
88 * LS.LDS_SIZE is shared by all 3 shader stages.
89 *
90 * The information about LDS and other non-compile-time parameters is then
91 * written to userdata SGPRs.
92 */
93 static void si_emit_derived_tess_state(struct si_context *sctx,
94 const struct pipe_draw_info *info,
95 unsigned *num_patches)
96 {
97 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
98 struct si_shader_ctx_state *ls = &sctx->vs_shader;
99 /* The TES pointer will only be used for sctx->last_tcs.
100 * It would be wrong to think that TCS = TES. */
101 struct si_shader_selector *tcs =
102 sctx->tcs_shader.cso ? sctx->tcs_shader.cso : sctx->tes_shader.cso;
103 unsigned tes_sh_base = sctx->shader_userdata.sh_base[PIPE_SHADER_TESS_EVAL];
104 unsigned num_tcs_input_cp = info->vertices_per_patch;
105 unsigned num_tcs_output_cp, num_tcs_inputs, num_tcs_outputs;
106 unsigned num_tcs_patch_outputs;
107 unsigned input_vertex_size, output_vertex_size, pervertex_output_patch_size;
108 unsigned input_patch_size, output_patch_size, output_patch0_offset;
109 unsigned perpatch_output_offset, lds_size, ls_rsrc2;
110 unsigned tcs_in_layout, tcs_out_layout, tcs_out_offsets;
111
112 *num_patches = 1; /* TODO: calculate this */
113
114 if (sctx->last_ls == ls->current &&
115 sctx->last_tcs == tcs &&
116 sctx->last_tes_sh_base == tes_sh_base &&
117 sctx->last_num_tcs_input_cp == num_tcs_input_cp)
118 return;
119
120 sctx->last_ls = ls->current;
121 sctx->last_tcs = tcs;
122 sctx->last_tes_sh_base = tes_sh_base;
123 sctx->last_num_tcs_input_cp = num_tcs_input_cp;
124
125 /* This calculates how shader inputs and outputs among VS, TCS, and TES
126 * are laid out in LDS. */
127 num_tcs_inputs = util_last_bit64(ls->cso->outputs_written);
128
129 if (sctx->tcs_shader.cso) {
130 num_tcs_outputs = util_last_bit64(tcs->outputs_written);
131 num_tcs_output_cp = tcs->info.properties[TGSI_PROPERTY_TCS_VERTICES_OUT];
132 num_tcs_patch_outputs = util_last_bit64(tcs->patch_outputs_written);
133 } else {
134 /* No TCS. Route varyings from LS to TES. */
135 num_tcs_outputs = num_tcs_inputs;
136 num_tcs_output_cp = num_tcs_input_cp;
137 num_tcs_patch_outputs = 2; /* TESSINNER + TESSOUTER */
138 }
139
140 input_vertex_size = num_tcs_inputs * 16;
141 output_vertex_size = num_tcs_outputs * 16;
142
143 input_patch_size = num_tcs_input_cp * input_vertex_size;
144
145 pervertex_output_patch_size = num_tcs_output_cp * output_vertex_size;
146 output_patch_size = pervertex_output_patch_size + num_tcs_patch_outputs * 16;
147
148 output_patch0_offset = sctx->tcs_shader.cso ? input_patch_size * *num_patches : 0;
149 perpatch_output_offset = output_patch0_offset + pervertex_output_patch_size;
150
151 lds_size = output_patch0_offset + output_patch_size * *num_patches;
152 ls_rsrc2 = ls->current->config.rsrc2;
153
154 if (sctx->b.chip_class >= CIK) {
155 assert(lds_size <= 65536);
156 ls_rsrc2 |= S_00B52C_LDS_SIZE(align(lds_size, 512) / 512);
157 } else {
158 assert(lds_size <= 32768);
159 ls_rsrc2 |= S_00B52C_LDS_SIZE(align(lds_size, 256) / 256);
160 }
161
162 /* Due to a hw bug, RSRC2_LS must be written twice with another
163 * LS register written in between. */
164 if (sctx->b.chip_class == CIK && sctx->b.family != CHIP_HAWAII)
165 radeon_set_sh_reg(cs, R_00B52C_SPI_SHADER_PGM_RSRC2_LS, ls_rsrc2);
166 radeon_set_sh_reg_seq(cs, R_00B528_SPI_SHADER_PGM_RSRC1_LS, 2);
167 radeon_emit(cs, ls->current->config.rsrc1);
168 radeon_emit(cs, ls_rsrc2);
169
170 /* Compute userdata SGPRs. */
171 assert(((input_vertex_size / 4) & ~0xff) == 0);
172 assert(((output_vertex_size / 4) & ~0xff) == 0);
173 assert(((input_patch_size / 4) & ~0x1fff) == 0);
174 assert(((output_patch_size / 4) & ~0x1fff) == 0);
175 assert(((output_patch0_offset / 16) & ~0xffff) == 0);
176 assert(((perpatch_output_offset / 16) & ~0xffff) == 0);
177 assert(num_tcs_input_cp <= 32);
178 assert(num_tcs_output_cp <= 32);
179
180 tcs_in_layout = (input_patch_size / 4) |
181 ((input_vertex_size / 4) << 13);
182 tcs_out_layout = (output_patch_size / 4) |
183 ((output_vertex_size / 4) << 13);
184 tcs_out_offsets = (output_patch0_offset / 16) |
185 ((perpatch_output_offset / 16) << 16);
186
187 /* Set them for LS. */
188 radeon_set_sh_reg(cs,
189 R_00B530_SPI_SHADER_USER_DATA_LS_0 + SI_SGPR_LS_OUT_LAYOUT * 4,
190 tcs_in_layout);
191
192 /* Set them for TCS. */
193 radeon_set_sh_reg_seq(cs,
194 R_00B430_SPI_SHADER_USER_DATA_HS_0 + SI_SGPR_TCS_OUT_OFFSETS * 4, 3);
195 radeon_emit(cs, tcs_out_offsets);
196 radeon_emit(cs, tcs_out_layout | (num_tcs_input_cp << 26));
197 radeon_emit(cs, tcs_in_layout);
198
199 /* Set them for TES. */
200 radeon_set_sh_reg_seq(cs, tes_sh_base + SI_SGPR_TCS_OUT_OFFSETS * 4, 2);
201 radeon_emit(cs, tcs_out_offsets);
202 radeon_emit(cs, tcs_out_layout | (num_tcs_output_cp << 26));
203 }
204
205 static unsigned si_num_prims_for_vertices(const struct pipe_draw_info *info)
206 {
207 switch (info->mode) {
208 case PIPE_PRIM_PATCHES:
209 return info->count / info->vertices_per_patch;
210 case R600_PRIM_RECTANGLE_LIST:
211 return info->count / 3;
212 default:
213 return u_prims_for_vertices(info->mode, info->count);
214 }
215 }
216
217 static unsigned si_get_ia_multi_vgt_param(struct si_context *sctx,
218 const struct pipe_draw_info *info,
219 unsigned num_patches)
220 {
221 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
222 unsigned prim = info->mode;
223 unsigned primgroup_size = 128; /* recommended without a GS */
224 unsigned max_primgroup_in_wave = 2;
225
226 /* SWITCH_ON_EOP(0) is always preferable. */
227 bool wd_switch_on_eop = false;
228 bool ia_switch_on_eop = false;
229 bool ia_switch_on_eoi = false;
230 bool partial_vs_wave = false;
231 bool partial_es_wave = false;
232
233 if (sctx->gs_shader.cso)
234 primgroup_size = 64; /* recommended with a GS */
235
236 if (sctx->tes_shader.cso) {
237 unsigned num_cp_out =
238 sctx->tcs_shader.cso ?
239 sctx->tcs_shader.cso->info.properties[TGSI_PROPERTY_TCS_VERTICES_OUT] :
240 info->vertices_per_patch;
241 unsigned max_size = 256 / MAX2(info->vertices_per_patch, num_cp_out);
242
243 primgroup_size = MIN2(primgroup_size, max_size);
244
245 /* primgroup_size must be set to a multiple of NUM_PATCHES */
246 primgroup_size = (primgroup_size / num_patches) * num_patches;
247
248 /* SWITCH_ON_EOI must be set if PrimID is used. */
249 if ((sctx->tcs_shader.cso && sctx->tcs_shader.cso->info.uses_primid) ||
250 sctx->tes_shader.cso->info.uses_primid)
251 ia_switch_on_eoi = true;
252
253 /* Bug with tessellation and GS on Bonaire and older 2 SE chips. */
254 if ((sctx->b.family == CHIP_TAHITI ||
255 sctx->b.family == CHIP_PITCAIRN ||
256 sctx->b.family == CHIP_BONAIRE) &&
257 sctx->gs_shader.cso)
258 partial_vs_wave = true;
259 }
260
261 /* This is a hardware requirement. */
262 if ((rs && rs->line_stipple_enable) ||
263 (sctx->b.screen->debug_flags & DBG_SWITCH_ON_EOP)) {
264 ia_switch_on_eop = true;
265 wd_switch_on_eop = true;
266 }
267
268 if (sctx->b.chip_class >= CIK) {
269 /* WD_SWITCH_ON_EOP has no effect on GPUs with less than
270 * 4 shader engines. Set 1 to pass the assertion below.
271 * The other cases are hardware requirements. */
272 if (sctx->b.screen->info.max_se < 4 ||
273 prim == PIPE_PRIM_POLYGON ||
274 prim == PIPE_PRIM_LINE_LOOP ||
275 prim == PIPE_PRIM_TRIANGLE_FAN ||
276 prim == PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY ||
277 info->primitive_restart ||
278 info->count_from_stream_output)
279 wd_switch_on_eop = true;
280
281 /* Hawaii hangs if instancing is enabled and WD_SWITCH_ON_EOP is 0.
282 * We don't know that for indirect drawing, so treat it as
283 * always problematic. */
284 if (sctx->b.family == CHIP_HAWAII &&
285 (info->indirect || info->instance_count > 1))
286 wd_switch_on_eop = true;
287
288 /* Required on CIK and later. */
289 if (sctx->b.screen->info.max_se > 2 && !wd_switch_on_eop)
290 ia_switch_on_eoi = true;
291
292 /* Required by Hawaii and, for some special cases, by VI. */
293 if (ia_switch_on_eoi &&
294 (sctx->b.family == CHIP_HAWAII ||
295 (sctx->b.chip_class == VI &&
296 (sctx->gs_shader.cso || max_primgroup_in_wave != 2))))
297 partial_vs_wave = true;
298
299 /* Instancing bug on Bonaire. */
300 if (sctx->b.family == CHIP_BONAIRE && ia_switch_on_eoi &&
301 (info->indirect || info->instance_count > 1))
302 partial_vs_wave = true;
303
304 /* If the WD switch is false, the IA switch must be false too. */
305 assert(wd_switch_on_eop || !ia_switch_on_eop);
306 }
307
308 /* If SWITCH_ON_EOI is set, PARTIAL_ES_WAVE must be set too. */
309 if (ia_switch_on_eoi)
310 partial_es_wave = true;
311
312 /* GS requirement. */
313 if (SI_GS_PER_ES / primgroup_size >= sctx->screen->gs_table_depth - 3)
314 partial_es_wave = true;
315
316 /* Hw bug with single-primitive instances and SWITCH_ON_EOI
317 * on multi-SE chips. */
318 if (sctx->b.screen->info.max_se >= 2 && ia_switch_on_eoi &&
319 (info->indirect ||
320 (info->instance_count > 1 &&
321 si_num_prims_for_vertices(info) <= 1)))
322 sctx->b.flags |= SI_CONTEXT_VGT_FLUSH;
323
324 return S_028AA8_SWITCH_ON_EOP(ia_switch_on_eop) |
325 S_028AA8_SWITCH_ON_EOI(ia_switch_on_eoi) |
326 S_028AA8_PARTIAL_VS_WAVE_ON(partial_vs_wave) |
327 S_028AA8_PARTIAL_ES_WAVE_ON(partial_es_wave) |
328 S_028AA8_PRIMGROUP_SIZE(primgroup_size - 1) |
329 S_028AA8_WD_SWITCH_ON_EOP(sctx->b.chip_class >= CIK ? wd_switch_on_eop : 0) |
330 S_028AA8_MAX_PRIMGRP_IN_WAVE(sctx->b.chip_class >= VI ?
331 max_primgroup_in_wave : 0);
332 }
333
334 static unsigned si_get_ls_hs_config(struct si_context *sctx,
335 const struct pipe_draw_info *info,
336 unsigned num_patches)
337 {
338 unsigned num_output_cp;
339
340 if (!sctx->tes_shader.cso)
341 return 0;
342
343 num_output_cp = sctx->tcs_shader.cso ?
344 sctx->tcs_shader.cso->info.properties[TGSI_PROPERTY_TCS_VERTICES_OUT] :
345 info->vertices_per_patch;
346
347 return S_028B58_NUM_PATCHES(num_patches) |
348 S_028B58_HS_NUM_INPUT_CP(info->vertices_per_patch) |
349 S_028B58_HS_NUM_OUTPUT_CP(num_output_cp);
350 }
351
352 static void si_emit_scratch_reloc(struct si_context *sctx)
353 {
354 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
355
356 if (!sctx->emit_scratch_reloc)
357 return;
358
359 radeon_set_context_reg(cs, R_0286E8_SPI_TMPRING_SIZE,
360 sctx->spi_tmpring_size);
361
362 if (sctx->scratch_buffer) {
363 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
364 sctx->scratch_buffer, RADEON_USAGE_READWRITE,
365 RADEON_PRIO_SCRATCH_BUFFER);
366
367 }
368 sctx->emit_scratch_reloc = false;
369 }
370
371 /* rast_prim is the primitive type after GS. */
372 static void si_emit_rasterizer_prim_state(struct si_context *sctx)
373 {
374 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
375 unsigned rast_prim = sctx->current_rast_prim;
376 struct si_state_rasterizer *rs = sctx->emitted.named.rasterizer;
377
378 /* Skip this if not rendering lines. */
379 if (rast_prim != PIPE_PRIM_LINES &&
380 rast_prim != PIPE_PRIM_LINE_LOOP &&
381 rast_prim != PIPE_PRIM_LINE_STRIP &&
382 rast_prim != PIPE_PRIM_LINES_ADJACENCY &&
383 rast_prim != PIPE_PRIM_LINE_STRIP_ADJACENCY)
384 return;
385
386 if (rast_prim == sctx->last_rast_prim &&
387 rs->pa_sc_line_stipple == sctx->last_sc_line_stipple)
388 return;
389
390 radeon_set_context_reg(cs, R_028A0C_PA_SC_LINE_STIPPLE,
391 rs->pa_sc_line_stipple |
392 S_028A0C_AUTO_RESET_CNTL(rast_prim == PIPE_PRIM_LINES ? 1 :
393 rast_prim == PIPE_PRIM_LINE_STRIP ? 2 : 0));
394
395 sctx->last_rast_prim = rast_prim;
396 sctx->last_sc_line_stipple = rs->pa_sc_line_stipple;
397 }
398
399 static void si_emit_draw_registers(struct si_context *sctx,
400 const struct pipe_draw_info *info)
401 {
402 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
403 unsigned prim = si_conv_pipe_prim(info->mode);
404 unsigned gs_out_prim = si_conv_prim_to_gs_out(sctx->current_rast_prim);
405 unsigned ia_multi_vgt_param, ls_hs_config, num_patches = 0;
406
407 if (sctx->tes_shader.cso)
408 si_emit_derived_tess_state(sctx, info, &num_patches);
409
410 ia_multi_vgt_param = si_get_ia_multi_vgt_param(sctx, info, num_patches);
411 ls_hs_config = si_get_ls_hs_config(sctx, info, num_patches);
412
413 /* Draw state. */
414 if (prim != sctx->last_prim ||
415 ia_multi_vgt_param != sctx->last_multi_vgt_param ||
416 ls_hs_config != sctx->last_ls_hs_config) {
417 if (sctx->b.chip_class >= CIK) {
418 radeon_emit(cs, PKT3(PKT3_DRAW_PREAMBLE, 2, 0));
419 radeon_emit(cs, prim); /* VGT_PRIMITIVE_TYPE */
420 radeon_emit(cs, ia_multi_vgt_param); /* IA_MULTI_VGT_PARAM */
421 radeon_emit(cs, ls_hs_config); /* VGT_LS_HS_CONFIG */
422 } else {
423 radeon_set_config_reg(cs, R_008958_VGT_PRIMITIVE_TYPE, prim);
424 radeon_set_context_reg(cs, R_028AA8_IA_MULTI_VGT_PARAM, ia_multi_vgt_param);
425 radeon_set_context_reg(cs, R_028B58_VGT_LS_HS_CONFIG, ls_hs_config);
426 }
427 sctx->last_prim = prim;
428 sctx->last_multi_vgt_param = ia_multi_vgt_param;
429 sctx->last_ls_hs_config = ls_hs_config;
430 }
431
432 if (gs_out_prim != sctx->last_gs_out_prim) {
433 radeon_set_context_reg(cs, R_028A6C_VGT_GS_OUT_PRIM_TYPE, gs_out_prim);
434 sctx->last_gs_out_prim = gs_out_prim;
435 }
436
437 /* Primitive restart. */
438 if (info->primitive_restart != sctx->last_primitive_restart_en) {
439 radeon_set_context_reg(cs, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, info->primitive_restart);
440 sctx->last_primitive_restart_en = info->primitive_restart;
441
442 if (info->primitive_restart &&
443 (info->restart_index != sctx->last_restart_index ||
444 sctx->last_restart_index == SI_RESTART_INDEX_UNKNOWN)) {
445 radeon_set_context_reg(cs, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
446 info->restart_index);
447 sctx->last_restart_index = info->restart_index;
448 }
449 }
450 }
451
452 static void si_emit_draw_packets(struct si_context *sctx,
453 const struct pipe_draw_info *info,
454 const struct pipe_index_buffer *ib)
455 {
456 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
457 unsigned sh_base_reg = sctx->shader_userdata.sh_base[PIPE_SHADER_VERTEX];
458 bool render_cond_bit = sctx->b.render_cond && !sctx->b.render_cond_force_off;
459
460 if (info->count_from_stream_output) {
461 struct r600_so_target *t =
462 (struct r600_so_target*)info->count_from_stream_output;
463 uint64_t va = t->buf_filled_size->gpu_address +
464 t->buf_filled_size_offset;
465
466 radeon_set_context_reg(cs, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE,
467 t->stride_in_dw);
468
469 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
470 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
471 COPY_DATA_DST_SEL(COPY_DATA_REG) |
472 COPY_DATA_WR_CONFIRM);
473 radeon_emit(cs, va); /* src address lo */
474 radeon_emit(cs, va >> 32); /* src address hi */
475 radeon_emit(cs, R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE >> 2);
476 radeon_emit(cs, 0); /* unused */
477
478 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
479 t->buf_filled_size, RADEON_USAGE_READ,
480 RADEON_PRIO_SO_FILLED_SIZE);
481 }
482
483 /* draw packet */
484 if (info->indexed) {
485 radeon_emit(cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
486
487 /* index type */
488 switch (ib->index_size) {
489 case 1:
490 radeon_emit(cs, V_028A7C_VGT_INDEX_8);
491 break;
492 case 2:
493 radeon_emit(cs, V_028A7C_VGT_INDEX_16 |
494 (SI_BIG_ENDIAN && sctx->b.chip_class <= CIK ?
495 V_028A7C_VGT_DMA_SWAP_16_BIT : 0));
496 break;
497 case 4:
498 radeon_emit(cs, V_028A7C_VGT_INDEX_32 |
499 (SI_BIG_ENDIAN && sctx->b.chip_class <= CIK ?
500 V_028A7C_VGT_DMA_SWAP_32_BIT : 0));
501 break;
502 default:
503 assert(!"unreachable");
504 return;
505 }
506 }
507
508 if (!info->indirect) {
509 int base_vertex;
510
511 radeon_emit(cs, PKT3(PKT3_NUM_INSTANCES, 0, 0));
512 radeon_emit(cs, info->instance_count);
513
514 /* Base vertex and start instance. */
515 base_vertex = info->indexed ? info->index_bias : info->start;
516
517 if (base_vertex != sctx->last_base_vertex ||
518 sctx->last_base_vertex == SI_BASE_VERTEX_UNKNOWN ||
519 info->start_instance != sctx->last_start_instance ||
520 sh_base_reg != sctx->last_sh_base_reg) {
521 radeon_set_sh_reg_seq(cs, sh_base_reg + SI_SGPR_BASE_VERTEX * 4, 2);
522 radeon_emit(cs, base_vertex);
523 radeon_emit(cs, info->start_instance);
524
525 sctx->last_base_vertex = base_vertex;
526 sctx->last_start_instance = info->start_instance;
527 sctx->last_sh_base_reg = sh_base_reg;
528 }
529 } else {
530 si_invalidate_draw_sh_constants(sctx);
531
532 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
533 (struct r600_resource *)info->indirect,
534 RADEON_USAGE_READ, RADEON_PRIO_DRAW_INDIRECT);
535 }
536
537 if (info->indexed) {
538 uint32_t index_max_size = (ib->buffer->width0 - ib->offset) /
539 ib->index_size;
540 uint64_t index_va = r600_resource(ib->buffer)->gpu_address + ib->offset;
541
542 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
543 (struct r600_resource *)ib->buffer,
544 RADEON_USAGE_READ, RADEON_PRIO_INDEX_BUFFER);
545
546 if (info->indirect) {
547 uint64_t indirect_va = r600_resource(info->indirect)->gpu_address;
548
549 assert(indirect_va % 8 == 0);
550 assert(index_va % 2 == 0);
551 assert(info->indirect_offset % 4 == 0);
552
553 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
554 radeon_emit(cs, 1);
555 radeon_emit(cs, indirect_va);
556 radeon_emit(cs, indirect_va >> 32);
557
558 radeon_emit(cs, PKT3(PKT3_INDEX_BASE, 1, 0));
559 radeon_emit(cs, index_va);
560 radeon_emit(cs, index_va >> 32);
561
562 radeon_emit(cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
563 radeon_emit(cs, index_max_size);
564
565 radeon_emit(cs, PKT3(PKT3_DRAW_INDEX_INDIRECT, 3, render_cond_bit));
566 radeon_emit(cs, info->indirect_offset);
567 radeon_emit(cs, (sh_base_reg + SI_SGPR_BASE_VERTEX * 4 - SI_SH_REG_OFFSET) >> 2);
568 radeon_emit(cs, (sh_base_reg + SI_SGPR_START_INSTANCE * 4 - SI_SH_REG_OFFSET) >> 2);
569 radeon_emit(cs, V_0287F0_DI_SRC_SEL_DMA);
570 } else {
571 index_va += info->start * ib->index_size;
572
573 radeon_emit(cs, PKT3(PKT3_DRAW_INDEX_2, 4, render_cond_bit));
574 radeon_emit(cs, index_max_size);
575 radeon_emit(cs, index_va);
576 radeon_emit(cs, (index_va >> 32UL) & 0xFF);
577 radeon_emit(cs, info->count);
578 radeon_emit(cs, V_0287F0_DI_SRC_SEL_DMA);
579 }
580 } else {
581 if (info->indirect) {
582 uint64_t indirect_va = r600_resource(info->indirect)->gpu_address;
583
584 assert(indirect_va % 8 == 0);
585 assert(info->indirect_offset % 4 == 0);
586
587 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
588 radeon_emit(cs, 1);
589 radeon_emit(cs, indirect_va);
590 radeon_emit(cs, indirect_va >> 32);
591
592 radeon_emit(cs, PKT3(PKT3_DRAW_INDIRECT, 3, render_cond_bit));
593 radeon_emit(cs, info->indirect_offset);
594 radeon_emit(cs, (sh_base_reg + SI_SGPR_BASE_VERTEX * 4 - SI_SH_REG_OFFSET) >> 2);
595 radeon_emit(cs, (sh_base_reg + SI_SGPR_START_INSTANCE * 4 - SI_SH_REG_OFFSET) >> 2);
596 radeon_emit(cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX);
597 } else {
598 radeon_emit(cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, render_cond_bit));
599 radeon_emit(cs, info->count);
600 radeon_emit(cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
601 S_0287F0_USE_OPAQUE(!!info->count_from_stream_output));
602 }
603 }
604 }
605
606 void si_emit_cache_flush(struct si_context *si_ctx, struct r600_atom *atom)
607 {
608 struct r600_common_context *sctx = &si_ctx->b;
609 struct radeon_winsys_cs *cs = sctx->gfx.cs;
610 uint32_t cp_coher_cntl = 0;
611
612 /* SI has a bug that it always flushes ICACHE and KCACHE if either
613 * bit is set. An alternative way is to write SQC_CACHES, but that
614 * doesn't seem to work reliably. Since the bug doesn't affect
615 * correctness (it only does more work than necessary) and
616 * the performance impact is likely negligible, there is no plan
617 * to add a workaround for it.
618 */
619
620 if (sctx->flags & SI_CONTEXT_INV_ICACHE)
621 cp_coher_cntl |= S_0085F0_SH_ICACHE_ACTION_ENA(1);
622 if (sctx->flags & SI_CONTEXT_INV_SMEM_L1)
623 cp_coher_cntl |= S_0085F0_SH_KCACHE_ACTION_ENA(1);
624
625 if (sctx->flags & SI_CONTEXT_INV_VMEM_L1)
626 cp_coher_cntl |= S_0085F0_TCL1_ACTION_ENA(1);
627 if (sctx->flags & SI_CONTEXT_INV_GLOBAL_L2) {
628 cp_coher_cntl |= S_0085F0_TC_ACTION_ENA(1);
629
630 if (sctx->chip_class >= VI)
631 cp_coher_cntl |= S_0301F0_TC_WB_ACTION_ENA(1);
632 }
633
634 if (sctx->flags & SI_CONTEXT_FLUSH_AND_INV_CB) {
635 cp_coher_cntl |= S_0085F0_CB_ACTION_ENA(1) |
636 S_0085F0_CB0_DEST_BASE_ENA(1) |
637 S_0085F0_CB1_DEST_BASE_ENA(1) |
638 S_0085F0_CB2_DEST_BASE_ENA(1) |
639 S_0085F0_CB3_DEST_BASE_ENA(1) |
640 S_0085F0_CB4_DEST_BASE_ENA(1) |
641 S_0085F0_CB5_DEST_BASE_ENA(1) |
642 S_0085F0_CB6_DEST_BASE_ENA(1) |
643 S_0085F0_CB7_DEST_BASE_ENA(1);
644
645 /* Necessary for DCC */
646 if (sctx->chip_class >= VI) {
647 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, 0));
648 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_DATA_TS) |
649 EVENT_INDEX(5));
650 radeon_emit(cs, 0);
651 radeon_emit(cs, 0);
652 radeon_emit(cs, 0);
653 radeon_emit(cs, 0);
654 }
655 }
656 if (sctx->flags & SI_CONTEXT_FLUSH_AND_INV_DB) {
657 cp_coher_cntl |= S_0085F0_DB_ACTION_ENA(1) |
658 S_0085F0_DB_DEST_BASE_ENA(1);
659 }
660
661 if (sctx->flags & SI_CONTEXT_FLUSH_AND_INV_CB_META) {
662 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
663 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_META) | EVENT_INDEX(0));
664 /* needed for wait for idle in SURFACE_SYNC */
665 assert(sctx->flags & SI_CONTEXT_FLUSH_AND_INV_CB);
666 }
667 if (sctx->flags & SI_CONTEXT_FLUSH_AND_INV_DB_META) {
668 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
669 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_DB_META) | EVENT_INDEX(0));
670 /* needed for wait for idle in SURFACE_SYNC */
671 assert(sctx->flags & SI_CONTEXT_FLUSH_AND_INV_DB);
672 }
673
674 /* Wait for shader engines to go idle.
675 * VS and PS waits are unnecessary if SURFACE_SYNC is going to wait
676 * for everything including CB/DB cache flushes.
677 */
678 if (!(sctx->flags & (SI_CONTEXT_FLUSH_AND_INV_CB |
679 SI_CONTEXT_FLUSH_AND_INV_DB))) {
680 if (sctx->flags & SI_CONTEXT_PS_PARTIAL_FLUSH) {
681 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
682 radeon_emit(cs, EVENT_TYPE(V_028A90_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
683 } else if (sctx->flags & SI_CONTEXT_VS_PARTIAL_FLUSH) {
684 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
685 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
686 }
687 }
688 if (sctx->flags & SI_CONTEXT_CS_PARTIAL_FLUSH) {
689 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
690 radeon_emit(cs, EVENT_TYPE(V_028A90_CS_PARTIAL_FLUSH | EVENT_INDEX(4)));
691 }
692
693 /* VGT state synchronization. */
694 if (sctx->flags & SI_CONTEXT_VGT_FLUSH) {
695 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
696 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
697 }
698 if (sctx->flags & SI_CONTEXT_VGT_STREAMOUT_SYNC) {
699 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
700 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_STREAMOUT_SYNC) | EVENT_INDEX(0));
701 }
702
703 /* Make sure ME is idle (it executes most packets) before continuing.
704 * This prevents read-after-write hazards between PFP and ME.
705 */
706 if (cp_coher_cntl || (sctx->flags & SI_CONTEXT_CS_PARTIAL_FLUSH)) {
707 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
708 radeon_emit(cs, 0);
709 }
710
711 /* When one of the DEST_BASE flags is set, SURFACE_SYNC waits for idle.
712 * Therefore, it should be last. Done in PFP.
713 */
714 if (cp_coher_cntl) {
715 /* ACQUIRE_MEM is only required on a compute ring. */
716 radeon_emit(cs, PKT3(PKT3_SURFACE_SYNC, 3, 0));
717 radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */
718 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
719 radeon_emit(cs, 0); /* CP_COHER_BASE */
720 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
721 }
722
723 if (sctx->flags & R600_CONTEXT_START_PIPELINE_STATS) {
724 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
725 radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_START) |
726 EVENT_INDEX(0));
727 } else if (sctx->flags & R600_CONTEXT_STOP_PIPELINE_STATS) {
728 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
729 radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_STOP) |
730 EVENT_INDEX(0));
731 }
732
733 sctx->flags = 0;
734 }
735
736 static void si_get_draw_start_count(struct si_context *sctx,
737 const struct pipe_draw_info *info,
738 unsigned *start, unsigned *count)
739 {
740 if (info->indirect) {
741 struct r600_resource *indirect =
742 (struct r600_resource*)info->indirect;
743 int *data = r600_buffer_map_sync_with_rings(&sctx->b,
744 indirect, PIPE_TRANSFER_READ);
745 data += info->indirect_offset/sizeof(int);
746 *start = data[2];
747 *count = data[0];
748 } else {
749 *start = info->start;
750 *count = info->count;
751 }
752 }
753
754 void si_ce_pre_draw_synchronization(struct si_context *sctx)
755 {
756 if (sctx->ce_need_synchronization) {
757 radeon_emit(sctx->ce_ib, PKT3(PKT3_INCREMENT_CE_COUNTER, 0, 0));
758 radeon_emit(sctx->ce_ib, 1);
759
760 radeon_emit(sctx->b.gfx.cs, PKT3(PKT3_WAIT_ON_CE_COUNTER, 0, 0));
761 radeon_emit(sctx->b.gfx.cs, 1);
762 }
763 }
764
765 void si_ce_post_draw_synchronization(struct si_context *sctx)
766 {
767 if (sctx->ce_need_synchronization) {
768 radeon_emit(sctx->b.gfx.cs, PKT3(PKT3_INCREMENT_DE_COUNTER, 0, 0));
769 radeon_emit(sctx->b.gfx.cs, 0);
770
771 sctx->ce_need_synchronization = false;
772 }
773 }
774
775 void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info)
776 {
777 struct si_context *sctx = (struct si_context *)ctx;
778 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
779 struct pipe_index_buffer ib = {};
780 unsigned mask, dirty_fb_counter;
781
782 if (!info->count && !info->indirect &&
783 (info->indexed || !info->count_from_stream_output))
784 return;
785
786 if (!sctx->vs_shader.cso) {
787 assert(0);
788 return;
789 }
790 if (!sctx->ps_shader.cso && (!rs || !rs->rasterizer_discard)) {
791 assert(0);
792 return;
793 }
794 if (!!sctx->tes_shader.cso != (info->mode == PIPE_PRIM_PATCHES)) {
795 assert(0);
796 return;
797 }
798
799 /* Re-emit the framebuffer state if needed. */
800 dirty_fb_counter = p_atomic_read(&sctx->b.screen->dirty_fb_counter);
801 if (dirty_fb_counter != sctx->b.last_dirty_fb_counter) {
802 sctx->b.last_dirty_fb_counter = dirty_fb_counter;
803 sctx->framebuffer.dirty_cbufs |=
804 ((1 << sctx->framebuffer.state.nr_cbufs) - 1);
805 sctx->framebuffer.dirty_zsbuf = true;
806 si_mark_atom_dirty(sctx, &sctx->framebuffer.atom);
807 }
808
809 si_decompress_graphics_textures(sctx);
810
811 /* Set the rasterization primitive type.
812 *
813 * This must be done after si_decompress_textures, which can call
814 * draw_vbo recursively, and before si_update_shaders, which uses
815 * current_rast_prim for this draw_vbo call. */
816 if (sctx->gs_shader.cso)
817 sctx->current_rast_prim = sctx->gs_shader.cso->gs_output_prim;
818 else if (sctx->tes_shader.cso)
819 sctx->current_rast_prim =
820 sctx->tes_shader.cso->info.properties[TGSI_PROPERTY_TES_PRIM_MODE];
821 else
822 sctx->current_rast_prim = info->mode;
823
824 if (!si_update_shaders(sctx) ||
825 !si_upload_graphics_shader_descriptors(sctx))
826 return;
827
828 if (info->indexed) {
829 /* Initialize the index buffer struct. */
830 pipe_resource_reference(&ib.buffer, sctx->index_buffer.buffer);
831 ib.user_buffer = sctx->index_buffer.user_buffer;
832 ib.index_size = sctx->index_buffer.index_size;
833 ib.offset = sctx->index_buffer.offset;
834
835 /* Translate or upload, if needed. */
836 /* 8-bit indices are supported on VI. */
837 if (sctx->b.chip_class <= CIK && ib.index_size == 1) {
838 struct pipe_resource *out_buffer = NULL;
839 unsigned out_offset, start, count, start_offset;
840 void *ptr;
841
842 si_get_draw_start_count(sctx, info, &start, &count);
843 start_offset = start * ib.index_size;
844
845 u_upload_alloc(sctx->b.uploader, start_offset, count * 2, 256,
846 &out_offset, &out_buffer, &ptr);
847 if (!out_buffer) {
848 pipe_resource_reference(&ib.buffer, NULL);
849 return;
850 }
851
852 util_shorten_ubyte_elts_to_userptr(&sctx->b.b, &ib, 0,
853 ib.offset + start_offset,
854 count, ptr);
855
856 pipe_resource_reference(&ib.buffer, NULL);
857 ib.user_buffer = NULL;
858 ib.buffer = out_buffer;
859 /* info->start will be added by the drawing code */
860 ib.offset = out_offset - start_offset;
861 ib.index_size = 2;
862 } else if (ib.user_buffer && !ib.buffer) {
863 unsigned start, count, start_offset;
864
865 si_get_draw_start_count(sctx, info, &start, &count);
866 start_offset = start * ib.index_size;
867
868 u_upload_data(sctx->b.uploader, start_offset, count * ib.index_size,
869 256, (char*)ib.user_buffer + start_offset,
870 &ib.offset, &ib.buffer);
871 if (!ib.buffer)
872 return;
873 /* info->start will be added by the drawing code */
874 ib.offset -= start_offset;
875 }
876 }
877
878 /* VI reads index buffers through TC L2. */
879 if (info->indexed && sctx->b.chip_class <= CIK &&
880 r600_resource(ib.buffer)->TC_L2_dirty) {
881 sctx->b.flags |= SI_CONTEXT_INV_GLOBAL_L2;
882 r600_resource(ib.buffer)->TC_L2_dirty = false;
883 }
884
885 /* Check flush flags. */
886 if (sctx->b.flags)
887 si_mark_atom_dirty(sctx, sctx->atoms.s.cache_flush);
888
889 si_need_cs_space(sctx);
890
891 /* Emit states. */
892 mask = sctx->dirty_atoms;
893 while (mask) {
894 struct r600_atom *atom = sctx->atoms.array[u_bit_scan(&mask)];
895
896 atom->emit(&sctx->b, atom);
897 }
898 sctx->dirty_atoms = 0;
899
900 si_pm4_emit_dirty(sctx);
901 si_emit_scratch_reloc(sctx);
902 si_emit_rasterizer_prim_state(sctx);
903 si_emit_draw_registers(sctx, info);
904
905 si_ce_pre_draw_synchronization(sctx);
906
907 si_emit_draw_packets(sctx, info, &ib);
908
909 si_ce_post_draw_synchronization(sctx);
910
911 if (sctx->trace_buf)
912 si_trace_emit(sctx);
913
914 /* Workaround for a VGT hang when streamout is enabled.
915 * It must be done after drawing. */
916 if ((sctx->b.family == CHIP_HAWAII ||
917 sctx->b.family == CHIP_TONGA ||
918 sctx->b.family == CHIP_FIJI) &&
919 r600_get_strmout_en(&sctx->b)) {
920 sctx->b.flags |= SI_CONTEXT_VGT_STREAMOUT_SYNC;
921 }
922
923 /* Set the depth buffer as dirty. */
924 if (sctx->framebuffer.state.zsbuf) {
925 struct pipe_surface *surf = sctx->framebuffer.state.zsbuf;
926 struct r600_texture *rtex = (struct r600_texture *)surf->texture;
927
928 rtex->dirty_level_mask |= 1 << surf->u.tex.level;
929
930 if (rtex->surface.flags & RADEON_SURF_SBUFFER)
931 rtex->stencil_dirty_level_mask |= 1 << surf->u.tex.level;
932 }
933 if (sctx->framebuffer.compressed_cb_mask) {
934 struct pipe_surface *surf;
935 struct r600_texture *rtex;
936 unsigned mask = sctx->framebuffer.compressed_cb_mask;
937
938 do {
939 unsigned i = u_bit_scan(&mask);
940 surf = sctx->framebuffer.state.cbufs[i];
941 rtex = (struct r600_texture*)surf->texture;
942
943 rtex->dirty_level_mask |= 1 << surf->u.tex.level;
944 } while (mask);
945 }
946
947 pipe_resource_reference(&ib.buffer, NULL);
948 sctx->b.num_draw_calls++;
949 }
950
951 void si_trace_emit(struct si_context *sctx)
952 {
953 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
954
955 sctx->trace_id++;
956 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, sctx->trace_buf,
957 RADEON_USAGE_READWRITE, RADEON_PRIO_TRACE);
958 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
959 radeon_emit(cs, S_370_DST_SEL(V_370_MEMORY_SYNC) |
960 S_370_WR_CONFIRM(1) |
961 S_370_ENGINE_SEL(V_370_ME));
962 radeon_emit(cs, sctx->trace_buf->gpu_address);
963 radeon_emit(cs, sctx->trace_buf->gpu_address >> 32);
964 radeon_emit(cs, sctx->trace_id);
965 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
966 radeon_emit(cs, SI_ENCODE_TRACE_POINT(sctx->trace_id));
967 }