2 * Copyright 2012 Advanced Micro Devices, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
25 #include "si_build_pm4.h"
28 #include "util/u_index_modify.h"
29 #include "util/u_log.h"
30 #include "util/u_upload_mgr.h"
31 #include "util/u_prim.h"
32 #include "util/u_suballoc.h"
36 /* special primitive types */
37 #define SI_PRIM_RECTANGLE_LIST PIPE_PRIM_MAX
39 static unsigned si_conv_pipe_prim(unsigned mode
)
41 static const unsigned prim_conv
[] = {
42 [PIPE_PRIM_POINTS
] = V_008958_DI_PT_POINTLIST
,
43 [PIPE_PRIM_LINES
] = V_008958_DI_PT_LINELIST
,
44 [PIPE_PRIM_LINE_LOOP
] = V_008958_DI_PT_LINELOOP
,
45 [PIPE_PRIM_LINE_STRIP
] = V_008958_DI_PT_LINESTRIP
,
46 [PIPE_PRIM_TRIANGLES
] = V_008958_DI_PT_TRILIST
,
47 [PIPE_PRIM_TRIANGLE_STRIP
] = V_008958_DI_PT_TRISTRIP
,
48 [PIPE_PRIM_TRIANGLE_FAN
] = V_008958_DI_PT_TRIFAN
,
49 [PIPE_PRIM_QUADS
] = V_008958_DI_PT_QUADLIST
,
50 [PIPE_PRIM_QUAD_STRIP
] = V_008958_DI_PT_QUADSTRIP
,
51 [PIPE_PRIM_POLYGON
] = V_008958_DI_PT_POLYGON
,
52 [PIPE_PRIM_LINES_ADJACENCY
] = V_008958_DI_PT_LINELIST_ADJ
,
53 [PIPE_PRIM_LINE_STRIP_ADJACENCY
] = V_008958_DI_PT_LINESTRIP_ADJ
,
54 [PIPE_PRIM_TRIANGLES_ADJACENCY
] = V_008958_DI_PT_TRILIST_ADJ
,
55 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY
] = V_008958_DI_PT_TRISTRIP_ADJ
,
56 [PIPE_PRIM_PATCHES
] = V_008958_DI_PT_PATCH
,
57 [SI_PRIM_RECTANGLE_LIST
] = V_008958_DI_PT_RECTLIST
59 assert(mode
< ARRAY_SIZE(prim_conv
));
60 return prim_conv
[mode
];
64 * This calculates the LDS size for tessellation shaders (VS, TCS, TES).
65 * LS.LDS_SIZE is shared by all 3 shader stages.
67 * The information about LDS and other non-compile-time parameters is then
68 * written to userdata SGPRs.
70 static void si_emit_derived_tess_state(struct si_context
*sctx
,
71 const struct pipe_draw_info
*info
,
72 unsigned *num_patches
)
74 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
75 struct si_shader
*ls_current
;
76 struct si_shader_selector
*ls
;
77 /* The TES pointer will only be used for sctx->last_tcs.
78 * It would be wrong to think that TCS = TES. */
79 struct si_shader_selector
*tcs
=
80 sctx
->tcs_shader
.cso
? sctx
->tcs_shader
.cso
: sctx
->tes_shader
.cso
;
81 unsigned tess_uses_primid
= sctx
->ia_multi_vgt_param_key
.u
.tess_uses_prim_id
;
82 bool has_primid_instancing_bug
= sctx
->chip_class
== GFX6
&&
83 sctx
->screen
->info
.max_se
== 1;
84 unsigned tes_sh_base
= sctx
->shader_pointers
.sh_base
[PIPE_SHADER_TESS_EVAL
];
85 unsigned num_tcs_input_cp
= info
->vertices_per_patch
;
86 unsigned num_tcs_output_cp
, num_tcs_inputs
, num_tcs_outputs
;
87 unsigned num_tcs_patch_outputs
;
88 unsigned input_vertex_size
, output_vertex_size
, pervertex_output_patch_size
;
89 unsigned input_patch_size
, output_patch_size
, output_patch0_offset
;
90 unsigned perpatch_output_offset
, lds_size
;
91 unsigned tcs_in_layout
, tcs_out_layout
, tcs_out_offsets
;
92 unsigned offchip_layout
, hardware_lds_size
, ls_hs_config
;
94 /* Since GFX9 has merged LS-HS in the TCS state, set LS = TCS. */
95 if (sctx
->chip_class
>= GFX9
) {
96 if (sctx
->tcs_shader
.cso
)
97 ls_current
= sctx
->tcs_shader
.current
;
99 ls_current
= sctx
->fixed_func_tcs_shader
.current
;
101 ls
= ls_current
->key
.part
.tcs
.ls
;
103 ls_current
= sctx
->vs_shader
.current
;
104 ls
= sctx
->vs_shader
.cso
;
107 if (sctx
->last_ls
== ls_current
&&
108 sctx
->last_tcs
== tcs
&&
109 sctx
->last_tes_sh_base
== tes_sh_base
&&
110 sctx
->last_num_tcs_input_cp
== num_tcs_input_cp
&&
111 (!has_primid_instancing_bug
||
112 (sctx
->last_tess_uses_primid
== tess_uses_primid
))) {
113 *num_patches
= sctx
->last_num_patches
;
117 sctx
->last_ls
= ls_current
;
118 sctx
->last_tcs
= tcs
;
119 sctx
->last_tes_sh_base
= tes_sh_base
;
120 sctx
->last_num_tcs_input_cp
= num_tcs_input_cp
;
121 sctx
->last_tess_uses_primid
= tess_uses_primid
;
123 /* This calculates how shader inputs and outputs among VS, TCS, and TES
124 * are laid out in LDS. */
125 num_tcs_inputs
= util_last_bit64(ls
->outputs_written
);
127 if (sctx
->tcs_shader
.cso
) {
128 num_tcs_outputs
= util_last_bit64(tcs
->outputs_written
);
129 num_tcs_output_cp
= tcs
->info
.properties
[TGSI_PROPERTY_TCS_VERTICES_OUT
];
130 num_tcs_patch_outputs
= util_last_bit64(tcs
->patch_outputs_written
);
132 /* No TCS. Route varyings from LS to TES. */
133 num_tcs_outputs
= num_tcs_inputs
;
134 num_tcs_output_cp
= num_tcs_input_cp
;
135 num_tcs_patch_outputs
= 2; /* TESSINNER + TESSOUTER */
138 input_vertex_size
= ls
->lshs_vertex_stride
;
139 output_vertex_size
= num_tcs_outputs
* 16;
141 input_patch_size
= num_tcs_input_cp
* input_vertex_size
;
143 pervertex_output_patch_size
= num_tcs_output_cp
* output_vertex_size
;
144 output_patch_size
= pervertex_output_patch_size
+ num_tcs_patch_outputs
* 16;
146 /* Ensure that we only need one wave per SIMD so we don't need to check
147 * resource usage. Also ensures that the number of tcs in and out
148 * vertices per threadgroup are at most 256.
150 unsigned max_verts_per_patch
= MAX2(num_tcs_input_cp
, num_tcs_output_cp
);
151 *num_patches
= 256 / max_verts_per_patch
;
153 /* Make sure that the data fits in LDS. This assumes the shaders only
154 * use LDS for the inputs and outputs.
156 * While GFX7 can use 64K per threadgroup, there is a hang on Stoney
157 * with 2 CUs if we use more than 32K. The closed Vulkan driver also
158 * uses 32K at most on all GCN chips.
160 hardware_lds_size
= 32768;
161 *num_patches
= MIN2(*num_patches
, hardware_lds_size
/ (input_patch_size
+
164 /* Make sure the output data fits in the offchip buffer */
165 *num_patches
= MIN2(*num_patches
,
166 (sctx
->screen
->tess_offchip_block_dw_size
* 4) /
169 /* Not necessary for correctness, but improves performance.
170 * The hardware can do more, but the radeonsi shader constant is
173 *num_patches
= MIN2(*num_patches
, 63); /* triangles: 3 full waves except 3 lanes */
175 /* When distributed tessellation is unsupported, switch between SEs
176 * at a higher frequency to compensate for it.
178 if (!sctx
->screen
->has_distributed_tess
&& sctx
->screen
->info
.max_se
> 1)
179 *num_patches
= MIN2(*num_patches
, 16); /* recommended */
181 /* Make sure that vector lanes are reasonably occupied. It probably
182 * doesn't matter much because this is LS-HS, and TES is likely to
183 * occupy significantly more CUs.
185 unsigned temp_verts_per_tg
= *num_patches
* max_verts_per_patch
;
186 unsigned wave_size
= sctx
->screen
->ge_wave_size
;
188 if (temp_verts_per_tg
> wave_size
&& temp_verts_per_tg
% wave_size
< wave_size
*3/4)
189 *num_patches
= (temp_verts_per_tg
& ~(wave_size
- 1)) / max_verts_per_patch
;
191 if (sctx
->chip_class
== GFX6
) {
192 /* GFX6 bug workaround, related to power management. Limit LS-HS
193 * threadgroups to only one wave.
195 unsigned one_wave
= wave_size
/ max_verts_per_patch
;
196 *num_patches
= MIN2(*num_patches
, one_wave
);
199 /* The VGT HS block increments the patch ID unconditionally
200 * within a single threadgroup. This results in incorrect
201 * patch IDs when instanced draws are used.
203 * The intended solution is to restrict threadgroups to
204 * a single instance by setting SWITCH_ON_EOI, which
205 * should cause IA to split instances up. However, this
206 * doesn't work correctly on GFX6 when there is no other
209 if (has_primid_instancing_bug
&& tess_uses_primid
)
212 sctx
->last_num_patches
= *num_patches
;
214 output_patch0_offset
= input_patch_size
* *num_patches
;
215 perpatch_output_offset
= output_patch0_offset
+ pervertex_output_patch_size
;
217 /* Compute userdata SGPRs. */
218 assert(((input_vertex_size
/ 4) & ~0xff) == 0);
219 assert(((output_vertex_size
/ 4) & ~0xff) == 0);
220 assert(((input_patch_size
/ 4) & ~0x1fff) == 0);
221 assert(((output_patch_size
/ 4) & ~0x1fff) == 0);
222 assert(((output_patch0_offset
/ 16) & ~0xffff) == 0);
223 assert(((perpatch_output_offset
/ 16) & ~0xffff) == 0);
224 assert(num_tcs_input_cp
<= 32);
225 assert(num_tcs_output_cp
<= 32);
227 uint64_t ring_va
= si_resource(sctx
->tess_rings
)->gpu_address
;
228 assert((ring_va
& u_bit_consecutive(0, 19)) == 0);
230 tcs_in_layout
= S_VS_STATE_LS_OUT_PATCH_SIZE(input_patch_size
/ 4) |
231 S_VS_STATE_LS_OUT_VERTEX_SIZE(input_vertex_size
/ 4);
232 tcs_out_layout
= (output_patch_size
/ 4) |
233 (num_tcs_input_cp
<< 13) |
235 tcs_out_offsets
= (output_patch0_offset
/ 16) |
236 ((perpatch_output_offset
/ 16) << 16);
237 offchip_layout
= *num_patches
|
238 (num_tcs_output_cp
<< 6) |
239 (pervertex_output_patch_size
* *num_patches
<< 12);
241 /* Compute the LDS size. */
242 lds_size
= output_patch0_offset
+ output_patch_size
* *num_patches
;
244 if (sctx
->chip_class
>= GFX7
) {
245 assert(lds_size
<= 65536);
246 lds_size
= align(lds_size
, 512) / 512;
248 assert(lds_size
<= 32768);
249 lds_size
= align(lds_size
, 256) / 256;
252 /* Set SI_SGPR_VS_STATE_BITS. */
253 sctx
->current_vs_state
&= C_VS_STATE_LS_OUT_PATCH_SIZE
&
254 C_VS_STATE_LS_OUT_VERTEX_SIZE
;
255 sctx
->current_vs_state
|= tcs_in_layout
;
257 /* We should be able to support in-shader LDS use with LLVM >= 9
258 * by just adding the lds_sizes together, but it has never
260 assert(ls_current
->config
.lds_size
== 0);
262 if (sctx
->chip_class
>= GFX9
) {
263 unsigned hs_rsrc2
= ls_current
->config
.rsrc2
;
265 if (sctx
->chip_class
>= GFX10
)
266 hs_rsrc2
|= S_00B42C_LDS_SIZE_GFX10(lds_size
);
268 hs_rsrc2
|= S_00B42C_LDS_SIZE_GFX9(lds_size
);
270 radeon_set_sh_reg(cs
, R_00B42C_SPI_SHADER_PGM_RSRC2_HS
, hs_rsrc2
);
272 /* Set userdata SGPRs for merged LS-HS. */
273 radeon_set_sh_reg_seq(cs
,
274 R_00B430_SPI_SHADER_USER_DATA_LS_0
+
275 GFX9_SGPR_TCS_OFFCHIP_LAYOUT
* 4, 3);
276 radeon_emit(cs
, offchip_layout
);
277 radeon_emit(cs
, tcs_out_offsets
);
278 radeon_emit(cs
, tcs_out_layout
);
280 unsigned ls_rsrc2
= ls_current
->config
.rsrc2
;
282 si_multiwave_lds_size_workaround(sctx
->screen
, &lds_size
);
283 ls_rsrc2
|= S_00B52C_LDS_SIZE(lds_size
);
285 /* Due to a hw bug, RSRC2_LS must be written twice with another
286 * LS register written in between. */
287 if (sctx
->chip_class
== GFX7
&& sctx
->family
!= CHIP_HAWAII
)
288 radeon_set_sh_reg(cs
, R_00B52C_SPI_SHADER_PGM_RSRC2_LS
, ls_rsrc2
);
289 radeon_set_sh_reg_seq(cs
, R_00B528_SPI_SHADER_PGM_RSRC1_LS
, 2);
290 radeon_emit(cs
, ls_current
->config
.rsrc1
);
291 radeon_emit(cs
, ls_rsrc2
);
293 /* Set userdata SGPRs for TCS. */
294 radeon_set_sh_reg_seq(cs
,
295 R_00B430_SPI_SHADER_USER_DATA_HS_0
+ GFX6_SGPR_TCS_OFFCHIP_LAYOUT
* 4, 4);
296 radeon_emit(cs
, offchip_layout
);
297 radeon_emit(cs
, tcs_out_offsets
);
298 radeon_emit(cs
, tcs_out_layout
);
299 radeon_emit(cs
, tcs_in_layout
);
302 /* Set userdata SGPRs for TES. */
303 radeon_set_sh_reg_seq(cs
, tes_sh_base
+ SI_SGPR_TES_OFFCHIP_LAYOUT
* 4, 2);
304 radeon_emit(cs
, offchip_layout
);
305 radeon_emit(cs
, ring_va
);
307 ls_hs_config
= S_028B58_NUM_PATCHES(*num_patches
) |
308 S_028B58_HS_NUM_INPUT_CP(num_tcs_input_cp
) |
309 S_028B58_HS_NUM_OUTPUT_CP(num_tcs_output_cp
);
311 if (sctx
->last_ls_hs_config
!= ls_hs_config
) {
312 if (sctx
->chip_class
>= GFX7
) {
313 radeon_set_context_reg_idx(cs
, R_028B58_VGT_LS_HS_CONFIG
, 2,
316 radeon_set_context_reg(cs
, R_028B58_VGT_LS_HS_CONFIG
,
319 sctx
->last_ls_hs_config
= ls_hs_config
;
320 sctx
->context_roll
= true;
324 static unsigned si_num_prims_for_vertices(const struct pipe_draw_info
*info
,
325 enum pipe_prim_type prim
)
328 case PIPE_PRIM_PATCHES
:
329 return info
->count
/ info
->vertices_per_patch
;
330 case PIPE_PRIM_POLYGON
:
331 return info
->count
>= 3;
332 case SI_PRIM_RECTANGLE_LIST
:
333 return info
->count
/ 3;
335 return u_decomposed_prims_for_vertices(prim
, info
->count
);
340 si_get_init_multi_vgt_param(struct si_screen
*sscreen
,
341 union si_vgt_param_key
*key
)
343 STATIC_ASSERT(sizeof(union si_vgt_param_key
) == 4);
344 unsigned max_primgroup_in_wave
= 2;
346 /* SWITCH_ON_EOP(0) is always preferable. */
347 bool wd_switch_on_eop
= false;
348 bool ia_switch_on_eop
= false;
349 bool ia_switch_on_eoi
= false;
350 bool partial_vs_wave
= false;
351 bool partial_es_wave
= false;
353 if (key
->u
.uses_tess
) {
354 /* SWITCH_ON_EOI must be set if PrimID is used. */
355 if (key
->u
.tess_uses_prim_id
)
356 ia_switch_on_eoi
= true;
358 /* Bug with tessellation and GS on Bonaire and older 2 SE chips. */
359 if ((sscreen
->info
.family
== CHIP_TAHITI
||
360 sscreen
->info
.family
== CHIP_PITCAIRN
||
361 sscreen
->info
.family
== CHIP_BONAIRE
) &&
363 partial_vs_wave
= true;
365 /* Needed for 028B6C_DISTRIBUTION_MODE != 0. (implies >= GFX8) */
366 if (sscreen
->has_distributed_tess
) {
367 if (key
->u
.uses_gs
) {
368 if (sscreen
->info
.chip_class
== GFX8
)
369 partial_es_wave
= true;
371 partial_vs_wave
= true;
376 /* This is a hardware requirement. */
377 if (key
->u
.line_stipple_enabled
||
378 (sscreen
->debug_flags
& DBG(SWITCH_ON_EOP
))) {
379 ia_switch_on_eop
= true;
380 wd_switch_on_eop
= true;
383 if (sscreen
->info
.chip_class
>= GFX7
) {
384 /* WD_SWITCH_ON_EOP has no effect on GPUs with less than
385 * 4 shader engines. Set 1 to pass the assertion below.
386 * The other cases are hardware requirements.
388 * Polaris supports primitive restart with WD_SWITCH_ON_EOP=0
389 * for points, line strips, and tri strips.
391 if (sscreen
->info
.max_se
<= 2 ||
392 key
->u
.prim
== PIPE_PRIM_POLYGON
||
393 key
->u
.prim
== PIPE_PRIM_LINE_LOOP
||
394 key
->u
.prim
== PIPE_PRIM_TRIANGLE_FAN
||
395 key
->u
.prim
== PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY
||
396 (key
->u
.primitive_restart
&&
397 (sscreen
->info
.family
< CHIP_POLARIS10
||
398 (key
->u
.prim
!= PIPE_PRIM_POINTS
&&
399 key
->u
.prim
!= PIPE_PRIM_LINE_STRIP
&&
400 key
->u
.prim
!= PIPE_PRIM_TRIANGLE_STRIP
))) ||
401 key
->u
.count_from_stream_output
)
402 wd_switch_on_eop
= true;
404 /* Hawaii hangs if instancing is enabled and WD_SWITCH_ON_EOP is 0.
405 * We don't know that for indirect drawing, so treat it as
406 * always problematic. */
407 if (sscreen
->info
.family
== CHIP_HAWAII
&&
408 key
->u
.uses_instancing
)
409 wd_switch_on_eop
= true;
411 /* Performance recommendation for 4 SE Gfx7-8 parts if
412 * instances are smaller than a primgroup.
413 * Assume indirect draws always use small instances.
414 * This is needed for good VS wave utilization.
416 if (sscreen
->info
.chip_class
<= GFX8
&&
417 sscreen
->info
.max_se
== 4 &&
418 key
->u
.multi_instances_smaller_than_primgroup
)
419 wd_switch_on_eop
= true;
421 /* Required on GFX7 and later. */
422 if (sscreen
->info
.max_se
== 4 && !wd_switch_on_eop
)
423 ia_switch_on_eoi
= true;
425 /* HW engineers suggested that PARTIAL_VS_WAVE_ON should be set
426 * to work around a GS hang.
428 if (key
->u
.uses_gs
&&
429 (sscreen
->info
.family
== CHIP_TONGA
||
430 sscreen
->info
.family
== CHIP_FIJI
||
431 sscreen
->info
.family
== CHIP_POLARIS10
||
432 sscreen
->info
.family
== CHIP_POLARIS11
||
433 sscreen
->info
.family
== CHIP_POLARIS12
||
434 sscreen
->info
.family
== CHIP_VEGAM
))
435 partial_vs_wave
= true;
437 /* Required by Hawaii and, for some special cases, by GFX8. */
438 if (ia_switch_on_eoi
&&
439 (sscreen
->info
.family
== CHIP_HAWAII
||
440 (sscreen
->info
.chip_class
== GFX8
&&
441 (key
->u
.uses_gs
|| max_primgroup_in_wave
!= 2))))
442 partial_vs_wave
= true;
444 /* Instancing bug on Bonaire. */
445 if (sscreen
->info
.family
== CHIP_BONAIRE
&& ia_switch_on_eoi
&&
446 key
->u
.uses_instancing
)
447 partial_vs_wave
= true;
449 /* This only applies to Polaris10 and later 4 SE chips.
450 * wd_switch_on_eop is already true on all other chips.
452 if (!wd_switch_on_eop
&& key
->u
.primitive_restart
)
453 partial_vs_wave
= true;
455 /* If the WD switch is false, the IA switch must be false too. */
456 assert(wd_switch_on_eop
|| !ia_switch_on_eop
);
459 /* If SWITCH_ON_EOI is set, PARTIAL_ES_WAVE must be set too. */
460 if (sscreen
->info
.chip_class
<= GFX8
&& ia_switch_on_eoi
)
461 partial_es_wave
= true;
463 return S_028AA8_SWITCH_ON_EOP(ia_switch_on_eop
) |
464 S_028AA8_SWITCH_ON_EOI(ia_switch_on_eoi
) |
465 S_028AA8_PARTIAL_VS_WAVE_ON(partial_vs_wave
) |
466 S_028AA8_PARTIAL_ES_WAVE_ON(partial_es_wave
) |
467 S_028AA8_WD_SWITCH_ON_EOP(sscreen
->info
.chip_class
>= GFX7
? wd_switch_on_eop
: 0) |
468 /* The following field was moved to VGT_SHADER_STAGES_EN in GFX9. */
469 S_028AA8_MAX_PRIMGRP_IN_WAVE(sscreen
->info
.chip_class
== GFX8
?
470 max_primgroup_in_wave
: 0) |
471 S_030960_EN_INST_OPT_BASIC(sscreen
->info
.chip_class
>= GFX9
) |
472 S_030960_EN_INST_OPT_ADV(sscreen
->info
.chip_class
>= GFX9
);
475 static void si_init_ia_multi_vgt_param_table(struct si_context
*sctx
)
477 for (int prim
= 0; prim
<= SI_PRIM_RECTANGLE_LIST
; prim
++)
478 for (int uses_instancing
= 0; uses_instancing
< 2; uses_instancing
++)
479 for (int multi_instances
= 0; multi_instances
< 2; multi_instances
++)
480 for (int primitive_restart
= 0; primitive_restart
< 2; primitive_restart
++)
481 for (int count_from_so
= 0; count_from_so
< 2; count_from_so
++)
482 for (int line_stipple
= 0; line_stipple
< 2; line_stipple
++)
483 for (int uses_tess
= 0; uses_tess
< 2; uses_tess
++)
484 for (int tess_uses_primid
= 0; tess_uses_primid
< 2; tess_uses_primid
++)
485 for (int uses_gs
= 0; uses_gs
< 2; uses_gs
++) {
486 union si_vgt_param_key key
;
490 key
.u
.uses_instancing
= uses_instancing
;
491 key
.u
.multi_instances_smaller_than_primgroup
= multi_instances
;
492 key
.u
.primitive_restart
= primitive_restart
;
493 key
.u
.count_from_stream_output
= count_from_so
;
494 key
.u
.line_stipple_enabled
= line_stipple
;
495 key
.u
.uses_tess
= uses_tess
;
496 key
.u
.tess_uses_prim_id
= tess_uses_primid
;
497 key
.u
.uses_gs
= uses_gs
;
499 sctx
->ia_multi_vgt_param
[key
.index
] =
500 si_get_init_multi_vgt_param(sctx
->screen
, &key
);
504 static unsigned si_get_ia_multi_vgt_param(struct si_context
*sctx
,
505 const struct pipe_draw_info
*info
,
506 enum pipe_prim_type prim
,
507 unsigned num_patches
,
508 unsigned instance_count
,
509 bool primitive_restart
)
511 union si_vgt_param_key key
= sctx
->ia_multi_vgt_param_key
;
512 unsigned primgroup_size
;
513 unsigned ia_multi_vgt_param
;
515 if (sctx
->tes_shader
.cso
) {
516 primgroup_size
= num_patches
; /* must be a multiple of NUM_PATCHES */
517 } else if (sctx
->gs_shader
.cso
) {
518 primgroup_size
= 64; /* recommended with a GS */
520 primgroup_size
= 128; /* recommended without a GS and tess */
524 key
.u
.uses_instancing
= info
->indirect
|| instance_count
> 1;
525 key
.u
.multi_instances_smaller_than_primgroup
=
527 (instance_count
> 1 &&
528 (info
->count_from_stream_output
||
529 si_num_prims_for_vertices(info
, prim
) < primgroup_size
));
530 key
.u
.primitive_restart
= primitive_restart
;
531 key
.u
.count_from_stream_output
= info
->count_from_stream_output
!= NULL
;
533 ia_multi_vgt_param
= sctx
->ia_multi_vgt_param
[key
.index
] |
534 S_028AA8_PRIMGROUP_SIZE(primgroup_size
- 1);
536 if (sctx
->gs_shader
.cso
) {
537 /* GS requirement. */
538 if (sctx
->chip_class
<= GFX8
&&
539 SI_GS_PER_ES
/ primgroup_size
>= sctx
->screen
->gs_table_depth
- 3)
540 ia_multi_vgt_param
|= S_028AA8_PARTIAL_ES_WAVE_ON(1);
542 /* GS hw bug with single-primitive instances and SWITCH_ON_EOI.
543 * The hw doc says all multi-SE chips are affected, but Vulkan
544 * only applies it to Hawaii. Do what Vulkan does.
546 if (sctx
->family
== CHIP_HAWAII
&&
547 G_028AA8_SWITCH_ON_EOI(ia_multi_vgt_param
) &&
549 (instance_count
> 1 &&
550 (info
->count_from_stream_output
||
551 si_num_prims_for_vertices(info
, prim
) <= 1))))
552 sctx
->flags
|= SI_CONTEXT_VGT_FLUSH
;
555 return ia_multi_vgt_param
;
558 static unsigned si_conv_prim_to_gs_out(unsigned mode
)
560 static const int prim_conv
[] = {
561 [PIPE_PRIM_POINTS
] = V_028A6C_OUTPRIM_TYPE_POINTLIST
,
562 [PIPE_PRIM_LINES
] = V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
563 [PIPE_PRIM_LINE_LOOP
] = V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
564 [PIPE_PRIM_LINE_STRIP
] = V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
565 [PIPE_PRIM_TRIANGLES
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
566 [PIPE_PRIM_TRIANGLE_STRIP
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
567 [PIPE_PRIM_TRIANGLE_FAN
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
568 [PIPE_PRIM_QUADS
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
569 [PIPE_PRIM_QUAD_STRIP
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
570 [PIPE_PRIM_POLYGON
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
571 [PIPE_PRIM_LINES_ADJACENCY
] = V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
572 [PIPE_PRIM_LINE_STRIP_ADJACENCY
] = V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
573 [PIPE_PRIM_TRIANGLES_ADJACENCY
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
574 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
575 [PIPE_PRIM_PATCHES
] = V_028A6C_OUTPRIM_TYPE_POINTLIST
,
576 [SI_PRIM_RECTANGLE_LIST
] = V_028A6C_VGT_OUT_RECT_V0
,
578 assert(mode
< ARRAY_SIZE(prim_conv
));
580 return prim_conv
[mode
];
583 /* rast_prim is the primitive type after GS. */
584 static void si_emit_rasterizer_prim_state(struct si_context
*sctx
)
586 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
587 enum pipe_prim_type rast_prim
= sctx
->current_rast_prim
;
588 struct si_state_rasterizer
*rs
= sctx
->queued
.named
.rasterizer
;
590 if (likely(rast_prim
== sctx
->last_rast_prim
&&
591 rs
->pa_sc_line_stipple
== sctx
->last_sc_line_stipple
&&
592 (sctx
->chip_class
<= GFX9
||
593 rs
->flatshade_first
== sctx
->last_flatshade_first
)))
596 if (util_prim_is_lines(rast_prim
)) {
597 /* For lines, reset the stipple pattern at each primitive. Otherwise,
598 * reset the stipple pattern at each packet (line strips, line loops).
600 radeon_set_context_reg(cs
, R_028A0C_PA_SC_LINE_STIPPLE
,
601 rs
->pa_sc_line_stipple
|
602 S_028A0C_AUTO_RESET_CNTL(rast_prim
== PIPE_PRIM_LINES
? 1 : 2));
603 sctx
->context_roll
= true;
606 unsigned gs_out
= si_conv_prim_to_gs_out(sctx
->current_rast_prim
);
608 if (rast_prim
!= sctx
->last_rast_prim
&&
609 (sctx
->ngg
|| sctx
->gs_shader
.cso
)) {
610 radeon_set_context_reg(cs
, R_028A6C_VGT_GS_OUT_PRIM_TYPE
, gs_out
);
611 sctx
->context_roll
= true;
613 if (sctx
->chip_class
>= GFX10
) {
614 sctx
->current_vs_state
&= C_VS_STATE_OUTPRIM
;
615 sctx
->current_vs_state
|= S_VS_STATE_OUTPRIM(gs_out
);
619 if (sctx
->chip_class
>= GFX10
) {
620 unsigned vtx_index
= rs
->flatshade_first
? 0 : gs_out
;
621 sctx
->current_vs_state
&= C_VS_STATE_PROVOKING_VTX_INDEX
;
622 sctx
->current_vs_state
|= S_VS_STATE_PROVOKING_VTX_INDEX(vtx_index
);
625 sctx
->last_rast_prim
= rast_prim
;
626 sctx
->last_sc_line_stipple
= rs
->pa_sc_line_stipple
;
627 sctx
->last_flatshade_first
= rs
->flatshade_first
;
630 static void si_emit_vs_state(struct si_context
*sctx
,
631 const struct pipe_draw_info
*info
)
633 sctx
->current_vs_state
&= C_VS_STATE_INDEXED
;
634 sctx
->current_vs_state
|= S_VS_STATE_INDEXED(!!info
->index_size
);
636 if (sctx
->num_vs_blit_sgprs
) {
637 /* Re-emit the state after we leave u_blitter. */
638 sctx
->last_vs_state
= ~0;
642 if (sctx
->current_vs_state
!= sctx
->last_vs_state
) {
643 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
645 /* For the API vertex shader (VS_STATE_INDEXED, LS_OUT_*). */
646 radeon_set_sh_reg(cs
,
647 sctx
->shader_pointers
.sh_base
[PIPE_SHADER_VERTEX
] +
648 SI_SGPR_VS_STATE_BITS
* 4,
649 sctx
->current_vs_state
);
651 /* Set CLAMP_VERTEX_COLOR and OUTPRIM in the last stage
652 * before the rasterizer.
654 * For TES or the GS copy shader without NGG:
656 if (sctx
->shader_pointers
.sh_base
[PIPE_SHADER_VERTEX
] !=
657 R_00B130_SPI_SHADER_USER_DATA_VS_0
) {
658 radeon_set_sh_reg(cs
,
659 R_00B130_SPI_SHADER_USER_DATA_VS_0
+
660 SI_SGPR_VS_STATE_BITS
* 4,
661 sctx
->current_vs_state
);
665 if (sctx
->chip_class
>= GFX10
&&
666 sctx
->shader_pointers
.sh_base
[PIPE_SHADER_VERTEX
] !=
667 R_00B230_SPI_SHADER_USER_DATA_GS_0
) {
668 radeon_set_sh_reg(cs
,
669 R_00B230_SPI_SHADER_USER_DATA_GS_0
+
670 SI_SGPR_VS_STATE_BITS
* 4,
671 sctx
->current_vs_state
);
674 sctx
->last_vs_state
= sctx
->current_vs_state
;
678 static inline bool si_prim_restart_index_changed(struct si_context
*sctx
,
679 bool primitive_restart
,
680 unsigned restart_index
)
682 return primitive_restart
&&
683 (restart_index
!= sctx
->last_restart_index
||
684 sctx
->last_restart_index
== SI_RESTART_INDEX_UNKNOWN
);
687 static void si_emit_ia_multi_vgt_param(struct si_context
*sctx
,
688 const struct pipe_draw_info
*info
,
689 enum pipe_prim_type prim
,
690 unsigned num_patches
,
691 unsigned instance_count
,
692 bool primitive_restart
)
694 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
695 unsigned ia_multi_vgt_param
;
697 ia_multi_vgt_param
= si_get_ia_multi_vgt_param(sctx
, info
, prim
, num_patches
,
698 instance_count
, primitive_restart
);
701 if (ia_multi_vgt_param
!= sctx
->last_multi_vgt_param
) {
702 if (sctx
->chip_class
== GFX9
)
703 radeon_set_uconfig_reg_idx(cs
, sctx
->screen
,
704 R_030960_IA_MULTI_VGT_PARAM
, 4,
706 else if (sctx
->chip_class
>= GFX7
)
707 radeon_set_context_reg_idx(cs
, R_028AA8_IA_MULTI_VGT_PARAM
, 1, ia_multi_vgt_param
);
709 radeon_set_context_reg(cs
, R_028AA8_IA_MULTI_VGT_PARAM
, ia_multi_vgt_param
);
711 sctx
->last_multi_vgt_param
= ia_multi_vgt_param
;
715 /* GFX10 removed IA_MULTI_VGT_PARAM in exchange for GE_CNTL.
716 * We overload last_multi_vgt_param.
718 static void gfx10_emit_ge_cntl(struct si_context
*sctx
, unsigned num_patches
)
723 ge_cntl
= si_get_vs_state(sctx
)->ge_cntl
|
724 S_03096C_PACKET_TO_ONE_PA(sctx
->ia_multi_vgt_param_key
.u
.line_stipple_enabled
);
726 union si_vgt_param_key key
= sctx
->ia_multi_vgt_param_key
;
727 unsigned primgroup_size
;
728 unsigned vertgroup_size
;
730 if (sctx
->tes_shader
.cso
) {
731 primgroup_size
= num_patches
; /* must be a multiple of NUM_PATCHES */
733 } else if (sctx
->gs_shader
.cso
) {
734 unsigned vgt_gs_onchip_cntl
= sctx
->gs_shader
.current
->ctx_reg
.gs
.vgt_gs_onchip_cntl
;
735 primgroup_size
= G_028A44_GS_PRIMS_PER_SUBGRP(vgt_gs_onchip_cntl
);
736 vertgroup_size
= G_028A44_ES_VERTS_PER_SUBGRP(vgt_gs_onchip_cntl
);
738 primgroup_size
= 128; /* recommended without a GS and tess */
742 ge_cntl
= S_03096C_PRIM_GRP_SIZE(primgroup_size
) |
743 S_03096C_VERT_GRP_SIZE(vertgroup_size
) |
744 S_03096C_BREAK_WAVE_AT_EOI(key
.u
.uses_tess
&& key
.u
.tess_uses_prim_id
) |
745 S_03096C_PACKET_TO_ONE_PA(key
.u
.line_stipple_enabled
);
748 if (ge_cntl
!= sctx
->last_multi_vgt_param
) {
749 radeon_set_uconfig_reg(sctx
->gfx_cs
, R_03096C_GE_CNTL
, ge_cntl
);
750 sctx
->last_multi_vgt_param
= ge_cntl
;
754 static void si_emit_draw_registers(struct si_context
*sctx
,
755 const struct pipe_draw_info
*info
,
756 enum pipe_prim_type prim
,
757 unsigned num_patches
,
758 unsigned instance_count
,
759 bool primitive_restart
)
761 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
762 unsigned vgt_prim
= si_conv_pipe_prim(prim
);
764 if (sctx
->chip_class
>= GFX10
)
765 gfx10_emit_ge_cntl(sctx
, num_patches
);
767 si_emit_ia_multi_vgt_param(sctx
, info
, prim
, num_patches
,
768 instance_count
, primitive_restart
);
770 if (vgt_prim
!= sctx
->last_prim
) {
771 if (sctx
->chip_class
>= GFX10
)
772 radeon_set_uconfig_reg(cs
, R_030908_VGT_PRIMITIVE_TYPE
, vgt_prim
);
773 else if (sctx
->chip_class
>= GFX7
)
774 radeon_set_uconfig_reg_idx(cs
, sctx
->screen
,
775 R_030908_VGT_PRIMITIVE_TYPE
, 1, vgt_prim
);
777 radeon_set_config_reg(cs
, R_008958_VGT_PRIMITIVE_TYPE
, vgt_prim
);
779 sctx
->last_prim
= vgt_prim
;
782 /* Primitive restart. */
783 if (primitive_restart
!= sctx
->last_primitive_restart_en
) {
784 if (sctx
->chip_class
>= GFX9
)
785 radeon_set_uconfig_reg(cs
, R_03092C_VGT_MULTI_PRIM_IB_RESET_EN
,
788 radeon_set_context_reg(cs
, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN
,
791 sctx
->last_primitive_restart_en
= primitive_restart
;
794 if (si_prim_restart_index_changed(sctx
, primitive_restart
, info
->restart_index
)) {
795 radeon_set_context_reg(cs
, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX
,
796 info
->restart_index
);
797 sctx
->last_restart_index
= info
->restart_index
;
798 sctx
->context_roll
= true;
802 static void si_emit_draw_packets(struct si_context
*sctx
,
803 const struct pipe_draw_info
*info
,
804 struct pipe_resource
*indexbuf
,
806 unsigned index_offset
,
807 unsigned instance_count
,
808 bool dispatch_prim_discard_cs
,
809 unsigned original_index_size
)
811 struct pipe_draw_indirect_info
*indirect
= info
->indirect
;
812 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
813 unsigned sh_base_reg
= sctx
->shader_pointers
.sh_base
[PIPE_SHADER_VERTEX
];
814 bool render_cond_bit
= sctx
->render_cond
&& !sctx
->render_cond_force_off
;
815 uint32_t index_max_size
= 0;
816 uint64_t index_va
= 0;
818 if (info
->count_from_stream_output
) {
819 struct si_streamout_target
*t
=
820 (struct si_streamout_target
*)info
->count_from_stream_output
;
822 radeon_set_context_reg(cs
, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE
,
824 si_cp_copy_data(sctx
, sctx
->gfx_cs
,
826 R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE
>> 2,
827 COPY_DATA_SRC_MEM
, t
->buf_filled_size
,
828 t
->buf_filled_size_offset
);
833 if (index_size
!= sctx
->last_index_size
) {
837 switch (index_size
) {
839 index_type
= V_028A7C_VGT_INDEX_8
;
842 index_type
= V_028A7C_VGT_INDEX_16
|
843 (SI_BIG_ENDIAN
&& sctx
->chip_class
<= GFX7
?
844 V_028A7C_VGT_DMA_SWAP_16_BIT
: 0);
847 index_type
= V_028A7C_VGT_INDEX_32
|
848 (SI_BIG_ENDIAN
&& sctx
->chip_class
<= GFX7
?
849 V_028A7C_VGT_DMA_SWAP_32_BIT
: 0);
852 assert(!"unreachable");
856 if (sctx
->chip_class
>= GFX9
) {
857 radeon_set_uconfig_reg_idx(cs
, sctx
->screen
,
858 R_03090C_VGT_INDEX_TYPE
, 2,
861 radeon_emit(cs
, PKT3(PKT3_INDEX_TYPE
, 0, 0));
862 radeon_emit(cs
, index_type
);
865 sctx
->last_index_size
= index_size
;
868 if (original_index_size
) {
869 index_max_size
= (indexbuf
->width0
- index_offset
) /
871 index_va
= si_resource(indexbuf
)->gpu_address
+ index_offset
;
873 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
,
874 si_resource(indexbuf
),
875 RADEON_USAGE_READ
, RADEON_PRIO_INDEX_BUFFER
);
878 /* On GFX7 and later, non-indexed draws overwrite VGT_INDEX_TYPE,
879 * so the state must be re-emitted before the next indexed draw.
881 if (sctx
->chip_class
>= GFX7
)
882 sctx
->last_index_size
= -1;
886 uint64_t indirect_va
= si_resource(indirect
->buffer
)->gpu_address
;
888 assert(indirect_va
% 8 == 0);
890 si_invalidate_draw_sh_constants(sctx
);
892 radeon_emit(cs
, PKT3(PKT3_SET_BASE
, 2, 0));
894 radeon_emit(cs
, indirect_va
);
895 radeon_emit(cs
, indirect_va
>> 32);
897 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
,
898 si_resource(indirect
->buffer
),
899 RADEON_USAGE_READ
, RADEON_PRIO_DRAW_INDIRECT
);
901 unsigned di_src_sel
= index_size
? V_0287F0_DI_SRC_SEL_DMA
902 : V_0287F0_DI_SRC_SEL_AUTO_INDEX
;
904 assert(indirect
->offset
% 4 == 0);
907 radeon_emit(cs
, PKT3(PKT3_INDEX_BASE
, 1, 0));
908 radeon_emit(cs
, index_va
);
909 radeon_emit(cs
, index_va
>> 32);
911 radeon_emit(cs
, PKT3(PKT3_INDEX_BUFFER_SIZE
, 0, 0));
912 radeon_emit(cs
, index_max_size
);
915 if (!sctx
->screen
->has_draw_indirect_multi
) {
916 radeon_emit(cs
, PKT3(index_size
? PKT3_DRAW_INDEX_INDIRECT
917 : PKT3_DRAW_INDIRECT
,
918 3, render_cond_bit
));
919 radeon_emit(cs
, indirect
->offset
);
920 radeon_emit(cs
, (sh_base_reg
+ SI_SGPR_BASE_VERTEX
* 4 - SI_SH_REG_OFFSET
) >> 2);
921 radeon_emit(cs
, (sh_base_reg
+ SI_SGPR_START_INSTANCE
* 4 - SI_SH_REG_OFFSET
) >> 2);
922 radeon_emit(cs
, di_src_sel
);
924 uint64_t count_va
= 0;
926 if (indirect
->indirect_draw_count
) {
927 struct si_resource
*params_buf
=
928 si_resource(indirect
->indirect_draw_count
);
930 radeon_add_to_buffer_list(
931 sctx
, sctx
->gfx_cs
, params_buf
,
932 RADEON_USAGE_READ
, RADEON_PRIO_DRAW_INDIRECT
);
934 count_va
= params_buf
->gpu_address
+ indirect
->indirect_draw_count_offset
;
937 radeon_emit(cs
, PKT3(index_size
? PKT3_DRAW_INDEX_INDIRECT_MULTI
:
938 PKT3_DRAW_INDIRECT_MULTI
,
939 8, render_cond_bit
));
940 radeon_emit(cs
, indirect
->offset
);
941 radeon_emit(cs
, (sh_base_reg
+ SI_SGPR_BASE_VERTEX
* 4 - SI_SH_REG_OFFSET
) >> 2);
942 radeon_emit(cs
, (sh_base_reg
+ SI_SGPR_START_INSTANCE
* 4 - SI_SH_REG_OFFSET
) >> 2);
943 radeon_emit(cs
, ((sh_base_reg
+ SI_SGPR_DRAWID
* 4 - SI_SH_REG_OFFSET
) >> 2) |
944 S_2C3_DRAW_INDEX_ENABLE(1) |
945 S_2C3_COUNT_INDIRECT_ENABLE(!!indirect
->indirect_draw_count
));
946 radeon_emit(cs
, indirect
->draw_count
);
947 radeon_emit(cs
, count_va
);
948 radeon_emit(cs
, count_va
>> 32);
949 radeon_emit(cs
, indirect
->stride
);
950 radeon_emit(cs
, di_src_sel
);
955 if (sctx
->last_instance_count
== SI_INSTANCE_COUNT_UNKNOWN
||
956 sctx
->last_instance_count
!= instance_count
) {
957 radeon_emit(cs
, PKT3(PKT3_NUM_INSTANCES
, 0, 0));
958 radeon_emit(cs
, instance_count
);
959 sctx
->last_instance_count
= instance_count
;
962 /* Base vertex and start instance. */
963 base_vertex
= original_index_size
? info
->index_bias
: info
->start
;
965 if (sctx
->num_vs_blit_sgprs
) {
966 /* Re-emit draw constants after we leave u_blitter. */
967 si_invalidate_draw_sh_constants(sctx
);
969 /* Blit VS doesn't use BASE_VERTEX, START_INSTANCE, and DRAWID. */
970 radeon_set_sh_reg_seq(cs
, sh_base_reg
+ SI_SGPR_VS_BLIT_DATA
* 4,
971 sctx
->num_vs_blit_sgprs
);
972 radeon_emit_array(cs
, sctx
->vs_blit_sh_data
,
973 sctx
->num_vs_blit_sgprs
);
974 } else if (base_vertex
!= sctx
->last_base_vertex
||
975 sctx
->last_base_vertex
== SI_BASE_VERTEX_UNKNOWN
||
976 info
->start_instance
!= sctx
->last_start_instance
||
977 info
->drawid
!= sctx
->last_drawid
||
978 sh_base_reg
!= sctx
->last_sh_base_reg
) {
979 radeon_set_sh_reg_seq(cs
, sh_base_reg
+ SI_SGPR_BASE_VERTEX
* 4, 3);
980 radeon_emit(cs
, base_vertex
);
981 radeon_emit(cs
, info
->start_instance
);
982 radeon_emit(cs
, info
->drawid
);
984 sctx
->last_base_vertex
= base_vertex
;
985 sctx
->last_start_instance
= info
->start_instance
;
986 sctx
->last_drawid
= info
->drawid
;
987 sctx
->last_sh_base_reg
= sh_base_reg
;
991 if (dispatch_prim_discard_cs
) {
992 index_va
+= info
->start
* original_index_size
;
993 index_max_size
= MIN2(index_max_size
, info
->count
);
995 si_dispatch_prim_discard_cs_and_draw(sctx
, info
,
998 index_va
, index_max_size
);
1002 index_va
+= info
->start
* index_size
;
1004 radeon_emit(cs
, PKT3(PKT3_DRAW_INDEX_2
, 4, render_cond_bit
));
1005 radeon_emit(cs
, index_max_size
);
1006 radeon_emit(cs
, index_va
);
1007 radeon_emit(cs
, index_va
>> 32);
1008 radeon_emit(cs
, info
->count
);
1009 radeon_emit(cs
, V_0287F0_DI_SRC_SEL_DMA
);
1011 radeon_emit(cs
, PKT3(PKT3_DRAW_INDEX_AUTO
, 1, render_cond_bit
));
1012 radeon_emit(cs
, info
->count
);
1013 radeon_emit(cs
, V_0287F0_DI_SRC_SEL_AUTO_INDEX
|
1014 S_0287F0_USE_OPAQUE(!!info
->count_from_stream_output
));
1019 void si_emit_surface_sync(struct si_context
*sctx
, struct radeon_cmdbuf
*cs
,
1020 unsigned cp_coher_cntl
)
1022 bool compute_ib
= !sctx
->has_graphics
||
1023 cs
== sctx
->prim_discard_compute_cs
;
1025 assert(sctx
->chip_class
<= GFX9
);
1027 if (sctx
->chip_class
== GFX9
|| compute_ib
) {
1028 /* Flush caches and wait for the caches to assert idle. */
1029 radeon_emit(cs
, PKT3(PKT3_ACQUIRE_MEM
, 5, 0));
1030 radeon_emit(cs
, cp_coher_cntl
); /* CP_COHER_CNTL */
1031 radeon_emit(cs
, 0xffffffff); /* CP_COHER_SIZE */
1032 radeon_emit(cs
, 0xffffff); /* CP_COHER_SIZE_HI */
1033 radeon_emit(cs
, 0); /* CP_COHER_BASE */
1034 radeon_emit(cs
, 0); /* CP_COHER_BASE_HI */
1035 radeon_emit(cs
, 0x0000000A); /* POLL_INTERVAL */
1037 /* ACQUIRE_MEM is only required on a compute ring. */
1038 radeon_emit(cs
, PKT3(PKT3_SURFACE_SYNC
, 3, 0));
1039 radeon_emit(cs
, cp_coher_cntl
); /* CP_COHER_CNTL */
1040 radeon_emit(cs
, 0xffffffff); /* CP_COHER_SIZE */
1041 radeon_emit(cs
, 0); /* CP_COHER_BASE */
1042 radeon_emit(cs
, 0x0000000A); /* POLL_INTERVAL */
1045 /* ACQUIRE_MEM has an implicit context roll if the current context
1048 sctx
->context_roll
= true;
1051 void si_prim_discard_signal_next_compute_ib_start(struct si_context
*sctx
)
1053 if (!si_compute_prim_discard_enabled(sctx
))
1056 if (!sctx
->barrier_buf
) {
1057 u_suballocator_alloc(sctx
->allocator_zeroed_memory
, 4, 4,
1058 &sctx
->barrier_buf_offset
,
1059 (struct pipe_resource
**)&sctx
->barrier_buf
);
1062 /* Emit a placeholder to signal the next compute IB to start.
1063 * See si_compute_prim_discard.c for explanation.
1065 uint32_t signal
= 1;
1066 si_cp_write_data(sctx
, sctx
->barrier_buf
, sctx
->barrier_buf_offset
,
1067 4, V_370_MEM
, V_370_ME
, &signal
);
1069 sctx
->last_pkt3_write_data
=
1070 &sctx
->gfx_cs
->current
.buf
[sctx
->gfx_cs
->current
.cdw
- 5];
1072 /* Only the last occurence of WRITE_DATA will be executed.
1073 * The packet will be enabled in si_flush_gfx_cs.
1075 *sctx
->last_pkt3_write_data
= PKT3(PKT3_NOP
, 3, 0);
1078 void gfx10_emit_cache_flush(struct si_context
*ctx
)
1080 struct radeon_cmdbuf
*cs
= ctx
->gfx_cs
;
1081 uint32_t gcr_cntl
= 0;
1082 unsigned cb_db_event
= 0;
1083 unsigned flags
= ctx
->flags
;
1085 if (!ctx
->has_graphics
) {
1086 /* Only process compute flags. */
1087 flags
&= SI_CONTEXT_INV_ICACHE
|
1088 SI_CONTEXT_INV_SCACHE
|
1089 SI_CONTEXT_INV_VCACHE
|
1092 SI_CONTEXT_INV_L2_METADATA
|
1093 SI_CONTEXT_CS_PARTIAL_FLUSH
;
1096 /* We don't need these. */
1097 assert(!(flags
& (SI_CONTEXT_VGT_FLUSH
|
1098 SI_CONTEXT_VGT_STREAMOUT_SYNC
|
1099 SI_CONTEXT_FLUSH_AND_INV_DB_META
)));
1101 if (flags
& SI_CONTEXT_FLUSH_AND_INV_CB
)
1102 ctx
->num_cb_cache_flushes
++;
1103 if (flags
& SI_CONTEXT_FLUSH_AND_INV_DB
)
1104 ctx
->num_db_cache_flushes
++;
1106 if (flags
& SI_CONTEXT_INV_ICACHE
)
1107 gcr_cntl
|= S_586_GLI_INV(V_586_GLI_ALL
);
1108 if (flags
& SI_CONTEXT_INV_SCACHE
) {
1109 /* TODO: When writing to the SMEM L1 cache, we need to set SEQ
1110 * to FORWARD when both L1 and L2 are written out (WB or INV).
1112 gcr_cntl
|= S_586_GL1_INV(1) | S_586_GLK_INV(1);
1114 if (flags
& SI_CONTEXT_INV_VCACHE
)
1115 gcr_cntl
|= S_586_GL1_INV(1) | S_586_GLV_INV(1);
1116 if (flags
& SI_CONTEXT_INV_L2
) {
1117 /* Writeback and invalidate everything in L2. */
1118 gcr_cntl
|= S_586_GL2_INV(1) | S_586_GLM_INV(1);
1119 ctx
->num_L2_invalidates
++;
1120 } else if (flags
& SI_CONTEXT_WB_L2
) {
1121 /* Writeback but do not invalidate. */
1122 gcr_cntl
|= S_586_GL2_WB(1);
1124 if (flags
& SI_CONTEXT_INV_L2_METADATA
)
1125 gcr_cntl
|= S_586_GLM_INV(1);
1127 if (flags
& (SI_CONTEXT_FLUSH_AND_INV_CB
| SI_CONTEXT_FLUSH_AND_INV_DB
)) {
1128 if (flags
& SI_CONTEXT_FLUSH_AND_INV_CB
) {
1129 /* Flush CMASK/FMASK/DCC. Will wait for idle later. */
1130 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
1131 radeon_emit(cs
, EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_META
) |
1134 if (flags
& SI_CONTEXT_FLUSH_AND_INV_DB
) {
1135 /* Flush HTILE. Will wait for idle later. */
1136 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
1137 radeon_emit(cs
, EVENT_TYPE(V_028A90_FLUSH_AND_INV_DB_META
) |
1141 /* First flush CB/DB, then L1/L2. */
1142 gcr_cntl
|= S_586_SEQ(V_586_SEQ_FORWARD
);
1144 if ((flags
& (SI_CONTEXT_FLUSH_AND_INV_CB
| SI_CONTEXT_FLUSH_AND_INV_DB
)) ==
1145 (SI_CONTEXT_FLUSH_AND_INV_CB
| SI_CONTEXT_FLUSH_AND_INV_DB
)) {
1146 cb_db_event
= V_028A90_CACHE_FLUSH_AND_INV_TS_EVENT
;
1147 } else if (flags
& SI_CONTEXT_FLUSH_AND_INV_CB
) {
1148 cb_db_event
= V_028A90_FLUSH_AND_INV_CB_DATA_TS
;
1149 } else if (flags
& SI_CONTEXT_FLUSH_AND_INV_DB
) {
1150 cb_db_event
= V_028A90_FLUSH_AND_INV_DB_DATA_TS
;
1155 /* Wait for graphics shaders to go idle if requested. */
1156 if (flags
& SI_CONTEXT_PS_PARTIAL_FLUSH
) {
1157 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
1158 radeon_emit(cs
, EVENT_TYPE(V_028A90_PS_PARTIAL_FLUSH
) | EVENT_INDEX(4));
1159 /* Only count explicit shader flushes, not implicit ones. */
1160 ctx
->num_vs_flushes
++;
1161 ctx
->num_ps_flushes
++;
1162 } else if (flags
& SI_CONTEXT_VS_PARTIAL_FLUSH
) {
1163 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
1164 radeon_emit(cs
, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH
) | EVENT_INDEX(4));
1165 ctx
->num_vs_flushes
++;
1169 if (flags
& SI_CONTEXT_CS_PARTIAL_FLUSH
&& ctx
->compute_is_busy
) {
1170 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
1171 radeon_emit(cs
, EVENT_TYPE(V_028A90_CS_PARTIAL_FLUSH
| EVENT_INDEX(4)));
1172 ctx
->num_cs_flushes
++;
1173 ctx
->compute_is_busy
= false;
1177 /* CB/DB flush and invalidate (or possibly just a wait for a
1178 * meta flush) via RELEASE_MEM.
1180 * Combine this with other cache flushes when possible; this
1181 * requires affected shaders to be idle, so do it after the
1182 * CS_PARTIAL_FLUSH before (VS/PS partial flushes are always
1187 /* Do the flush (enqueue the event and wait for it). */
1188 va
= ctx
->wait_mem_scratch
->gpu_address
;
1189 ctx
->wait_mem_number
++;
1191 /* Get GCR_CNTL fields, because the encoding is different in RELEASE_MEM. */
1192 unsigned glm_wb
= G_586_GLM_WB(gcr_cntl
);
1193 unsigned glm_inv
= G_586_GLM_INV(gcr_cntl
);
1194 unsigned glv_inv
= G_586_GLV_INV(gcr_cntl
);
1195 unsigned gl1_inv
= G_586_GL1_INV(gcr_cntl
);
1196 assert(G_586_GL2_US(gcr_cntl
) == 0);
1197 assert(G_586_GL2_RANGE(gcr_cntl
) == 0);
1198 assert(G_586_GL2_DISCARD(gcr_cntl
) == 0);
1199 unsigned gl2_inv
= G_586_GL2_INV(gcr_cntl
);
1200 unsigned gl2_wb
= G_586_GL2_WB(gcr_cntl
);
1201 unsigned gcr_seq
= G_586_SEQ(gcr_cntl
);
1203 gcr_cntl
&= C_586_GLM_WB
&
1208 C_586_GL2_WB
; /* keep SEQ */
1210 si_cp_release_mem(ctx
, cs
, cb_db_event
,
1211 S_490_GLM_WB(glm_wb
) |
1212 S_490_GLM_INV(glm_inv
) |
1213 S_490_GLV_INV(glv_inv
) |
1214 S_490_GL1_INV(gl1_inv
) |
1215 S_490_GL2_INV(gl2_inv
) |
1216 S_490_GL2_WB(gl2_wb
) |
1219 EOP_INT_SEL_SEND_DATA_AFTER_WR_CONFIRM
,
1220 EOP_DATA_SEL_VALUE_32BIT
,
1221 ctx
->wait_mem_scratch
, va
,
1222 ctx
->wait_mem_number
, SI_NOT_QUERY
);
1223 si_cp_wait_mem(ctx
, ctx
->gfx_cs
, va
, ctx
->wait_mem_number
, 0xffffffff,
1224 WAIT_REG_MEM_EQUAL
);
1227 /* Ignore fields that only modify the behavior of other fields. */
1228 if (gcr_cntl
& C_586_GL1_RANGE
& C_586_GL2_RANGE
& C_586_SEQ
) {
1229 /* Flush caches and wait for the caches to assert idle.
1230 * The cache flush is executed in the ME, but the PFP waits
1233 radeon_emit(cs
, PKT3(PKT3_ACQUIRE_MEM
, 6, 0));
1234 radeon_emit(cs
, 0); /* CP_COHER_CNTL */
1235 radeon_emit(cs
, 0xffffffff); /* CP_COHER_SIZE */
1236 radeon_emit(cs
, 0xffffff); /* CP_COHER_SIZE_HI */
1237 radeon_emit(cs
, 0); /* CP_COHER_BASE */
1238 radeon_emit(cs
, 0); /* CP_COHER_BASE_HI */
1239 radeon_emit(cs
, 0x0000000A); /* POLL_INTERVAL */
1240 radeon_emit(cs
, gcr_cntl
); /* GCR_CNTL */
1241 } else if (cb_db_event
||
1242 (flags
& (SI_CONTEXT_VS_PARTIAL_FLUSH
|
1243 SI_CONTEXT_PS_PARTIAL_FLUSH
|
1244 SI_CONTEXT_CS_PARTIAL_FLUSH
))) {
1245 /* We need to ensure that PFP waits as well. */
1246 radeon_emit(cs
, PKT3(PKT3_PFP_SYNC_ME
, 0, 0));
1250 if (flags
& SI_CONTEXT_START_PIPELINE_STATS
) {
1251 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
1252 radeon_emit(cs
, EVENT_TYPE(V_028A90_PIPELINESTAT_START
) |
1254 } else if (flags
& SI_CONTEXT_STOP_PIPELINE_STATS
) {
1255 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
1256 radeon_emit(cs
, EVENT_TYPE(V_028A90_PIPELINESTAT_STOP
) |
1263 void si_emit_cache_flush(struct si_context
*sctx
)
1265 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
1266 uint32_t flags
= sctx
->flags
;
1268 if (!sctx
->has_graphics
) {
1269 /* Only process compute flags. */
1270 flags
&= SI_CONTEXT_INV_ICACHE
|
1271 SI_CONTEXT_INV_SCACHE
|
1272 SI_CONTEXT_INV_VCACHE
|
1275 SI_CONTEXT_INV_L2_METADATA
|
1276 SI_CONTEXT_CS_PARTIAL_FLUSH
;
1279 uint32_t cp_coher_cntl
= 0;
1280 const uint32_t flush_cb_db
= flags
& (SI_CONTEXT_FLUSH_AND_INV_CB
|
1281 SI_CONTEXT_FLUSH_AND_INV_DB
);
1282 const bool is_barrier
= flush_cb_db
||
1283 /* INV_ICACHE == beginning of gfx IB. Checking
1284 * INV_ICACHE fixes corruption for DeusExMD with
1285 * compute-based culling, but I don't know why.
1287 flags
& (SI_CONTEXT_INV_ICACHE
|
1288 SI_CONTEXT_PS_PARTIAL_FLUSH
|
1289 SI_CONTEXT_VS_PARTIAL_FLUSH
) ||
1290 (flags
& SI_CONTEXT_CS_PARTIAL_FLUSH
&&
1291 sctx
->compute_is_busy
);
1293 assert(sctx
->chip_class
<= GFX9
);
1295 if (flags
& SI_CONTEXT_FLUSH_AND_INV_CB
)
1296 sctx
->num_cb_cache_flushes
++;
1297 if (flags
& SI_CONTEXT_FLUSH_AND_INV_DB
)
1298 sctx
->num_db_cache_flushes
++;
1300 /* GFX6 has a bug that it always flushes ICACHE and KCACHE if either
1301 * bit is set. An alternative way is to write SQC_CACHES, but that
1302 * doesn't seem to work reliably. Since the bug doesn't affect
1303 * correctness (it only does more work than necessary) and
1304 * the performance impact is likely negligible, there is no plan
1305 * to add a workaround for it.
1308 if (flags
& SI_CONTEXT_INV_ICACHE
)
1309 cp_coher_cntl
|= S_0085F0_SH_ICACHE_ACTION_ENA(1);
1310 if (flags
& SI_CONTEXT_INV_SCACHE
)
1311 cp_coher_cntl
|= S_0085F0_SH_KCACHE_ACTION_ENA(1);
1313 if (sctx
->chip_class
<= GFX8
) {
1314 if (flags
& SI_CONTEXT_FLUSH_AND_INV_CB
) {
1315 cp_coher_cntl
|= S_0085F0_CB_ACTION_ENA(1) |
1316 S_0085F0_CB0_DEST_BASE_ENA(1) |
1317 S_0085F0_CB1_DEST_BASE_ENA(1) |
1318 S_0085F0_CB2_DEST_BASE_ENA(1) |
1319 S_0085F0_CB3_DEST_BASE_ENA(1) |
1320 S_0085F0_CB4_DEST_BASE_ENA(1) |
1321 S_0085F0_CB5_DEST_BASE_ENA(1) |
1322 S_0085F0_CB6_DEST_BASE_ENA(1) |
1323 S_0085F0_CB7_DEST_BASE_ENA(1);
1325 /* Necessary for DCC */
1326 if (sctx
->chip_class
== GFX8
)
1327 si_cp_release_mem(sctx
, cs
,
1328 V_028A90_FLUSH_AND_INV_CB_DATA_TS
,
1329 0, EOP_DST_SEL_MEM
, EOP_INT_SEL_NONE
,
1330 EOP_DATA_SEL_DISCARD
, NULL
,
1331 0, 0, SI_NOT_QUERY
);
1333 if (flags
& SI_CONTEXT_FLUSH_AND_INV_DB
)
1334 cp_coher_cntl
|= S_0085F0_DB_ACTION_ENA(1) |
1335 S_0085F0_DB_DEST_BASE_ENA(1);
1338 if (flags
& SI_CONTEXT_FLUSH_AND_INV_CB
) {
1339 /* Flush CMASK/FMASK/DCC. SURFACE_SYNC will wait for idle. */
1340 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
1341 radeon_emit(cs
, EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_META
) | EVENT_INDEX(0));
1343 if (flags
& (SI_CONTEXT_FLUSH_AND_INV_DB
|
1344 SI_CONTEXT_FLUSH_AND_INV_DB_META
)) {
1345 /* Flush HTILE. SURFACE_SYNC will wait for idle. */
1346 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
1347 radeon_emit(cs
, EVENT_TYPE(V_028A90_FLUSH_AND_INV_DB_META
) | EVENT_INDEX(0));
1350 /* Wait for shader engines to go idle.
1351 * VS and PS waits are unnecessary if SURFACE_SYNC is going to wait
1352 * for everything including CB/DB cache flushes.
1355 if (flags
& SI_CONTEXT_PS_PARTIAL_FLUSH
) {
1356 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
1357 radeon_emit(cs
, EVENT_TYPE(V_028A90_PS_PARTIAL_FLUSH
) | EVENT_INDEX(4));
1358 /* Only count explicit shader flushes, not implicit ones
1359 * done by SURFACE_SYNC.
1361 sctx
->num_vs_flushes
++;
1362 sctx
->num_ps_flushes
++;
1363 } else if (flags
& SI_CONTEXT_VS_PARTIAL_FLUSH
) {
1364 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
1365 radeon_emit(cs
, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH
) | EVENT_INDEX(4));
1366 sctx
->num_vs_flushes
++;
1370 if (flags
& SI_CONTEXT_CS_PARTIAL_FLUSH
&&
1371 sctx
->compute_is_busy
) {
1372 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
1373 radeon_emit(cs
, EVENT_TYPE(V_028A90_CS_PARTIAL_FLUSH
) | EVENT_INDEX(4));
1374 sctx
->num_cs_flushes
++;
1375 sctx
->compute_is_busy
= false;
1378 /* VGT state synchronization. */
1379 if (flags
& SI_CONTEXT_VGT_FLUSH
) {
1380 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
1381 radeon_emit(cs
, EVENT_TYPE(V_028A90_VGT_FLUSH
) | EVENT_INDEX(0));
1383 if (flags
& SI_CONTEXT_VGT_STREAMOUT_SYNC
) {
1384 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
1385 radeon_emit(cs
, EVENT_TYPE(V_028A90_VGT_STREAMOUT_SYNC
) | EVENT_INDEX(0));
1388 /* GFX9: Wait for idle if we're flushing CB or DB. ACQUIRE_MEM doesn't
1389 * wait for idle on GFX9. We have to use a TS event.
1391 if (sctx
->chip_class
== GFX9
&& flush_cb_db
) {
1393 unsigned tc_flags
, cb_db_event
;
1395 /* Set the CB/DB flush event. */
1396 switch (flush_cb_db
) {
1397 case SI_CONTEXT_FLUSH_AND_INV_CB
:
1398 cb_db_event
= V_028A90_FLUSH_AND_INV_CB_DATA_TS
;
1400 case SI_CONTEXT_FLUSH_AND_INV_DB
:
1401 cb_db_event
= V_028A90_FLUSH_AND_INV_DB_DATA_TS
;
1405 cb_db_event
= V_028A90_CACHE_FLUSH_AND_INV_TS_EVENT
;
1408 /* These are the only allowed combinations. If you need to
1409 * do multiple operations at once, do them separately.
1410 * All operations that invalidate L2 also seem to invalidate
1411 * metadata. Volatile (VOL) and WC flushes are not listed here.
1413 * TC | TC_WB = writeback & invalidate L2 & L1
1414 * TC | TC_WB | TC_NC = writeback & invalidate L2 for MTYPE == NC
1415 * TC_WB | TC_NC = writeback L2 for MTYPE == NC
1416 * TC | TC_NC = invalidate L2 for MTYPE == NC
1417 * TC | TC_MD = writeback & invalidate L2 metadata (DCC, etc.)
1418 * TCL1 = invalidate L1
1422 if (flags
& SI_CONTEXT_INV_L2_METADATA
) {
1423 tc_flags
= EVENT_TC_ACTION_ENA
|
1424 EVENT_TC_MD_ACTION_ENA
;
1427 /* Ideally flush TC together with CB/DB. */
1428 if (flags
& SI_CONTEXT_INV_L2
) {
1429 /* Writeback and invalidate everything in L2 & L1. */
1430 tc_flags
= EVENT_TC_ACTION_ENA
|
1431 EVENT_TC_WB_ACTION_ENA
;
1433 /* Clear the flags. */
1434 flags
&= ~(SI_CONTEXT_INV_L2
|
1436 SI_CONTEXT_INV_VCACHE
);
1437 sctx
->num_L2_invalidates
++;
1440 /* Do the flush (enqueue the event and wait for it). */
1441 va
= sctx
->wait_mem_scratch
->gpu_address
;
1442 sctx
->wait_mem_number
++;
1444 si_cp_release_mem(sctx
, cs
, cb_db_event
, tc_flags
,
1446 EOP_INT_SEL_SEND_DATA_AFTER_WR_CONFIRM
,
1447 EOP_DATA_SEL_VALUE_32BIT
,
1448 sctx
->wait_mem_scratch
, va
,
1449 sctx
->wait_mem_number
, SI_NOT_QUERY
);
1450 si_cp_wait_mem(sctx
, cs
, va
, sctx
->wait_mem_number
, 0xffffffff,
1451 WAIT_REG_MEM_EQUAL
);
1454 /* Make sure ME is idle (it executes most packets) before continuing.
1455 * This prevents read-after-write hazards between PFP and ME.
1457 if (sctx
->has_graphics
&&
1459 (flags
& (SI_CONTEXT_CS_PARTIAL_FLUSH
|
1460 SI_CONTEXT_INV_VCACHE
|
1462 SI_CONTEXT_WB_L2
)))) {
1463 radeon_emit(cs
, PKT3(PKT3_PFP_SYNC_ME
, 0, 0));
1468 * When one of the CP_COHER_CNTL.DEST_BASE flags is set, SURFACE_SYNC
1469 * waits for idle, so it should be last. SURFACE_SYNC is done in PFP.
1471 * cp_coher_cntl should contain all necessary flags except TC flags
1474 * GFX6-GFX7 don't support L2 write-back.
1476 if (flags
& SI_CONTEXT_INV_L2
||
1477 (sctx
->chip_class
<= GFX7
&&
1478 (flags
& SI_CONTEXT_WB_L2
))) {
1479 /* Invalidate L1 & L2. (L1 is always invalidated on GFX6)
1480 * WB must be set on GFX8+ when TC_ACTION is set.
1482 si_emit_surface_sync(sctx
, sctx
->gfx_cs
, cp_coher_cntl
|
1483 S_0085F0_TC_ACTION_ENA(1) |
1484 S_0085F0_TCL1_ACTION_ENA(1) |
1485 S_0301F0_TC_WB_ACTION_ENA(sctx
->chip_class
>= GFX8
));
1487 sctx
->num_L2_invalidates
++;
1489 /* L1 invalidation and L2 writeback must be done separately,
1490 * because both operations can't be done together.
1492 if (flags
& SI_CONTEXT_WB_L2
) {
1494 * NC = apply to non-coherent MTYPEs
1495 * (i.e. MTYPE <= 1, which is what we use everywhere)
1497 * WB doesn't work without NC.
1499 si_emit_surface_sync(sctx
, sctx
->gfx_cs
, cp_coher_cntl
|
1500 S_0301F0_TC_WB_ACTION_ENA(1) |
1501 S_0301F0_TC_NC_ACTION_ENA(1));
1503 sctx
->num_L2_writebacks
++;
1505 if (flags
& SI_CONTEXT_INV_VCACHE
) {
1506 /* Invalidate per-CU VMEM L1. */
1507 si_emit_surface_sync(sctx
, sctx
->gfx_cs
, cp_coher_cntl
|
1508 S_0085F0_TCL1_ACTION_ENA(1));
1513 /* If TC flushes haven't cleared this... */
1515 si_emit_surface_sync(sctx
, sctx
->gfx_cs
, cp_coher_cntl
);
1518 si_prim_discard_signal_next_compute_ib_start(sctx
);
1520 if (flags
& SI_CONTEXT_START_PIPELINE_STATS
) {
1521 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
1522 radeon_emit(cs
, EVENT_TYPE(V_028A90_PIPELINESTAT_START
) |
1524 } else if (flags
& SI_CONTEXT_STOP_PIPELINE_STATS
) {
1525 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
1526 radeon_emit(cs
, EVENT_TYPE(V_028A90_PIPELINESTAT_STOP
) |
1533 static void si_get_draw_start_count(struct si_context
*sctx
,
1534 const struct pipe_draw_info
*info
,
1535 unsigned *start
, unsigned *count
)
1537 struct pipe_draw_indirect_info
*indirect
= info
->indirect
;
1540 unsigned indirect_count
;
1541 struct pipe_transfer
*transfer
;
1542 unsigned begin
, end
;
1546 if (indirect
->indirect_draw_count
) {
1547 data
= pipe_buffer_map_range(&sctx
->b
,
1548 indirect
->indirect_draw_count
,
1549 indirect
->indirect_draw_count_offset
,
1551 PIPE_TRANSFER_READ
, &transfer
);
1553 indirect_count
= *data
;
1555 pipe_buffer_unmap(&sctx
->b
, transfer
);
1557 indirect_count
= indirect
->draw_count
;
1560 if (!indirect_count
) {
1561 *start
= *count
= 0;
1565 map_size
= (indirect_count
- 1) * indirect
->stride
+ 3 * sizeof(unsigned);
1566 data
= pipe_buffer_map_range(&sctx
->b
, indirect
->buffer
,
1567 indirect
->offset
, map_size
,
1568 PIPE_TRANSFER_READ
, &transfer
);
1573 for (unsigned i
= 0; i
< indirect_count
; ++i
) {
1574 unsigned count
= data
[0];
1575 unsigned start
= data
[2];
1578 begin
= MIN2(begin
, start
);
1579 end
= MAX2(end
, start
+ count
);
1582 data
+= indirect
->stride
/ sizeof(unsigned);
1585 pipe_buffer_unmap(&sctx
->b
, transfer
);
1589 *count
= end
- begin
;
1591 *start
= *count
= 0;
1594 *start
= info
->start
;
1595 *count
= info
->count
;
1599 static void si_emit_all_states(struct si_context
*sctx
, const struct pipe_draw_info
*info
,
1600 enum pipe_prim_type prim
, unsigned instance_count
,
1601 bool primitive_restart
, unsigned skip_atom_mask
)
1603 unsigned num_patches
= 0;
1605 si_emit_rasterizer_prim_state(sctx
);
1606 if (sctx
->tes_shader
.cso
)
1607 si_emit_derived_tess_state(sctx
, info
, &num_patches
);
1609 /* Emit state atoms. */
1610 unsigned mask
= sctx
->dirty_atoms
& ~skip_atom_mask
;
1612 sctx
->atoms
.array
[u_bit_scan(&mask
)].emit(sctx
);
1614 sctx
->dirty_atoms
&= skip_atom_mask
;
1617 mask
= sctx
->dirty_states
;
1619 unsigned i
= u_bit_scan(&mask
);
1620 struct si_pm4_state
*state
= sctx
->queued
.array
[i
];
1622 if (!state
|| sctx
->emitted
.array
[i
] == state
)
1625 si_pm4_emit(sctx
, state
);
1626 sctx
->emitted
.array
[i
] = state
;
1628 sctx
->dirty_states
= 0;
1630 /* Emit draw states. */
1631 si_emit_vs_state(sctx
, info
);
1632 si_emit_draw_registers(sctx
, info
, prim
, num_patches
, instance_count
,
1637 si_all_vs_resources_read_only(struct si_context
*sctx
,
1638 struct pipe_resource
*indexbuf
)
1640 struct radeon_winsys
*ws
= sctx
->ws
;
1641 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
1645 ws
->cs_is_buffer_referenced(cs
, si_resource(indexbuf
)->buf
,
1646 RADEON_USAGE_WRITE
))
1647 goto has_write_reference
;
1649 /* Vertex buffers. */
1650 struct si_vertex_elements
*velems
= sctx
->vertex_elements
;
1651 unsigned num_velems
= velems
->count
;
1653 for (unsigned i
= 0; i
< num_velems
; i
++) {
1654 if (!((1 << i
) & velems
->first_vb_use_mask
))
1657 unsigned vb_index
= velems
->vertex_buffer_index
[i
];
1658 struct pipe_resource
*res
= sctx
->vertex_buffer
[vb_index
].buffer
.resource
;
1662 if (ws
->cs_is_buffer_referenced(cs
, si_resource(res
)->buf
,
1663 RADEON_USAGE_WRITE
))
1664 goto has_write_reference
;
1667 /* Constant and shader buffers. */
1668 struct si_descriptors
*buffers
=
1669 &sctx
->descriptors
[si_const_and_shader_buffer_descriptors_idx(PIPE_SHADER_VERTEX
)];
1670 for (unsigned i
= 0; i
< buffers
->num_active_slots
; i
++) {
1671 unsigned index
= buffers
->first_active_slot
+ i
;
1672 struct pipe_resource
*res
=
1673 sctx
->const_and_shader_buffers
[PIPE_SHADER_VERTEX
].buffers
[index
];
1677 if (ws
->cs_is_buffer_referenced(cs
, si_resource(res
)->buf
,
1678 RADEON_USAGE_WRITE
))
1679 goto has_write_reference
;
1683 struct si_shader_selector
*vs
= sctx
->vs_shader
.cso
;
1684 if (vs
->info
.samplers_declared
) {
1685 unsigned num_samplers
= util_last_bit(vs
->info
.samplers_declared
);
1687 for (unsigned i
= 0; i
< num_samplers
; i
++) {
1688 struct pipe_sampler_view
*view
= sctx
->samplers
[PIPE_SHADER_VERTEX
].views
[i
];
1692 if (ws
->cs_is_buffer_referenced(cs
,
1693 si_resource(view
->texture
)->buf
,
1694 RADEON_USAGE_WRITE
))
1695 goto has_write_reference
;
1700 if (vs
->info
.images_declared
) {
1701 unsigned num_images
= util_last_bit(vs
->info
.images_declared
);
1703 for (unsigned i
= 0; i
< num_images
; i
++) {
1704 struct pipe_resource
*res
= sctx
->images
[PIPE_SHADER_VERTEX
].views
[i
].resource
;
1708 if (ws
->cs_is_buffer_referenced(cs
, si_resource(res
)->buf
,
1709 RADEON_USAGE_WRITE
))
1710 goto has_write_reference
;
1716 has_write_reference
:
1717 /* If the current gfx IB has enough packets, flush it to remove write
1718 * references to buffers.
1720 if (cs
->prev_dw
+ cs
->current
.cdw
> 2048) {
1721 si_flush_gfx_cs(sctx
, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW
, NULL
);
1722 assert(si_all_vs_resources_read_only(sctx
, indexbuf
));
1728 static ALWAYS_INLINE
bool pd_msg(const char *s
)
1730 if (SI_PRIM_DISCARD_DEBUG
)
1731 printf("PD failed: %s\n", s
);
1735 static void si_draw_vbo(struct pipe_context
*ctx
, const struct pipe_draw_info
*info
)
1737 struct si_context
*sctx
= (struct si_context
*)ctx
;
1738 struct si_state_rasterizer
*rs
= sctx
->queued
.named
.rasterizer
;
1739 struct pipe_resource
*indexbuf
= info
->index
.resource
;
1740 unsigned dirty_tex_counter
, dirty_buf_counter
;
1741 enum pipe_prim_type rast_prim
, prim
= info
->mode
;
1742 unsigned index_size
= info
->index_size
;
1743 unsigned index_offset
= info
->indirect
? info
->start
* index_size
: 0;
1744 unsigned instance_count
= info
->instance_count
;
1745 bool primitive_restart
= info
->primitive_restart
&&
1746 (!sctx
->screen
->options
.prim_restart_tri_strips_only
||
1747 (prim
!= PIPE_PRIM_TRIANGLE_STRIP
&&
1748 prim
!= PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY
));
1750 if (likely(!info
->indirect
)) {
1751 /* GFX6-GFX7 treat instance_count==0 as instance_count==1. There is
1752 * no workaround for indirect draws, but we can at least skip
1755 if (unlikely(!instance_count
))
1758 /* Handle count == 0. */
1759 if (unlikely(!info
->count
&&
1760 (index_size
|| !info
->count_from_stream_output
)))
1764 if (unlikely(!sctx
->vs_shader
.cso
||
1766 (!sctx
->ps_shader
.cso
&& !rs
->rasterizer_discard
) ||
1767 (!!sctx
->tes_shader
.cso
!= (prim
== PIPE_PRIM_PATCHES
)))) {
1772 /* Recompute and re-emit the texture resource states if needed. */
1773 dirty_tex_counter
= p_atomic_read(&sctx
->screen
->dirty_tex_counter
);
1774 if (unlikely(dirty_tex_counter
!= sctx
->last_dirty_tex_counter
)) {
1775 sctx
->last_dirty_tex_counter
= dirty_tex_counter
;
1776 sctx
->framebuffer
.dirty_cbufs
|=
1777 ((1 << sctx
->framebuffer
.state
.nr_cbufs
) - 1);
1778 sctx
->framebuffer
.dirty_zsbuf
= true;
1779 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.framebuffer
);
1780 si_update_all_texture_descriptors(sctx
);
1783 dirty_buf_counter
= p_atomic_read(&sctx
->screen
->dirty_buf_counter
);
1784 if (unlikely(dirty_buf_counter
!= sctx
->last_dirty_buf_counter
)) {
1785 sctx
->last_dirty_buf_counter
= dirty_buf_counter
;
1786 /* Rebind all buffers unconditionally. */
1787 si_rebind_buffer(sctx
, NULL
);
1790 si_decompress_textures(sctx
, u_bit_consecutive(0, SI_NUM_GRAPHICS_SHADERS
));
1792 /* Set the rasterization primitive type.
1794 * This must be done after si_decompress_textures, which can call
1795 * draw_vbo recursively, and before si_update_shaders, which uses
1796 * current_rast_prim for this draw_vbo call. */
1797 if (sctx
->gs_shader
.cso
) {
1798 /* Only possibilities: POINTS, LINE_STRIP, TRIANGLES */
1799 rast_prim
= sctx
->gs_shader
.cso
->rast_prim
;
1800 } else if (sctx
->tes_shader
.cso
) {
1801 /* Only possibilities: POINTS, LINE_STRIP, TRIANGLES */
1802 rast_prim
= sctx
->tes_shader
.cso
->rast_prim
;
1803 } else if (util_rast_prim_is_triangles(prim
)) {
1804 rast_prim
= PIPE_PRIM_TRIANGLES
;
1806 /* Only possibilities, POINTS, LINE*, RECTANGLES */
1810 if (rast_prim
!= sctx
->current_rast_prim
) {
1811 if (util_prim_is_points_or_lines(sctx
->current_rast_prim
) !=
1812 util_prim_is_points_or_lines(rast_prim
))
1813 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.guardband
);
1815 sctx
->current_rast_prim
= rast_prim
;
1816 sctx
->do_update_shaders
= true;
1819 if (sctx
->tes_shader
.cso
&&
1820 sctx
->screen
->has_ls_vgpr_init_bug
) {
1821 /* Determine whether the LS VGPR fix should be applied.
1823 * It is only required when num input CPs > num output CPs,
1824 * which cannot happen with the fixed function TCS. We should
1825 * also update this bit when switching from TCS to fixed
1828 struct si_shader_selector
*tcs
= sctx
->tcs_shader
.cso
;
1831 info
->vertices_per_patch
>
1832 tcs
->info
.properties
[TGSI_PROPERTY_TCS_VERTICES_OUT
];
1834 if (ls_vgpr_fix
!= sctx
->ls_vgpr_fix
) {
1835 sctx
->ls_vgpr_fix
= ls_vgpr_fix
;
1836 sctx
->do_update_shaders
= true;
1840 if (sctx
->chip_class
<= GFX9
&& sctx
->gs_shader
.cso
) {
1841 /* Determine whether the GS triangle strip adjacency fix should
1842 * be applied. Rotate every other triangle if
1843 * - triangle strips with adjacency are fed to the GS and
1844 * - primitive restart is disabled (the rotation doesn't help
1845 * when the restart occurs after an odd number of triangles).
1847 bool gs_tri_strip_adj_fix
=
1848 !sctx
->tes_shader
.cso
&&
1849 prim
== PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY
&&
1852 if (gs_tri_strip_adj_fix
!= sctx
->gs_tri_strip_adj_fix
) {
1853 sctx
->gs_tri_strip_adj_fix
= gs_tri_strip_adj_fix
;
1854 sctx
->do_update_shaders
= true;
1859 /* Translate or upload, if needed. */
1860 /* 8-bit indices are supported on GFX8. */
1861 if (sctx
->chip_class
<= GFX7
&& index_size
== 1) {
1862 unsigned start
, count
, start_offset
, size
, offset
;
1865 si_get_draw_start_count(sctx
, info
, &start
, &count
);
1866 start_offset
= start
* 2;
1870 u_upload_alloc(ctx
->stream_uploader
, start_offset
,
1872 si_optimal_tcc_alignment(sctx
, size
),
1873 &offset
, &indexbuf
, &ptr
);
1877 util_shorten_ubyte_elts_to_userptr(&sctx
->b
, info
, 0, 0,
1878 index_offset
+ start
,
1881 /* info->start will be added by the drawing code */
1882 index_offset
= offset
- start_offset
;
1884 } else if (info
->has_user_indices
) {
1885 unsigned start_offset
;
1887 assert(!info
->indirect
);
1888 start_offset
= info
->start
* index_size
;
1891 u_upload_data(ctx
->stream_uploader
, start_offset
,
1892 info
->count
* index_size
,
1893 sctx
->screen
->info
.tcc_cache_line_size
,
1894 (char*)info
->index
.user
+ start_offset
,
1895 &index_offset
, &indexbuf
);
1899 /* info->start will be added by the drawing code */
1900 index_offset
-= start_offset
;
1901 } else if (sctx
->chip_class
<= GFX7
&&
1902 si_resource(indexbuf
)->TC_L2_dirty
) {
1903 /* GFX8 reads index buffers through TC L2, so it doesn't
1905 sctx
->flags
|= SI_CONTEXT_WB_L2
;
1906 si_resource(indexbuf
)->TC_L2_dirty
= false;
1910 bool dispatch_prim_discard_cs
= false;
1911 bool prim_discard_cs_instancing
= false;
1912 unsigned original_index_size
= index_size
;
1913 unsigned direct_count
= 0;
1915 if (info
->indirect
) {
1916 struct pipe_draw_indirect_info
*indirect
= info
->indirect
;
1918 /* Add the buffer size for memory checking in need_cs_space. */
1919 si_context_add_resource_size(sctx
, indirect
->buffer
);
1921 /* Indirect buffers use TC L2 on GFX9, but not older hw. */
1922 if (sctx
->chip_class
<= GFX8
) {
1923 if (si_resource(indirect
->buffer
)->TC_L2_dirty
) {
1924 sctx
->flags
|= SI_CONTEXT_WB_L2
;
1925 si_resource(indirect
->buffer
)->TC_L2_dirty
= false;
1928 if (indirect
->indirect_draw_count
&&
1929 si_resource(indirect
->indirect_draw_count
)->TC_L2_dirty
) {
1930 sctx
->flags
|= SI_CONTEXT_WB_L2
;
1931 si_resource(indirect
->indirect_draw_count
)->TC_L2_dirty
= false;
1935 /* Multiply by 3 for strips and fans to get an approximate vertex
1936 * count as triangles. */
1937 direct_count
= info
->count
* instance_count
*
1938 (prim
== PIPE_PRIM_TRIANGLES
? 1 : 3);
1941 /* Determine if we can use the primitive discard compute shader. */
1942 if (si_compute_prim_discard_enabled(sctx
) &&
1943 (direct_count
> sctx
->prim_discard_vertex_count_threshold
?
1944 (sctx
->compute_num_verts_rejected
+= direct_count
, true) : /* Add, then return true. */
1945 (sctx
->compute_num_verts_ineligible
+= direct_count
, false)) && /* Add, then return false. */
1946 (!info
->count_from_stream_output
|| pd_msg("draw_opaque")) &&
1947 (primitive_restart
?
1948 /* Supported prim types with primitive restart: */
1949 (prim
== PIPE_PRIM_TRIANGLE_STRIP
|| pd_msg("bad prim type with primitive restart")) &&
1950 /* Disallow instancing with primitive restart: */
1951 (instance_count
== 1 || pd_msg("instance_count > 1 with primitive restart")) :
1952 /* Supported prim types without primitive restart + allow instancing: */
1953 (1 << prim
) & ((1 << PIPE_PRIM_TRIANGLES
) |
1954 (1 << PIPE_PRIM_TRIANGLE_STRIP
) |
1955 (1 << PIPE_PRIM_TRIANGLE_FAN
)) &&
1956 /* Instancing is limited to 16-bit indices, because InstanceID is packed into VertexID. */
1957 /* TODO: DrawArraysInstanced doesn't sometimes work, so it's disabled. */
1958 (instance_count
== 1 ||
1959 (instance_count
<= USHRT_MAX
&& index_size
&& index_size
<= 2) ||
1960 pd_msg("instance_count too large or index_size == 4 or DrawArraysInstanced"))) &&
1961 (info
->drawid
== 0 || !sctx
->vs_shader
.cso
->info
.uses_drawid
|| pd_msg("draw_id > 0")) &&
1962 (!sctx
->render_cond
|| pd_msg("render condition")) &&
1963 /* Forced enablement ignores pipeline statistics queries. */
1964 (sctx
->screen
->debug_flags
& (DBG(PD
) | DBG(ALWAYS_PD
)) ||
1965 (!sctx
->num_pipeline_stat_queries
&& !sctx
->streamout
.prims_gen_query_enabled
) ||
1966 pd_msg("pipestat or primgen query")) &&
1967 (!sctx
->vertex_elements
->instance_divisor_is_fetched
|| pd_msg("loads instance divisors")) &&
1968 (!sctx
->tes_shader
.cso
|| pd_msg("uses tess")) &&
1969 (!sctx
->gs_shader
.cso
|| pd_msg("uses GS")) &&
1970 (!sctx
->ps_shader
.cso
->info
.uses_primid
|| pd_msg("PS uses PrimID")) &&
1971 #if SI_PRIM_DISCARD_DEBUG /* same as cso->prim_discard_cs_allowed */
1972 (!sctx
->vs_shader
.cso
->info
.uses_bindless_images
|| pd_msg("uses bindless images")) &&
1973 (!sctx
->vs_shader
.cso
->info
.uses_bindless_samplers
|| pd_msg("uses bindless samplers")) &&
1974 (!sctx
->vs_shader
.cso
->info
.writes_memory
|| pd_msg("writes memory")) &&
1975 (!sctx
->vs_shader
.cso
->info
.writes_viewport_index
|| pd_msg("writes viewport index")) &&
1976 !sctx
->vs_shader
.cso
->info
.properties
[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION
] &&
1977 !sctx
->vs_shader
.cso
->so
.num_outputs
&&
1979 (sctx
->vs_shader
.cso
->prim_discard_cs_allowed
|| pd_msg("VS shader uses unsupported features")) &&
1981 /* Check that all buffers are used for read only, because compute
1982 * dispatches can run ahead. */
1983 (si_all_vs_resources_read_only(sctx
, index_size
? indexbuf
: NULL
) || pd_msg("write reference"))) {
1984 switch (si_prepare_prim_discard_or_split_draw(sctx
, info
, primitive_restart
)) {
1985 case SI_PRIM_DISCARD_ENABLED
:
1986 original_index_size
= index_size
;
1987 prim_discard_cs_instancing
= instance_count
> 1;
1988 dispatch_prim_discard_cs
= true;
1990 /* The compute shader changes/lowers the following: */
1991 prim
= PIPE_PRIM_TRIANGLES
;
1994 primitive_restart
= false;
1995 sctx
->compute_num_verts_rejected
-= direct_count
;
1996 sctx
->compute_num_verts_accepted
+= direct_count
;
1998 case SI_PRIM_DISCARD_DISABLED
:
2000 case SI_PRIM_DISCARD_DRAW_SPLIT
:
2001 sctx
->compute_num_verts_rejected
-= direct_count
;
2002 goto return_cleanup
;
2006 if (prim_discard_cs_instancing
!= sctx
->prim_discard_cs_instancing
) {
2007 sctx
->prim_discard_cs_instancing
= prim_discard_cs_instancing
;
2008 sctx
->do_update_shaders
= true;
2011 if (sctx
->do_update_shaders
&& !si_update_shaders(sctx
))
2012 goto return_cleanup
;
2014 si_need_gfx_cs_space(sctx
);
2016 if (sctx
->bo_list_add_all_gfx_resources
)
2017 si_gfx_resources_add_all_to_bo_list(sctx
);
2019 /* Since we've called si_context_add_resource_size for vertex buffers,
2020 * this must be called after si_need_cs_space, because we must let
2021 * need_cs_space flush before we add buffers to the buffer list.
2023 if (!si_upload_vertex_buffer_descriptors(sctx
))
2024 goto return_cleanup
;
2026 /* Vega10/Raven scissor bug workaround. When any context register is
2027 * written (i.e. the GPU rolls the context), PA_SC_VPORT_SCISSOR
2028 * registers must be written too.
2030 bool has_gfx9_scissor_bug
= sctx
->screen
->has_gfx9_scissor_bug
;
2031 unsigned masked_atoms
= 0;
2033 if (has_gfx9_scissor_bug
) {
2034 masked_atoms
|= si_get_atom_bit(sctx
, &sctx
->atoms
.s
.scissors
);
2036 if (info
->count_from_stream_output
||
2037 sctx
->dirty_atoms
& si_atoms_that_always_roll_context() ||
2038 sctx
->dirty_states
& si_states_that_always_roll_context())
2039 sctx
->context_roll
= true;
2042 /* Use optimal packet order based on whether we need to sync the pipeline. */
2043 if (unlikely(sctx
->flags
& (SI_CONTEXT_FLUSH_AND_INV_CB
|
2044 SI_CONTEXT_FLUSH_AND_INV_DB
|
2045 SI_CONTEXT_PS_PARTIAL_FLUSH
|
2046 SI_CONTEXT_CS_PARTIAL_FLUSH
))) {
2047 /* If we have to wait for idle, set all states first, so that all
2048 * SET packets are processed in parallel with previous draw calls.
2049 * Then draw and prefetch at the end. This ensures that the time
2050 * the CUs are idle is very short.
2052 if (unlikely(sctx
->flags
& SI_CONTEXT_FLUSH_FOR_RENDER_COND
))
2053 masked_atoms
|= si_get_atom_bit(sctx
, &sctx
->atoms
.s
.render_cond
);
2055 if (!si_upload_graphics_shader_descriptors(sctx
))
2056 goto return_cleanup
;
2058 /* Emit all states except possibly render condition. */
2059 si_emit_all_states(sctx
, info
, prim
, instance_count
,
2060 primitive_restart
, masked_atoms
);
2061 sctx
->emit_cache_flush(sctx
);
2062 /* <-- CUs are idle here. */
2064 if (si_is_atom_dirty(sctx
, &sctx
->atoms
.s
.render_cond
))
2065 sctx
->atoms
.s
.render_cond
.emit(sctx
);
2067 if (has_gfx9_scissor_bug
&&
2068 (sctx
->context_roll
||
2069 si_is_atom_dirty(sctx
, &sctx
->atoms
.s
.scissors
)))
2070 sctx
->atoms
.s
.scissors
.emit(sctx
);
2072 sctx
->dirty_atoms
= 0;
2074 si_emit_draw_packets(sctx
, info
, indexbuf
, index_size
, index_offset
,
2075 instance_count
, dispatch_prim_discard_cs
,
2076 original_index_size
);
2077 /* <-- CUs are busy here. */
2079 /* Start prefetches after the draw has been started. Both will run
2080 * in parallel, but starting the draw first is more important.
2082 if (sctx
->chip_class
>= GFX7
&& sctx
->prefetch_L2_mask
)
2083 cik_emit_prefetch_L2(sctx
, false);
2085 /* If we don't wait for idle, start prefetches first, then set
2086 * states, and draw at the end.
2089 sctx
->emit_cache_flush(sctx
);
2091 /* Only prefetch the API VS and VBO descriptors. */
2092 if (sctx
->chip_class
>= GFX7
&& sctx
->prefetch_L2_mask
)
2093 cik_emit_prefetch_L2(sctx
, true);
2095 if (!si_upload_graphics_shader_descriptors(sctx
))
2096 goto return_cleanup
;
2098 si_emit_all_states(sctx
, info
, prim
, instance_count
,
2099 primitive_restart
, masked_atoms
);
2101 if (has_gfx9_scissor_bug
&&
2102 (sctx
->context_roll
||
2103 si_is_atom_dirty(sctx
, &sctx
->atoms
.s
.scissors
)))
2104 sctx
->atoms
.s
.scissors
.emit(sctx
);
2106 sctx
->dirty_atoms
= 0;
2108 si_emit_draw_packets(sctx
, info
, indexbuf
, index_size
, index_offset
,
2109 instance_count
, dispatch_prim_discard_cs
,
2110 original_index_size
);
2112 /* Prefetch the remaining shaders after the draw has been
2114 if (sctx
->chip_class
>= GFX7
&& sctx
->prefetch_L2_mask
)
2115 cik_emit_prefetch_L2(sctx
, false);
2118 /* Clear the context roll flag after the draw call. */
2119 sctx
->context_roll
= false;
2121 if (unlikely(sctx
->current_saved_cs
)) {
2122 si_trace_emit(sctx
);
2123 si_log_draw_state(sctx
, sctx
->log
);
2126 /* Workaround for a VGT hang when streamout is enabled.
2127 * It must be done after drawing. */
2128 if ((sctx
->family
== CHIP_HAWAII
||
2129 sctx
->family
== CHIP_TONGA
||
2130 sctx
->family
== CHIP_FIJI
) &&
2131 si_get_strmout_en(sctx
)) {
2132 sctx
->flags
|= SI_CONTEXT_VGT_STREAMOUT_SYNC
;
2135 if (unlikely(sctx
->decompression_enabled
)) {
2136 sctx
->num_decompress_calls
++;
2138 sctx
->num_draw_calls
++;
2139 if (sctx
->framebuffer
.state
.nr_cbufs
> 1)
2140 sctx
->num_mrt_draw_calls
++;
2141 if (primitive_restart
)
2142 sctx
->num_prim_restart_calls
++;
2143 if (G_0286E8_WAVESIZE(sctx
->spi_tmpring_size
))
2144 sctx
->num_spill_draw_calls
++;
2148 if (index_size
&& indexbuf
!= info
->index
.resource
)
2149 pipe_resource_reference(&indexbuf
, NULL
);
2153 si_draw_rectangle(struct blitter_context
*blitter
,
2154 void *vertex_elements_cso
,
2155 blitter_get_vs_func get_vs
,
2156 int x1
, int y1
, int x2
, int y2
,
2157 float depth
, unsigned num_instances
,
2158 enum blitter_attrib_type type
,
2159 const union blitter_attrib
*attrib
)
2161 struct pipe_context
*pipe
= util_blitter_get_pipe(blitter
);
2162 struct si_context
*sctx
= (struct si_context
*)pipe
;
2164 /* Pack position coordinates as signed int16. */
2165 sctx
->vs_blit_sh_data
[0] = (uint32_t)(x1
& 0xffff) |
2166 ((uint32_t)(y1
& 0xffff) << 16);
2167 sctx
->vs_blit_sh_data
[1] = (uint32_t)(x2
& 0xffff) |
2168 ((uint32_t)(y2
& 0xffff) << 16);
2169 sctx
->vs_blit_sh_data
[2] = fui(depth
);
2172 case UTIL_BLITTER_ATTRIB_COLOR
:
2173 memcpy(&sctx
->vs_blit_sh_data
[3], attrib
->color
,
2176 case UTIL_BLITTER_ATTRIB_TEXCOORD_XY
:
2177 case UTIL_BLITTER_ATTRIB_TEXCOORD_XYZW
:
2178 memcpy(&sctx
->vs_blit_sh_data
[3], &attrib
->texcoord
,
2179 sizeof(attrib
->texcoord
));
2181 case UTIL_BLITTER_ATTRIB_NONE
:;
2184 pipe
->bind_vs_state(pipe
, si_get_blitter_vs(sctx
, type
, num_instances
));
2186 struct pipe_draw_info info
= {};
2187 info
.mode
= SI_PRIM_RECTANGLE_LIST
;
2189 info
.instance_count
= num_instances
;
2191 /* Don't set per-stage shader pointers for VS. */
2192 sctx
->shader_pointers_dirty
&= ~SI_DESCS_SHADER_MASK(VERTEX
);
2193 sctx
->vertex_buffer_pointer_dirty
= false;
2195 si_draw_vbo(pipe
, &info
);
2198 void si_trace_emit(struct si_context
*sctx
)
2200 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
2201 uint32_t trace_id
= ++sctx
->current_saved_cs
->trace_id
;
2203 si_cp_write_data(sctx
, sctx
->current_saved_cs
->trace_buf
,
2204 0, 4, V_370_MEM
, V_370_ME
, &trace_id
);
2206 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
2207 radeon_emit(cs
, AC_ENCODE_TRACE_POINT(trace_id
));
2210 u_log_flush(sctx
->log
);
2213 void si_init_draw_functions(struct si_context
*sctx
)
2215 sctx
->b
.draw_vbo
= si_draw_vbo
;
2217 sctx
->blitter
->draw_rectangle
= si_draw_rectangle
;
2219 si_init_ia_multi_vgt_param_table(sctx
);