2 * Copyright 2012 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 * Christian König <christian.koenig@amd.com>
28 #include "si_shader.h"
29 #include "radeon/r600_cs.h"
32 #include "util/u_index_modify.h"
33 #include "util/u_upload_mgr.h"
34 #include "util/u_prim.h"
35 #include "util/u_memory.h"
37 static unsigned si_conv_pipe_prim(unsigned mode
)
39 static const unsigned prim_conv
[] = {
40 [PIPE_PRIM_POINTS
] = V_008958_DI_PT_POINTLIST
,
41 [PIPE_PRIM_LINES
] = V_008958_DI_PT_LINELIST
,
42 [PIPE_PRIM_LINE_LOOP
] = V_008958_DI_PT_LINELOOP
,
43 [PIPE_PRIM_LINE_STRIP
] = V_008958_DI_PT_LINESTRIP
,
44 [PIPE_PRIM_TRIANGLES
] = V_008958_DI_PT_TRILIST
,
45 [PIPE_PRIM_TRIANGLE_STRIP
] = V_008958_DI_PT_TRISTRIP
,
46 [PIPE_PRIM_TRIANGLE_FAN
] = V_008958_DI_PT_TRIFAN
,
47 [PIPE_PRIM_QUADS
] = V_008958_DI_PT_QUADLIST
,
48 [PIPE_PRIM_QUAD_STRIP
] = V_008958_DI_PT_QUADSTRIP
,
49 [PIPE_PRIM_POLYGON
] = V_008958_DI_PT_POLYGON
,
50 [PIPE_PRIM_LINES_ADJACENCY
] = V_008958_DI_PT_LINELIST_ADJ
,
51 [PIPE_PRIM_LINE_STRIP_ADJACENCY
] = V_008958_DI_PT_LINESTRIP_ADJ
,
52 [PIPE_PRIM_TRIANGLES_ADJACENCY
] = V_008958_DI_PT_TRILIST_ADJ
,
53 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY
] = V_008958_DI_PT_TRISTRIP_ADJ
,
54 [PIPE_PRIM_PATCHES
] = V_008958_DI_PT_PATCH
,
55 [R600_PRIM_RECTANGLE_LIST
] = V_008958_DI_PT_RECTLIST
57 assert(mode
< ARRAY_SIZE(prim_conv
));
58 return prim_conv
[mode
];
61 static unsigned si_conv_prim_to_gs_out(unsigned mode
)
63 static const int prim_conv
[] = {
64 [PIPE_PRIM_POINTS
] = V_028A6C_OUTPRIM_TYPE_POINTLIST
,
65 [PIPE_PRIM_LINES
] = V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
66 [PIPE_PRIM_LINE_LOOP
] = V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
67 [PIPE_PRIM_LINE_STRIP
] = V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
68 [PIPE_PRIM_TRIANGLES
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
69 [PIPE_PRIM_TRIANGLE_STRIP
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
70 [PIPE_PRIM_TRIANGLE_FAN
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
71 [PIPE_PRIM_QUADS
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
72 [PIPE_PRIM_QUAD_STRIP
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
73 [PIPE_PRIM_POLYGON
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
74 [PIPE_PRIM_LINES_ADJACENCY
] = V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
75 [PIPE_PRIM_LINE_STRIP_ADJACENCY
] = V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
76 [PIPE_PRIM_TRIANGLES_ADJACENCY
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
77 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
78 [PIPE_PRIM_PATCHES
] = V_028A6C_OUTPRIM_TYPE_POINTLIST
,
79 [R600_PRIM_RECTANGLE_LIST
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
81 assert(mode
< ARRAY_SIZE(prim_conv
));
83 return prim_conv
[mode
];
87 * This calculates the LDS size for tessellation shaders (VS, TCS, TES).
88 * LS.LDS_SIZE is shared by all 3 shader stages.
90 * The information about LDS and other non-compile-time parameters is then
91 * written to userdata SGPRs.
93 static void si_emit_derived_tess_state(struct si_context
*sctx
,
94 const struct pipe_draw_info
*info
,
95 unsigned *num_patches
)
97 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
98 struct si_shader_ctx_state
*ls
= &sctx
->vs_shader
;
99 /* The TES pointer will only be used for sctx->last_tcs.
100 * It would be wrong to think that TCS = TES. */
101 struct si_shader_selector
*tcs
=
102 sctx
->tcs_shader
.cso
? sctx
->tcs_shader
.cso
: sctx
->tes_shader
.cso
;
103 unsigned tes_sh_base
= sctx
->shader_userdata
.sh_base
[PIPE_SHADER_TESS_EVAL
];
104 unsigned num_tcs_input_cp
= info
->vertices_per_patch
;
105 unsigned num_tcs_output_cp
, num_tcs_inputs
, num_tcs_outputs
;
106 unsigned num_tcs_patch_outputs
;
107 unsigned input_vertex_size
, output_vertex_size
, pervertex_output_patch_size
;
108 unsigned input_patch_size
, output_patch_size
, output_patch0_offset
;
109 unsigned perpatch_output_offset
, lds_size
, ls_rsrc2
;
110 unsigned tcs_in_layout
, tcs_out_layout
, tcs_out_offsets
;
111 unsigned offchip_layout
, hardware_lds_size
;
113 /* This calculates how shader inputs and outputs among VS, TCS, and TES
114 * are laid out in LDS. */
115 num_tcs_inputs
= util_last_bit64(ls
->cso
->outputs_written
);
117 if (sctx
->tcs_shader
.cso
) {
118 num_tcs_outputs
= util_last_bit64(tcs
->outputs_written
);
119 num_tcs_output_cp
= tcs
->info
.properties
[TGSI_PROPERTY_TCS_VERTICES_OUT
];
120 num_tcs_patch_outputs
= util_last_bit64(tcs
->patch_outputs_written
);
122 /* No TCS. Route varyings from LS to TES. */
123 num_tcs_outputs
= num_tcs_inputs
;
124 num_tcs_output_cp
= num_tcs_input_cp
;
125 num_tcs_patch_outputs
= 2; /* TESSINNER + TESSOUTER */
128 input_vertex_size
= num_tcs_inputs
* 16;
129 output_vertex_size
= num_tcs_outputs
* 16;
131 input_patch_size
= num_tcs_input_cp
* input_vertex_size
;
133 pervertex_output_patch_size
= num_tcs_output_cp
* output_vertex_size
;
134 output_patch_size
= pervertex_output_patch_size
+ num_tcs_patch_outputs
* 16;
136 /* Ensure that we only need one wave per SIMD so we don't need to check
137 * resource usage. Also ensures that the number of tcs in and out
138 * vertices per threadgroup are at most 256.
140 *num_patches
= 64 / MAX2(num_tcs_input_cp
, num_tcs_output_cp
) * 4;
142 /* Make sure that the data fits in LDS. This assumes the shaders only
143 * use LDS for the inputs and outputs.
145 hardware_lds_size
= sctx
->b
.chip_class
>= CIK
? 65536 : 32768;
146 *num_patches
= MIN2(*num_patches
, hardware_lds_size
/ (input_patch_size
+
149 /* Make sure the output data fits in the offchip buffer */
150 *num_patches
= MIN2(*num_patches
, SI_TESS_OFFCHIP_BLOCK_SIZE
/
153 /* Not necessary for correctness, but improves performance. The
154 * specific value is taken from the proprietary driver.
156 *num_patches
= MIN2(*num_patches
, 40);
158 output_patch0_offset
= input_patch_size
* *num_patches
;
159 perpatch_output_offset
= output_patch0_offset
+ pervertex_output_patch_size
;
161 lds_size
= output_patch0_offset
+ output_patch_size
* *num_patches
;
162 ls_rsrc2
= ls
->current
->config
.rsrc2
;
164 if (sctx
->b
.chip_class
>= CIK
) {
165 assert(lds_size
<= 65536);
166 ls_rsrc2
|= S_00B52C_LDS_SIZE(align(lds_size
, 512) / 512);
168 assert(lds_size
<= 32768);
169 ls_rsrc2
|= S_00B52C_LDS_SIZE(align(lds_size
, 256) / 256);
172 if (sctx
->last_ls
== ls
->current
&&
173 sctx
->last_tcs
== tcs
&&
174 sctx
->last_tes_sh_base
== tes_sh_base
&&
175 sctx
->last_num_tcs_input_cp
== num_tcs_input_cp
)
178 sctx
->last_ls
= ls
->current
;
179 sctx
->last_tcs
= tcs
;
180 sctx
->last_tes_sh_base
= tes_sh_base
;
181 sctx
->last_num_tcs_input_cp
= num_tcs_input_cp
;
183 /* Due to a hw bug, RSRC2_LS must be written twice with another
184 * LS register written in between. */
185 if (sctx
->b
.chip_class
== CIK
&& sctx
->b
.family
!= CHIP_HAWAII
)
186 radeon_set_sh_reg(cs
, R_00B52C_SPI_SHADER_PGM_RSRC2_LS
, ls_rsrc2
);
187 radeon_set_sh_reg_seq(cs
, R_00B528_SPI_SHADER_PGM_RSRC1_LS
, 2);
188 radeon_emit(cs
, ls
->current
->config
.rsrc1
);
189 radeon_emit(cs
, ls_rsrc2
);
191 /* Compute userdata SGPRs. */
192 assert(((input_vertex_size
/ 4) & ~0xff) == 0);
193 assert(((output_vertex_size
/ 4) & ~0xff) == 0);
194 assert(((input_patch_size
/ 4) & ~0x1fff) == 0);
195 assert(((output_patch_size
/ 4) & ~0x1fff) == 0);
196 assert(((output_patch0_offset
/ 16) & ~0xffff) == 0);
197 assert(((perpatch_output_offset
/ 16) & ~0xffff) == 0);
198 assert(num_tcs_input_cp
<= 32);
199 assert(num_tcs_output_cp
<= 32);
201 tcs_in_layout
= (input_patch_size
/ 4) |
202 ((input_vertex_size
/ 4) << 13);
203 tcs_out_layout
= (output_patch_size
/ 4) |
204 ((output_vertex_size
/ 4) << 13);
205 tcs_out_offsets
= (output_patch0_offset
/ 16) |
206 ((perpatch_output_offset
/ 16) << 16);
207 offchip_layout
= (pervertex_output_patch_size
* *num_patches
<< 16) |
208 (num_tcs_output_cp
<< 9) | *num_patches
;
210 /* Set them for LS. */
211 radeon_set_sh_reg(cs
,
212 R_00B530_SPI_SHADER_USER_DATA_LS_0
+ SI_SGPR_LS_OUT_LAYOUT
* 4,
215 /* Set them for TCS. */
216 radeon_set_sh_reg_seq(cs
,
217 R_00B430_SPI_SHADER_USER_DATA_HS_0
+ SI_SGPR_TCS_OFFCHIP_LAYOUT
* 4, 4);
218 radeon_emit(cs
, offchip_layout
);
219 radeon_emit(cs
, tcs_out_offsets
);
220 radeon_emit(cs
, tcs_out_layout
| (num_tcs_input_cp
<< 26));
221 radeon_emit(cs
, tcs_in_layout
);
223 /* Set them for TES. */
224 radeon_set_sh_reg_seq(cs
, tes_sh_base
+ SI_SGPR_TCS_OFFCHIP_LAYOUT
* 4, 1);
225 radeon_emit(cs
, offchip_layout
);
228 static unsigned si_num_prims_for_vertices(const struct pipe_draw_info
*info
)
230 switch (info
->mode
) {
231 case PIPE_PRIM_PATCHES
:
232 return info
->count
/ info
->vertices_per_patch
;
233 case R600_PRIM_RECTANGLE_LIST
:
234 return info
->count
/ 3;
236 return u_prims_for_vertices(info
->mode
, info
->count
);
240 static unsigned si_get_ia_multi_vgt_param(struct si_context
*sctx
,
241 const struct pipe_draw_info
*info
,
242 unsigned num_patches
)
244 struct si_state_rasterizer
*rs
= sctx
->queued
.named
.rasterizer
;
245 unsigned prim
= info
->mode
;
246 unsigned primgroup_size
= 128; /* recommended without a GS */
247 unsigned max_primgroup_in_wave
= 2;
249 /* SWITCH_ON_EOP(0) is always preferable. */
250 bool wd_switch_on_eop
= false;
251 bool ia_switch_on_eop
= false;
252 bool ia_switch_on_eoi
= false;
253 bool partial_vs_wave
= false;
254 bool partial_es_wave
= false;
256 if (sctx
->gs_shader
.cso
)
257 primgroup_size
= 64; /* recommended with a GS */
259 if (sctx
->tes_shader
.cso
) {
260 /* primgroup_size must be set to a multiple of NUM_PATCHES */
261 primgroup_size
= num_patches
;
263 /* SWITCH_ON_EOI must be set if PrimID is used. */
264 if ((sctx
->tcs_shader
.cso
&& sctx
->tcs_shader
.cso
->info
.uses_primid
) ||
265 sctx
->tes_shader
.cso
->info
.uses_primid
)
266 ia_switch_on_eoi
= true;
268 /* Bug with tessellation and GS on Bonaire and older 2 SE chips. */
269 if ((sctx
->b
.family
== CHIP_TAHITI
||
270 sctx
->b
.family
== CHIP_PITCAIRN
||
271 sctx
->b
.family
== CHIP_BONAIRE
) &&
273 partial_vs_wave
= true;
275 /* Needed for 028B6C_DISTRIBUTION_MODE != 0 */
276 if (sctx
->b
.chip_class
>= VI
) {
277 if (sctx
->gs_shader
.cso
)
278 partial_es_wave
= true;
280 partial_vs_wave
= true;
284 /* This is a hardware requirement. */
285 if ((rs
&& rs
->line_stipple_enable
) ||
286 (sctx
->b
.screen
->debug_flags
& DBG_SWITCH_ON_EOP
)) {
287 ia_switch_on_eop
= true;
288 wd_switch_on_eop
= true;
291 if (sctx
->b
.chip_class
>= CIK
) {
292 /* WD_SWITCH_ON_EOP has no effect on GPUs with less than
293 * 4 shader engines. Set 1 to pass the assertion below.
294 * The other cases are hardware requirements.
296 * Polaris supports primitive restart with WD_SWITCH_ON_EOP=0
297 * for points, line strips, and tri strips.
299 if (sctx
->b
.screen
->info
.max_se
< 4 ||
300 prim
== PIPE_PRIM_POLYGON
||
301 prim
== PIPE_PRIM_LINE_LOOP
||
302 prim
== PIPE_PRIM_TRIANGLE_FAN
||
303 prim
== PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY
||
304 (info
->primitive_restart
&&
305 (sctx
->b
.family
< CHIP_POLARIS10
||
306 (prim
!= PIPE_PRIM_POINTS
&&
307 prim
!= PIPE_PRIM_LINE_STRIP
&&
308 prim
!= PIPE_PRIM_TRIANGLE_STRIP
))) ||
309 info
->count_from_stream_output
)
310 wd_switch_on_eop
= true;
312 /* Hawaii hangs if instancing is enabled and WD_SWITCH_ON_EOP is 0.
313 * We don't know that for indirect drawing, so treat it as
314 * always problematic. */
315 if (sctx
->b
.family
== CHIP_HAWAII
&&
316 (info
->indirect
|| info
->instance_count
> 1))
317 wd_switch_on_eop
= true;
319 /* Performance recommendation for 4 SE Gfx7-8 parts if
320 * instances are smaller than a primgroup. Ignore the fact
321 * primgroup_size is a primitive count, not vertex count.
322 * Don't do anything for indirect draws.
324 if (sctx
->b
.chip_class
<= VI
&&
325 sctx
->b
.screen
->info
.max_se
>= 4 &&
327 info
->instance_count
> 1 && info
->count
< primgroup_size
)
328 wd_switch_on_eop
= true;
330 /* Required on CIK and later. */
331 if (sctx
->b
.screen
->info
.max_se
> 2 && !wd_switch_on_eop
)
332 ia_switch_on_eoi
= true;
334 /* Required by Hawaii and, for some special cases, by VI. */
335 if (ia_switch_on_eoi
&&
336 (sctx
->b
.family
== CHIP_HAWAII
||
337 (sctx
->b
.chip_class
== VI
&&
338 (sctx
->gs_shader
.cso
|| max_primgroup_in_wave
!= 2))))
339 partial_vs_wave
= true;
341 /* Instancing bug on Bonaire. */
342 if (sctx
->b
.family
== CHIP_BONAIRE
&& ia_switch_on_eoi
&&
343 (info
->indirect
|| info
->instance_count
> 1))
344 partial_vs_wave
= true;
346 /* If the WD switch is false, the IA switch must be false too. */
347 assert(wd_switch_on_eop
|| !ia_switch_on_eop
);
350 /* If SWITCH_ON_EOI is set, PARTIAL_ES_WAVE must be set too. */
351 if (ia_switch_on_eoi
)
352 partial_es_wave
= true;
354 /* GS requirement. */
355 if (SI_GS_PER_ES
/ primgroup_size
>= sctx
->screen
->gs_table_depth
- 3)
356 partial_es_wave
= true;
358 /* Hw bug with single-primitive instances and SWITCH_ON_EOI
359 * on multi-SE chips. */
360 if (sctx
->b
.screen
->info
.max_se
>= 2 && ia_switch_on_eoi
&&
362 (info
->instance_count
> 1 &&
363 si_num_prims_for_vertices(info
) <= 1)))
364 sctx
->b
.flags
|= SI_CONTEXT_VGT_FLUSH
;
366 return S_028AA8_SWITCH_ON_EOP(ia_switch_on_eop
) |
367 S_028AA8_SWITCH_ON_EOI(ia_switch_on_eoi
) |
368 S_028AA8_PARTIAL_VS_WAVE_ON(partial_vs_wave
) |
369 S_028AA8_PARTIAL_ES_WAVE_ON(partial_es_wave
) |
370 S_028AA8_PRIMGROUP_SIZE(primgroup_size
- 1) |
371 S_028AA8_WD_SWITCH_ON_EOP(sctx
->b
.chip_class
>= CIK
? wd_switch_on_eop
: 0) |
372 S_028AA8_MAX_PRIMGRP_IN_WAVE(sctx
->b
.chip_class
>= VI
?
373 max_primgroup_in_wave
: 0);
376 static unsigned si_get_ls_hs_config(struct si_context
*sctx
,
377 const struct pipe_draw_info
*info
,
378 unsigned num_patches
)
380 unsigned num_output_cp
;
382 if (!sctx
->tes_shader
.cso
)
385 num_output_cp
= sctx
->tcs_shader
.cso
?
386 sctx
->tcs_shader
.cso
->info
.properties
[TGSI_PROPERTY_TCS_VERTICES_OUT
] :
387 info
->vertices_per_patch
;
389 return S_028B58_NUM_PATCHES(num_patches
) |
390 S_028B58_HS_NUM_INPUT_CP(info
->vertices_per_patch
) |
391 S_028B58_HS_NUM_OUTPUT_CP(num_output_cp
);
394 static void si_emit_scratch_reloc(struct si_context
*sctx
)
396 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
398 if (!sctx
->emit_scratch_reloc
)
401 radeon_set_context_reg(cs
, R_0286E8_SPI_TMPRING_SIZE
,
402 sctx
->spi_tmpring_size
);
404 if (sctx
->scratch_buffer
) {
405 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
,
406 sctx
->scratch_buffer
, RADEON_USAGE_READWRITE
,
407 RADEON_PRIO_SCRATCH_BUFFER
);
410 sctx
->emit_scratch_reloc
= false;
413 /* rast_prim is the primitive type after GS. */
414 static void si_emit_rasterizer_prim_state(struct si_context
*sctx
)
416 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
417 unsigned rast_prim
= sctx
->current_rast_prim
;
418 struct si_state_rasterizer
*rs
= sctx
->emitted
.named
.rasterizer
;
420 /* Skip this if not rendering lines. */
421 if (rast_prim
!= PIPE_PRIM_LINES
&&
422 rast_prim
!= PIPE_PRIM_LINE_LOOP
&&
423 rast_prim
!= PIPE_PRIM_LINE_STRIP
&&
424 rast_prim
!= PIPE_PRIM_LINES_ADJACENCY
&&
425 rast_prim
!= PIPE_PRIM_LINE_STRIP_ADJACENCY
)
428 if (rast_prim
== sctx
->last_rast_prim
&&
429 rs
->pa_sc_line_stipple
== sctx
->last_sc_line_stipple
)
432 /* For lines, reset the stipple pattern at each primitive. Otherwise,
433 * reset the stipple pattern at each packet (line strips, line loops).
435 radeon_set_context_reg(cs
, R_028A0C_PA_SC_LINE_STIPPLE
,
436 rs
->pa_sc_line_stipple
|
437 S_028A0C_AUTO_RESET_CNTL(rast_prim
== PIPE_PRIM_LINES
? 1 : 2));
439 sctx
->last_rast_prim
= rast_prim
;
440 sctx
->last_sc_line_stipple
= rs
->pa_sc_line_stipple
;
443 static void si_emit_draw_registers(struct si_context
*sctx
,
444 const struct pipe_draw_info
*info
)
446 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
447 unsigned prim
= si_conv_pipe_prim(info
->mode
);
448 unsigned gs_out_prim
= si_conv_prim_to_gs_out(sctx
->current_rast_prim
);
449 unsigned ia_multi_vgt_param
, ls_hs_config
, num_patches
= 0;
451 /* Polaris needs different VTX_REUSE_DEPTH settings depending on
452 * whether the "fractional odd" tessellation spacing is used.
454 if (sctx
->b
.family
>= CHIP_POLARIS10
) {
455 struct si_shader_selector
*tes
= sctx
->tes_shader
.cso
;
456 unsigned vtx_reuse_depth
= 30;
459 tes
->info
.properties
[TGSI_PROPERTY_TES_SPACING
] ==
460 PIPE_TESS_SPACING_FRACTIONAL_ODD
)
461 vtx_reuse_depth
= 14;
463 if (vtx_reuse_depth
!= sctx
->last_vtx_reuse_depth
) {
464 radeon_set_context_reg(cs
, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL
,
466 sctx
->last_vtx_reuse_depth
= vtx_reuse_depth
;
470 if (sctx
->tes_shader
.cso
)
471 si_emit_derived_tess_state(sctx
, info
, &num_patches
);
473 ia_multi_vgt_param
= si_get_ia_multi_vgt_param(sctx
, info
, num_patches
);
474 ls_hs_config
= si_get_ls_hs_config(sctx
, info
, num_patches
);
477 if (prim
!= sctx
->last_prim
||
478 ia_multi_vgt_param
!= sctx
->last_multi_vgt_param
||
479 ls_hs_config
!= sctx
->last_ls_hs_config
) {
480 if (sctx
->b
.family
>= CHIP_POLARIS10
) {
481 radeon_set_context_reg_idx(cs
, R_028AA8_IA_MULTI_VGT_PARAM
, 1, ia_multi_vgt_param
);
482 radeon_set_context_reg_idx(cs
, R_028B58_VGT_LS_HS_CONFIG
, 2, ls_hs_config
);
483 radeon_set_uconfig_reg_idx(cs
, R_030908_VGT_PRIMITIVE_TYPE
, 1, prim
);
484 } else if (sctx
->b
.chip_class
>= CIK
) {
485 radeon_emit(cs
, PKT3(PKT3_DRAW_PREAMBLE
, 2, 0));
486 radeon_emit(cs
, prim
); /* VGT_PRIMITIVE_TYPE */
487 radeon_emit(cs
, ia_multi_vgt_param
); /* IA_MULTI_VGT_PARAM */
488 radeon_emit(cs
, ls_hs_config
); /* VGT_LS_HS_CONFIG */
490 radeon_set_config_reg(cs
, R_008958_VGT_PRIMITIVE_TYPE
, prim
);
491 radeon_set_context_reg(cs
, R_028AA8_IA_MULTI_VGT_PARAM
, ia_multi_vgt_param
);
492 radeon_set_context_reg(cs
, R_028B58_VGT_LS_HS_CONFIG
, ls_hs_config
);
495 sctx
->last_prim
= prim
;
496 sctx
->last_multi_vgt_param
= ia_multi_vgt_param
;
497 sctx
->last_ls_hs_config
= ls_hs_config
;
500 if (gs_out_prim
!= sctx
->last_gs_out_prim
) {
501 radeon_set_context_reg(cs
, R_028A6C_VGT_GS_OUT_PRIM_TYPE
, gs_out_prim
);
502 sctx
->last_gs_out_prim
= gs_out_prim
;
505 /* Primitive restart. */
506 if (info
->primitive_restart
!= sctx
->last_primitive_restart_en
) {
507 radeon_set_context_reg(cs
, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN
, info
->primitive_restart
);
508 sctx
->last_primitive_restart_en
= info
->primitive_restart
;
510 if (info
->primitive_restart
&&
511 (info
->restart_index
!= sctx
->last_restart_index
||
512 sctx
->last_restart_index
== SI_RESTART_INDEX_UNKNOWN
)) {
513 radeon_set_context_reg(cs
, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX
,
514 info
->restart_index
);
515 sctx
->last_restart_index
= info
->restart_index
;
520 static void si_emit_draw_packets(struct si_context
*sctx
,
521 const struct pipe_draw_info
*info
,
522 const struct pipe_index_buffer
*ib
)
524 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
525 unsigned sh_base_reg
= sctx
->shader_userdata
.sh_base
[PIPE_SHADER_VERTEX
];
526 bool render_cond_bit
= sctx
->b
.render_cond
&& !sctx
->b
.render_cond_force_off
;
528 if (info
->count_from_stream_output
) {
529 struct r600_so_target
*t
=
530 (struct r600_so_target
*)info
->count_from_stream_output
;
531 uint64_t va
= t
->buf_filled_size
->gpu_address
+
532 t
->buf_filled_size_offset
;
534 radeon_set_context_reg(cs
, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE
,
537 radeon_emit(cs
, PKT3(PKT3_COPY_DATA
, 4, 0));
538 radeon_emit(cs
, COPY_DATA_SRC_SEL(COPY_DATA_MEM
) |
539 COPY_DATA_DST_SEL(COPY_DATA_REG
) |
540 COPY_DATA_WR_CONFIRM
);
541 radeon_emit(cs
, va
); /* src address lo */
542 radeon_emit(cs
, va
>> 32); /* src address hi */
543 radeon_emit(cs
, R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE
>> 2);
544 radeon_emit(cs
, 0); /* unused */
546 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
,
547 t
->buf_filled_size
, RADEON_USAGE_READ
,
548 RADEON_PRIO_SO_FILLED_SIZE
);
553 radeon_emit(cs
, PKT3(PKT3_INDEX_TYPE
, 0, 0));
556 switch (ib
->index_size
) {
558 radeon_emit(cs
, V_028A7C_VGT_INDEX_8
);
561 radeon_emit(cs
, V_028A7C_VGT_INDEX_16
|
562 (SI_BIG_ENDIAN
&& sctx
->b
.chip_class
<= CIK
?
563 V_028A7C_VGT_DMA_SWAP_16_BIT
: 0));
566 radeon_emit(cs
, V_028A7C_VGT_INDEX_32
|
567 (SI_BIG_ENDIAN
&& sctx
->b
.chip_class
<= CIK
?
568 V_028A7C_VGT_DMA_SWAP_32_BIT
: 0));
571 assert(!"unreachable");
576 if (!info
->indirect
) {
579 radeon_emit(cs
, PKT3(PKT3_NUM_INSTANCES
, 0, 0));
580 radeon_emit(cs
, info
->instance_count
);
582 /* Base vertex and start instance. */
583 base_vertex
= info
->indexed
? info
->index_bias
: info
->start
;
585 if (base_vertex
!= sctx
->last_base_vertex
||
586 sctx
->last_base_vertex
== SI_BASE_VERTEX_UNKNOWN
||
587 info
->start_instance
!= sctx
->last_start_instance
||
588 sh_base_reg
!= sctx
->last_sh_base_reg
) {
589 radeon_set_sh_reg_seq(cs
, sh_base_reg
+ SI_SGPR_BASE_VERTEX
* 4, 2);
590 radeon_emit(cs
, base_vertex
);
591 radeon_emit(cs
, info
->start_instance
);
593 sctx
->last_base_vertex
= base_vertex
;
594 sctx
->last_start_instance
= info
->start_instance
;
595 sctx
->last_sh_base_reg
= sh_base_reg
;
598 si_invalidate_draw_sh_constants(sctx
);
600 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
,
601 (struct r600_resource
*)info
->indirect
,
602 RADEON_USAGE_READ
, RADEON_PRIO_DRAW_INDIRECT
);
606 uint32_t index_max_size
= (ib
->buffer
->width0
- ib
->offset
) /
608 uint64_t index_va
= r600_resource(ib
->buffer
)->gpu_address
+ ib
->offset
;
610 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
,
611 (struct r600_resource
*)ib
->buffer
,
612 RADEON_USAGE_READ
, RADEON_PRIO_INDEX_BUFFER
);
614 if (info
->indirect
) {
615 uint64_t indirect_va
= r600_resource(info
->indirect
)->gpu_address
;
617 assert(indirect_va
% 8 == 0);
618 assert(index_va
% 2 == 0);
619 assert(info
->indirect_offset
% 4 == 0);
621 radeon_emit(cs
, PKT3(PKT3_SET_BASE
, 2, 0));
623 radeon_emit(cs
, indirect_va
);
624 radeon_emit(cs
, indirect_va
>> 32);
626 radeon_emit(cs
, PKT3(PKT3_INDEX_BASE
, 1, 0));
627 radeon_emit(cs
, index_va
);
628 radeon_emit(cs
, index_va
>> 32);
630 radeon_emit(cs
, PKT3(PKT3_INDEX_BUFFER_SIZE
, 0, 0));
631 radeon_emit(cs
, index_max_size
);
633 if (sctx
->b
.family
< CHIP_POLARIS10
) {
634 radeon_emit(cs
, PKT3(PKT3_DRAW_INDEX_INDIRECT
, 3, render_cond_bit
));
635 radeon_emit(cs
, info
->indirect_offset
);
636 radeon_emit(cs
, (sh_base_reg
+ SI_SGPR_BASE_VERTEX
* 4 - SI_SH_REG_OFFSET
) >> 2);
637 radeon_emit(cs
, (sh_base_reg
+ SI_SGPR_START_INSTANCE
* 4 - SI_SH_REG_OFFSET
) >> 2);
638 radeon_emit(cs
, V_0287F0_DI_SRC_SEL_DMA
);
640 radeon_emit(cs
, PKT3(PKT3_DRAW_INDEX_INDIRECT_MULTI
, 8, render_cond_bit
));
641 radeon_emit(cs
, info
->indirect_offset
);
642 radeon_emit(cs
, (sh_base_reg
+ SI_SGPR_BASE_VERTEX
* 4 - SI_SH_REG_OFFSET
) >> 2);
643 radeon_emit(cs
, (sh_base_reg
+ SI_SGPR_START_INSTANCE
* 4 - SI_SH_REG_OFFSET
) >> 2);
644 radeon_emit(cs
, 0); /* draw_index */
645 radeon_emit(cs
, 1); /* count */
646 radeon_emit(cs
, 0); /* count_addr -- disabled */
648 radeon_emit(cs
, 16); /* stride */
649 radeon_emit(cs
, V_0287F0_DI_SRC_SEL_DMA
);
652 index_va
+= info
->start
* ib
->index_size
;
654 radeon_emit(cs
, PKT3(PKT3_DRAW_INDEX_2
, 4, render_cond_bit
));
655 radeon_emit(cs
, index_max_size
);
656 radeon_emit(cs
, index_va
);
657 radeon_emit(cs
, (index_va
>> 32UL) & 0xFF);
658 radeon_emit(cs
, info
->count
);
659 radeon_emit(cs
, V_0287F0_DI_SRC_SEL_DMA
);
662 if (info
->indirect
) {
663 uint64_t indirect_va
= r600_resource(info
->indirect
)->gpu_address
;
665 assert(indirect_va
% 8 == 0);
666 assert(info
->indirect_offset
% 4 == 0);
668 radeon_emit(cs
, PKT3(PKT3_SET_BASE
, 2, 0));
670 radeon_emit(cs
, indirect_va
);
671 radeon_emit(cs
, indirect_va
>> 32);
673 if (sctx
->b
.family
< CHIP_POLARIS10
) {
674 radeon_emit(cs
, PKT3(PKT3_DRAW_INDIRECT
, 3, render_cond_bit
));
675 radeon_emit(cs
, info
->indirect_offset
);
676 radeon_emit(cs
, (sh_base_reg
+ SI_SGPR_BASE_VERTEX
* 4 - SI_SH_REG_OFFSET
) >> 2);
677 radeon_emit(cs
, (sh_base_reg
+ SI_SGPR_START_INSTANCE
* 4 - SI_SH_REG_OFFSET
) >> 2);
678 radeon_emit(cs
, V_0287F0_DI_SRC_SEL_AUTO_INDEX
);
680 radeon_emit(cs
, PKT3(PKT3_DRAW_INDIRECT_MULTI
, 8, render_cond_bit
));
681 radeon_emit(cs
, info
->indirect_offset
);
682 radeon_emit(cs
, (sh_base_reg
+ SI_SGPR_BASE_VERTEX
* 4 - SI_SH_REG_OFFSET
) >> 2);
683 radeon_emit(cs
, (sh_base_reg
+ SI_SGPR_START_INSTANCE
* 4 - SI_SH_REG_OFFSET
) >> 2);
684 radeon_emit(cs
, 0); /* draw_index */
685 radeon_emit(cs
, 1); /* count */
686 radeon_emit(cs
, 0); /* count_addr -- disabled */
688 radeon_emit(cs
, 16); /* stride */
689 radeon_emit(cs
, V_0287F0_DI_SRC_SEL_AUTO_INDEX
);
692 radeon_emit(cs
, PKT3(PKT3_DRAW_INDEX_AUTO
, 1, render_cond_bit
));
693 radeon_emit(cs
, info
->count
);
694 radeon_emit(cs
, V_0287F0_DI_SRC_SEL_AUTO_INDEX
|
695 S_0287F0_USE_OPAQUE(!!info
->count_from_stream_output
));
700 void si_emit_cache_flush(struct si_context
*si_ctx
, struct r600_atom
*atom
)
702 struct r600_common_context
*sctx
= &si_ctx
->b
;
703 struct radeon_winsys_cs
*cs
= sctx
->gfx
.cs
;
704 uint32_t cp_coher_cntl
= 0;
706 /* SI has a bug that it always flushes ICACHE and KCACHE if either
707 * bit is set. An alternative way is to write SQC_CACHES, but that
708 * doesn't seem to work reliably. Since the bug doesn't affect
709 * correctness (it only does more work than necessary) and
710 * the performance impact is likely negligible, there is no plan
711 * to add a workaround for it.
714 if (sctx
->flags
& SI_CONTEXT_INV_ICACHE
)
715 cp_coher_cntl
|= S_0085F0_SH_ICACHE_ACTION_ENA(1);
716 if (sctx
->flags
& SI_CONTEXT_INV_SMEM_L1
)
717 cp_coher_cntl
|= S_0085F0_SH_KCACHE_ACTION_ENA(1);
719 if (sctx
->flags
& SI_CONTEXT_INV_VMEM_L1
)
720 cp_coher_cntl
|= S_0085F0_TCL1_ACTION_ENA(1);
721 if (sctx
->flags
& SI_CONTEXT_INV_GLOBAL_L2
) {
722 cp_coher_cntl
|= S_0085F0_TC_ACTION_ENA(1);
724 if (sctx
->chip_class
>= VI
)
725 cp_coher_cntl
|= S_0301F0_TC_WB_ACTION_ENA(1);
728 if (sctx
->flags
& SI_CONTEXT_FLUSH_AND_INV_CB
) {
729 cp_coher_cntl
|= S_0085F0_CB_ACTION_ENA(1) |
730 S_0085F0_CB0_DEST_BASE_ENA(1) |
731 S_0085F0_CB1_DEST_BASE_ENA(1) |
732 S_0085F0_CB2_DEST_BASE_ENA(1) |
733 S_0085F0_CB3_DEST_BASE_ENA(1) |
734 S_0085F0_CB4_DEST_BASE_ENA(1) |
735 S_0085F0_CB5_DEST_BASE_ENA(1) |
736 S_0085F0_CB6_DEST_BASE_ENA(1) |
737 S_0085F0_CB7_DEST_BASE_ENA(1);
739 /* Necessary for DCC */
740 if (sctx
->chip_class
>= VI
) {
741 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE_EOP
, 4, 0));
742 radeon_emit(cs
, EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_DATA_TS
) |
750 if (sctx
->flags
& SI_CONTEXT_FLUSH_AND_INV_DB
) {
751 cp_coher_cntl
|= S_0085F0_DB_ACTION_ENA(1) |
752 S_0085F0_DB_DEST_BASE_ENA(1);
755 if (sctx
->flags
& SI_CONTEXT_FLUSH_AND_INV_CB_META
) {
756 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
757 radeon_emit(cs
, EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_META
) | EVENT_INDEX(0));
758 /* needed for wait for idle in SURFACE_SYNC */
759 assert(sctx
->flags
& SI_CONTEXT_FLUSH_AND_INV_CB
);
761 if (sctx
->flags
& SI_CONTEXT_FLUSH_AND_INV_DB_META
) {
762 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
763 radeon_emit(cs
, EVENT_TYPE(V_028A90_FLUSH_AND_INV_DB_META
) | EVENT_INDEX(0));
764 /* needed for wait for idle in SURFACE_SYNC */
765 assert(sctx
->flags
& SI_CONTEXT_FLUSH_AND_INV_DB
);
768 /* Wait for shader engines to go idle.
769 * VS and PS waits are unnecessary if SURFACE_SYNC is going to wait
770 * for everything including CB/DB cache flushes.
772 if (!(sctx
->flags
& (SI_CONTEXT_FLUSH_AND_INV_CB
|
773 SI_CONTEXT_FLUSH_AND_INV_DB
))) {
774 if (sctx
->flags
& SI_CONTEXT_PS_PARTIAL_FLUSH
) {
775 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
776 radeon_emit(cs
, EVENT_TYPE(V_028A90_PS_PARTIAL_FLUSH
) | EVENT_INDEX(4));
777 } else if (sctx
->flags
& SI_CONTEXT_VS_PARTIAL_FLUSH
) {
778 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
779 radeon_emit(cs
, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH
) | EVENT_INDEX(4));
782 if (sctx
->flags
& SI_CONTEXT_CS_PARTIAL_FLUSH
) {
783 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
784 radeon_emit(cs
, EVENT_TYPE(V_028A90_CS_PARTIAL_FLUSH
| EVENT_INDEX(4)));
787 /* VGT state synchronization. */
788 if (sctx
->flags
& SI_CONTEXT_VGT_FLUSH
) {
789 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
790 radeon_emit(cs
, EVENT_TYPE(V_028A90_VGT_FLUSH
) | EVENT_INDEX(0));
792 if (sctx
->flags
& SI_CONTEXT_VGT_STREAMOUT_SYNC
) {
793 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
794 radeon_emit(cs
, EVENT_TYPE(V_028A90_VGT_STREAMOUT_SYNC
) | EVENT_INDEX(0));
797 /* Make sure ME is idle (it executes most packets) before continuing.
798 * This prevents read-after-write hazards between PFP and ME.
800 if (cp_coher_cntl
|| (sctx
->flags
& SI_CONTEXT_CS_PARTIAL_FLUSH
)) {
801 radeon_emit(cs
, PKT3(PKT3_PFP_SYNC_ME
, 0, 0));
805 /* When one of the DEST_BASE flags is set, SURFACE_SYNC waits for idle.
806 * Therefore, it should be last. Done in PFP.
809 /* ACQUIRE_MEM is only required on a compute ring. */
810 radeon_emit(cs
, PKT3(PKT3_SURFACE_SYNC
, 3, 0));
811 radeon_emit(cs
, cp_coher_cntl
); /* CP_COHER_CNTL */
812 radeon_emit(cs
, 0xffffffff); /* CP_COHER_SIZE */
813 radeon_emit(cs
, 0); /* CP_COHER_BASE */
814 radeon_emit(cs
, 0x0000000A); /* POLL_INTERVAL */
817 if (sctx
->flags
& R600_CONTEXT_START_PIPELINE_STATS
) {
818 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
819 radeon_emit(cs
, EVENT_TYPE(V_028A90_PIPELINESTAT_START
) |
821 } else if (sctx
->flags
& R600_CONTEXT_STOP_PIPELINE_STATS
) {
822 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
823 radeon_emit(cs
, EVENT_TYPE(V_028A90_PIPELINESTAT_STOP
) |
830 static void si_get_draw_start_count(struct si_context
*sctx
,
831 const struct pipe_draw_info
*info
,
832 unsigned *start
, unsigned *count
)
834 if (info
->indirect
) {
835 struct r600_resource
*indirect
=
836 (struct r600_resource
*)info
->indirect
;
837 int *data
= r600_buffer_map_sync_with_rings(&sctx
->b
,
838 indirect
, PIPE_TRANSFER_READ
);
839 data
+= info
->indirect_offset
/sizeof(int);
843 *start
= info
->start
;
844 *count
= info
->count
;
848 void si_ce_pre_draw_synchronization(struct si_context
*sctx
)
850 if (sctx
->ce_need_synchronization
) {
851 radeon_emit(sctx
->ce_ib
, PKT3(PKT3_INCREMENT_CE_COUNTER
, 0, 0));
852 radeon_emit(sctx
->ce_ib
, 1);
854 radeon_emit(sctx
->b
.gfx
.cs
, PKT3(PKT3_WAIT_ON_CE_COUNTER
, 0, 0));
855 radeon_emit(sctx
->b
.gfx
.cs
, 1);
859 void si_ce_post_draw_synchronization(struct si_context
*sctx
)
861 if (sctx
->ce_need_synchronization
) {
862 radeon_emit(sctx
->b
.gfx
.cs
, PKT3(PKT3_INCREMENT_DE_COUNTER
, 0, 0));
863 radeon_emit(sctx
->b
.gfx
.cs
, 0);
865 sctx
->ce_need_synchronization
= false;
869 void si_draw_vbo(struct pipe_context
*ctx
, const struct pipe_draw_info
*info
)
871 struct si_context
*sctx
= (struct si_context
*)ctx
;
872 struct si_state_rasterizer
*rs
= sctx
->queued
.named
.rasterizer
;
873 struct pipe_index_buffer ib
= {};
874 unsigned mask
, dirty_fb_counter
, dirty_tex_counter
;
876 if (!info
->count
&& !info
->indirect
&&
877 (info
->indexed
|| !info
->count_from_stream_output
))
880 if (!sctx
->vs_shader
.cso
) {
884 if (!sctx
->ps_shader
.cso
&& (!rs
|| !rs
->rasterizer_discard
)) {
888 if (!!sctx
->tes_shader
.cso
!= (info
->mode
== PIPE_PRIM_PATCHES
)) {
893 /* Re-emit the framebuffer state if needed. */
894 dirty_fb_counter
= p_atomic_read(&sctx
->b
.screen
->dirty_fb_counter
);
895 if (dirty_fb_counter
!= sctx
->b
.last_dirty_fb_counter
) {
896 sctx
->b
.last_dirty_fb_counter
= dirty_fb_counter
;
897 sctx
->framebuffer
.dirty_cbufs
|=
898 ((1 << sctx
->framebuffer
.state
.nr_cbufs
) - 1);
899 sctx
->framebuffer
.dirty_zsbuf
= true;
900 si_mark_atom_dirty(sctx
, &sctx
->framebuffer
.atom
);
903 /* Invalidate & recompute texture descriptors if needed. */
904 dirty_tex_counter
= p_atomic_read(&sctx
->b
.screen
->dirty_tex_descriptor_counter
);
905 if (dirty_tex_counter
!= sctx
->b
.last_dirty_tex_descriptor_counter
) {
906 sctx
->b
.last_dirty_tex_descriptor_counter
= dirty_tex_counter
;
907 si_update_all_texture_descriptors(sctx
);
910 si_decompress_graphics_textures(sctx
);
912 /* Set the rasterization primitive type.
914 * This must be done after si_decompress_textures, which can call
915 * draw_vbo recursively, and before si_update_shaders, which uses
916 * current_rast_prim for this draw_vbo call. */
917 if (sctx
->gs_shader
.cso
)
918 sctx
->current_rast_prim
= sctx
->gs_shader
.cso
->gs_output_prim
;
919 else if (sctx
->tes_shader
.cso
)
920 sctx
->current_rast_prim
=
921 sctx
->tes_shader
.cso
->info
.properties
[TGSI_PROPERTY_TES_PRIM_MODE
];
923 sctx
->current_rast_prim
= info
->mode
;
925 if (!si_update_shaders(sctx
) ||
926 !si_upload_graphics_shader_descriptors(sctx
))
930 /* Initialize the index buffer struct. */
931 pipe_resource_reference(&ib
.buffer
, sctx
->index_buffer
.buffer
);
932 ib
.user_buffer
= sctx
->index_buffer
.user_buffer
;
933 ib
.index_size
= sctx
->index_buffer
.index_size
;
934 ib
.offset
= sctx
->index_buffer
.offset
;
936 /* Translate or upload, if needed. */
937 /* 8-bit indices are supported on VI. */
938 if (sctx
->b
.chip_class
<= CIK
&& ib
.index_size
== 1) {
939 struct pipe_resource
*out_buffer
= NULL
;
940 unsigned out_offset
, start
, count
, start_offset
;
943 si_get_draw_start_count(sctx
, info
, &start
, &count
);
944 start_offset
= start
* ib
.index_size
;
946 u_upload_alloc(sctx
->b
.uploader
, start_offset
, count
* 2, 256,
947 &out_offset
, &out_buffer
, &ptr
);
949 pipe_resource_reference(&ib
.buffer
, NULL
);
953 util_shorten_ubyte_elts_to_userptr(&sctx
->b
.b
, &ib
, 0,
954 ib
.offset
+ start_offset
,
957 pipe_resource_reference(&ib
.buffer
, NULL
);
958 ib
.user_buffer
= NULL
;
959 ib
.buffer
= out_buffer
;
960 /* info->start will be added by the drawing code */
961 ib
.offset
= out_offset
- start_offset
;
963 } else if (ib
.user_buffer
&& !ib
.buffer
) {
964 unsigned start
, count
, start_offset
;
966 si_get_draw_start_count(sctx
, info
, &start
, &count
);
967 start_offset
= start
* ib
.index_size
;
969 u_upload_data(sctx
->b
.uploader
, start_offset
, count
* ib
.index_size
,
970 256, (char*)ib
.user_buffer
+ start_offset
,
971 &ib
.offset
, &ib
.buffer
);
974 /* info->start will be added by the drawing code */
975 ib
.offset
-= start_offset
;
979 /* VI reads index buffers through TC L2. */
980 if (info
->indexed
&& sctx
->b
.chip_class
<= CIK
&&
981 r600_resource(ib
.buffer
)->TC_L2_dirty
) {
982 sctx
->b
.flags
|= SI_CONTEXT_INV_GLOBAL_L2
;
983 r600_resource(ib
.buffer
)->TC_L2_dirty
= false;
986 /* Check flush flags. */
988 si_mark_atom_dirty(sctx
, sctx
->atoms
.s
.cache_flush
);
990 si_need_cs_space(sctx
);
993 mask
= sctx
->dirty_atoms
;
995 struct r600_atom
*atom
= sctx
->atoms
.array
[u_bit_scan(&mask
)];
997 atom
->emit(&sctx
->b
, atom
);
999 sctx
->dirty_atoms
= 0;
1001 si_pm4_emit_dirty(sctx
);
1002 si_emit_scratch_reloc(sctx
);
1003 si_emit_rasterizer_prim_state(sctx
);
1004 si_emit_draw_registers(sctx
, info
);
1006 si_ce_pre_draw_synchronization(sctx
);
1008 si_emit_draw_packets(sctx
, info
, &ib
);
1010 si_ce_post_draw_synchronization(sctx
);
1012 if (sctx
->trace_buf
)
1013 si_trace_emit(sctx
);
1015 /* Workaround for a VGT hang when streamout is enabled.
1016 * It must be done after drawing. */
1017 if ((sctx
->b
.family
== CHIP_HAWAII
||
1018 sctx
->b
.family
== CHIP_TONGA
||
1019 sctx
->b
.family
== CHIP_FIJI
) &&
1020 r600_get_strmout_en(&sctx
->b
)) {
1021 sctx
->b
.flags
|= SI_CONTEXT_VGT_STREAMOUT_SYNC
;
1024 /* Set the depth buffer as dirty. */
1025 if (sctx
->framebuffer
.state
.zsbuf
) {
1026 struct pipe_surface
*surf
= sctx
->framebuffer
.state
.zsbuf
;
1027 struct r600_texture
*rtex
= (struct r600_texture
*)surf
->texture
;
1029 rtex
->dirty_level_mask
|= 1 << surf
->u
.tex
.level
;
1031 if (rtex
->surface
.flags
& RADEON_SURF_SBUFFER
)
1032 rtex
->stencil_dirty_level_mask
|= 1 << surf
->u
.tex
.level
;
1034 if (sctx
->framebuffer
.compressed_cb_mask
) {
1035 struct pipe_surface
*surf
;
1036 struct r600_texture
*rtex
;
1037 unsigned mask
= sctx
->framebuffer
.compressed_cb_mask
;
1040 unsigned i
= u_bit_scan(&mask
);
1041 surf
= sctx
->framebuffer
.state
.cbufs
[i
];
1042 rtex
= (struct r600_texture
*)surf
->texture
;
1044 rtex
->dirty_level_mask
|= 1 << surf
->u
.tex
.level
;
1048 pipe_resource_reference(&ib
.buffer
, NULL
);
1049 sctx
->b
.num_draw_calls
++;
1050 if (G_0286E8_WAVESIZE(sctx
->spi_tmpring_size
))
1051 sctx
->b
.num_spill_draw_calls
++;
1054 void si_trace_emit(struct si_context
*sctx
)
1056 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
1059 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
, sctx
->trace_buf
,
1060 RADEON_USAGE_READWRITE
, RADEON_PRIO_TRACE
);
1061 radeon_emit(cs
, PKT3(PKT3_WRITE_DATA
, 3, 0));
1062 radeon_emit(cs
, S_370_DST_SEL(V_370_MEMORY_SYNC
) |
1063 S_370_WR_CONFIRM(1) |
1064 S_370_ENGINE_SEL(V_370_ME
));
1065 radeon_emit(cs
, sctx
->trace_buf
->gpu_address
);
1066 radeon_emit(cs
, sctx
->trace_buf
->gpu_address
>> 32);
1067 radeon_emit(cs
, sctx
->trace_id
);
1068 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
1069 radeon_emit(cs
, SI_ENCODE_TRACE_POINT(sctx
->trace_id
));