2 * Copyright 2012 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 * Christian König <christian.koenig@amd.com>
28 #include "radeon/r600_cs.h"
31 #include "util/u_index_modify.h"
32 #include "util/u_upload_mgr.h"
33 #include "util/u_prim.h"
35 static unsigned si_conv_pipe_prim(unsigned mode
)
37 static const unsigned prim_conv
[] = {
38 [PIPE_PRIM_POINTS
] = V_008958_DI_PT_POINTLIST
,
39 [PIPE_PRIM_LINES
] = V_008958_DI_PT_LINELIST
,
40 [PIPE_PRIM_LINE_LOOP
] = V_008958_DI_PT_LINELOOP
,
41 [PIPE_PRIM_LINE_STRIP
] = V_008958_DI_PT_LINESTRIP
,
42 [PIPE_PRIM_TRIANGLES
] = V_008958_DI_PT_TRILIST
,
43 [PIPE_PRIM_TRIANGLE_STRIP
] = V_008958_DI_PT_TRISTRIP
,
44 [PIPE_PRIM_TRIANGLE_FAN
] = V_008958_DI_PT_TRIFAN
,
45 [PIPE_PRIM_QUADS
] = V_008958_DI_PT_QUADLIST
,
46 [PIPE_PRIM_QUAD_STRIP
] = V_008958_DI_PT_QUADSTRIP
,
47 [PIPE_PRIM_POLYGON
] = V_008958_DI_PT_POLYGON
,
48 [PIPE_PRIM_LINES_ADJACENCY
] = V_008958_DI_PT_LINELIST_ADJ
,
49 [PIPE_PRIM_LINE_STRIP_ADJACENCY
] = V_008958_DI_PT_LINESTRIP_ADJ
,
50 [PIPE_PRIM_TRIANGLES_ADJACENCY
] = V_008958_DI_PT_TRILIST_ADJ
,
51 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY
] = V_008958_DI_PT_TRISTRIP_ADJ
,
52 [PIPE_PRIM_PATCHES
] = V_008958_DI_PT_PATCH
,
53 [R600_PRIM_RECTANGLE_LIST
] = V_008958_DI_PT_RECTLIST
55 assert(mode
< ARRAY_SIZE(prim_conv
));
56 return prim_conv
[mode
];
59 static unsigned si_conv_prim_to_gs_out(unsigned mode
)
61 static const int prim_conv
[] = {
62 [PIPE_PRIM_POINTS
] = V_028A6C_OUTPRIM_TYPE_POINTLIST
,
63 [PIPE_PRIM_LINES
] = V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
64 [PIPE_PRIM_LINE_LOOP
] = V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
65 [PIPE_PRIM_LINE_STRIP
] = V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
66 [PIPE_PRIM_TRIANGLES
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
67 [PIPE_PRIM_TRIANGLE_STRIP
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
68 [PIPE_PRIM_TRIANGLE_FAN
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
69 [PIPE_PRIM_QUADS
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
70 [PIPE_PRIM_QUAD_STRIP
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
71 [PIPE_PRIM_POLYGON
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
72 [PIPE_PRIM_LINES_ADJACENCY
] = V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
73 [PIPE_PRIM_LINE_STRIP_ADJACENCY
] = V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
74 [PIPE_PRIM_TRIANGLES_ADJACENCY
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
75 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
76 [PIPE_PRIM_PATCHES
] = V_028A6C_OUTPRIM_TYPE_POINTLIST
,
77 [R600_PRIM_RECTANGLE_LIST
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
79 assert(mode
< ARRAY_SIZE(prim_conv
));
81 return prim_conv
[mode
];
85 * This calculates the LDS size for tessellation shaders (VS, TCS, TES).
86 * LS.LDS_SIZE is shared by all 3 shader stages.
88 * The information about LDS and other non-compile-time parameters is then
89 * written to userdata SGPRs.
91 static void si_emit_derived_tess_state(struct si_context
*sctx
,
92 const struct pipe_draw_info
*info
,
93 unsigned *num_patches
)
95 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
96 struct si_shader_ctx_state
*ls
= &sctx
->vs_shader
;
97 /* The TES pointer will only be used for sctx->last_tcs.
98 * It would be wrong to think that TCS = TES. */
99 struct si_shader_selector
*tcs
=
100 sctx
->tcs_shader
.cso
? sctx
->tcs_shader
.cso
: sctx
->tes_shader
.cso
;
101 unsigned tes_sh_base
= sctx
->shader_userdata
.sh_base
[PIPE_SHADER_TESS_EVAL
];
102 unsigned num_tcs_input_cp
= info
->vertices_per_patch
;
103 unsigned num_tcs_output_cp
, num_tcs_inputs
, num_tcs_outputs
;
104 unsigned num_tcs_patch_outputs
;
105 unsigned input_vertex_size
, output_vertex_size
, pervertex_output_patch_size
;
106 unsigned input_patch_size
, output_patch_size
, output_patch0_offset
;
107 unsigned perpatch_output_offset
, lds_size
, ls_rsrc2
;
108 unsigned tcs_in_layout
, tcs_out_layout
, tcs_out_offsets
;
109 unsigned offchip_layout
, hardware_lds_size
, ls_hs_config
;
111 /* This calculates how shader inputs and outputs among VS, TCS, and TES
112 * are laid out in LDS. */
113 num_tcs_inputs
= util_last_bit64(ls
->cso
->outputs_written
);
115 if (sctx
->tcs_shader
.cso
) {
116 num_tcs_outputs
= util_last_bit64(tcs
->outputs_written
);
117 num_tcs_output_cp
= tcs
->info
.properties
[TGSI_PROPERTY_TCS_VERTICES_OUT
];
118 num_tcs_patch_outputs
= util_last_bit64(tcs
->patch_outputs_written
);
120 /* No TCS. Route varyings from LS to TES. */
121 num_tcs_outputs
= num_tcs_inputs
;
122 num_tcs_output_cp
= num_tcs_input_cp
;
123 num_tcs_patch_outputs
= 2; /* TESSINNER + TESSOUTER */
126 input_vertex_size
= num_tcs_inputs
* 16;
127 output_vertex_size
= num_tcs_outputs
* 16;
129 input_patch_size
= num_tcs_input_cp
* input_vertex_size
;
131 pervertex_output_patch_size
= num_tcs_output_cp
* output_vertex_size
;
132 output_patch_size
= pervertex_output_patch_size
+ num_tcs_patch_outputs
* 16;
134 /* Ensure that we only need one wave per SIMD so we don't need to check
135 * resource usage. Also ensures that the number of tcs in and out
136 * vertices per threadgroup are at most 256.
138 *num_patches
= 64 / MAX2(num_tcs_input_cp
, num_tcs_output_cp
) * 4;
140 /* Make sure that the data fits in LDS. This assumes the shaders only
141 * use LDS for the inputs and outputs.
143 hardware_lds_size
= sctx
->b
.chip_class
>= CIK
? 65536 : 32768;
144 *num_patches
= MIN2(*num_patches
, hardware_lds_size
/ (input_patch_size
+
147 /* Make sure the output data fits in the offchip buffer */
148 *num_patches
= MIN2(*num_patches
,
149 (sctx
->screen
->tess_offchip_block_dw_size
* 4) /
152 /* Not necessary for correctness, but improves performance. The
153 * specific value is taken from the proprietary driver.
155 *num_patches
= MIN2(*num_patches
, 40);
157 output_patch0_offset
= input_patch_size
* *num_patches
;
158 perpatch_output_offset
= output_patch0_offset
+ pervertex_output_patch_size
;
160 lds_size
= output_patch0_offset
+ output_patch_size
* *num_patches
;
161 ls_rsrc2
= ls
->current
->config
.rsrc2
;
163 if (sctx
->b
.chip_class
>= CIK
) {
164 assert(lds_size
<= 65536);
165 ls_rsrc2
|= S_00B52C_LDS_SIZE(align(lds_size
, 512) / 512);
167 assert(lds_size
<= 32768);
168 ls_rsrc2
|= S_00B52C_LDS_SIZE(align(lds_size
, 256) / 256);
171 if (sctx
->last_ls
== ls
->current
&&
172 sctx
->last_tcs
== tcs
&&
173 sctx
->last_tes_sh_base
== tes_sh_base
&&
174 sctx
->last_num_tcs_input_cp
== num_tcs_input_cp
)
177 sctx
->last_ls
= ls
->current
;
178 sctx
->last_tcs
= tcs
;
179 sctx
->last_tes_sh_base
= tes_sh_base
;
180 sctx
->last_num_tcs_input_cp
= num_tcs_input_cp
;
182 /* Due to a hw bug, RSRC2_LS must be written twice with another
183 * LS register written in between. */
184 if (sctx
->b
.chip_class
== CIK
&& sctx
->b
.family
!= CHIP_HAWAII
)
185 radeon_set_sh_reg(cs
, R_00B52C_SPI_SHADER_PGM_RSRC2_LS
, ls_rsrc2
);
186 radeon_set_sh_reg_seq(cs
, R_00B528_SPI_SHADER_PGM_RSRC1_LS
, 2);
187 radeon_emit(cs
, ls
->current
->config
.rsrc1
);
188 radeon_emit(cs
, ls_rsrc2
);
190 /* Compute userdata SGPRs. */
191 assert(((input_vertex_size
/ 4) & ~0xff) == 0);
192 assert(((output_vertex_size
/ 4) & ~0xff) == 0);
193 assert(((input_patch_size
/ 4) & ~0x1fff) == 0);
194 assert(((output_patch_size
/ 4) & ~0x1fff) == 0);
195 assert(((output_patch0_offset
/ 16) & ~0xffff) == 0);
196 assert(((perpatch_output_offset
/ 16) & ~0xffff) == 0);
197 assert(num_tcs_input_cp
<= 32);
198 assert(num_tcs_output_cp
<= 32);
200 tcs_in_layout
= (input_patch_size
/ 4) |
201 ((input_vertex_size
/ 4) << 13);
202 tcs_out_layout
= (output_patch_size
/ 4) |
203 ((output_vertex_size
/ 4) << 13);
204 tcs_out_offsets
= (output_patch0_offset
/ 16) |
205 ((perpatch_output_offset
/ 16) << 16);
206 offchip_layout
= (pervertex_output_patch_size
* *num_patches
<< 16) |
207 (num_tcs_output_cp
<< 9) | *num_patches
;
209 /* Set them for LS. */
210 radeon_set_sh_reg(cs
,
211 R_00B530_SPI_SHADER_USER_DATA_LS_0
+ SI_SGPR_LS_OUT_LAYOUT
* 4,
214 /* Set them for TCS. */
215 radeon_set_sh_reg_seq(cs
,
216 R_00B430_SPI_SHADER_USER_DATA_HS_0
+ SI_SGPR_TCS_OFFCHIP_LAYOUT
* 4, 4);
217 radeon_emit(cs
, offchip_layout
);
218 radeon_emit(cs
, tcs_out_offsets
);
219 radeon_emit(cs
, tcs_out_layout
| (num_tcs_input_cp
<< 26));
220 radeon_emit(cs
, tcs_in_layout
);
222 /* Set them for TES. */
223 radeon_set_sh_reg_seq(cs
, tes_sh_base
+ SI_SGPR_TCS_OFFCHIP_LAYOUT
* 4, 1);
224 radeon_emit(cs
, offchip_layout
);
226 ls_hs_config
= S_028B58_NUM_PATCHES(*num_patches
) |
227 S_028B58_HS_NUM_INPUT_CP(num_tcs_input_cp
) |
228 S_028B58_HS_NUM_OUTPUT_CP(num_tcs_output_cp
);
230 if (sctx
->b
.chip_class
>= CIK
)
231 radeon_set_context_reg_idx(cs
, R_028B58_VGT_LS_HS_CONFIG
, 2,
234 radeon_set_context_reg(cs
, R_028B58_VGT_LS_HS_CONFIG
,
238 static unsigned si_num_prims_for_vertices(const struct pipe_draw_info
*info
)
240 switch (info
->mode
) {
241 case PIPE_PRIM_PATCHES
:
242 return info
->count
/ info
->vertices_per_patch
;
243 case R600_PRIM_RECTANGLE_LIST
:
244 return info
->count
/ 3;
246 return u_prims_for_vertices(info
->mode
, info
->count
);
250 static unsigned si_get_ia_multi_vgt_param(struct si_context
*sctx
,
251 const struct pipe_draw_info
*info
,
252 unsigned num_patches
)
254 struct si_state_rasterizer
*rs
= sctx
->queued
.named
.rasterizer
;
255 unsigned prim
= info
->mode
;
256 unsigned primgroup_size
= 128; /* recommended without a GS */
257 unsigned max_primgroup_in_wave
= 2;
259 /* SWITCH_ON_EOP(0) is always preferable. */
260 bool wd_switch_on_eop
= false;
261 bool ia_switch_on_eop
= false;
262 bool ia_switch_on_eoi
= false;
263 bool partial_vs_wave
= false;
264 bool partial_es_wave
= false;
266 if (sctx
->gs_shader
.cso
)
267 primgroup_size
= 64; /* recommended with a GS */
269 if (sctx
->tes_shader
.cso
) {
270 /* primgroup_size must be set to a multiple of NUM_PATCHES */
271 primgroup_size
= num_patches
;
273 /* SWITCH_ON_EOI must be set if PrimID is used. */
274 if ((sctx
->tcs_shader
.cso
&& sctx
->tcs_shader
.cso
->info
.uses_primid
) ||
275 sctx
->tes_shader
.cso
->info
.uses_primid
)
276 ia_switch_on_eoi
= true;
278 /* Bug with tessellation and GS on Bonaire and older 2 SE chips. */
279 if ((sctx
->b
.family
== CHIP_TAHITI
||
280 sctx
->b
.family
== CHIP_PITCAIRN
||
281 sctx
->b
.family
== CHIP_BONAIRE
) &&
283 partial_vs_wave
= true;
285 /* Needed for 028B6C_DISTRIBUTION_MODE != 0 */
286 if (sctx
->screen
->has_distributed_tess
) {
287 if (sctx
->gs_shader
.cso
)
288 partial_es_wave
= true;
290 partial_vs_wave
= true;
294 /* This is a hardware requirement. */
295 if ((rs
&& rs
->line_stipple_enable
) ||
296 (sctx
->b
.screen
->debug_flags
& DBG_SWITCH_ON_EOP
)) {
297 ia_switch_on_eop
= true;
298 wd_switch_on_eop
= true;
301 if (sctx
->b
.chip_class
>= CIK
) {
302 /* WD_SWITCH_ON_EOP has no effect on GPUs with less than
303 * 4 shader engines. Set 1 to pass the assertion below.
304 * The other cases are hardware requirements.
306 * Polaris supports primitive restart with WD_SWITCH_ON_EOP=0
307 * for points, line strips, and tri strips.
309 if (sctx
->b
.screen
->info
.max_se
< 4 ||
310 prim
== PIPE_PRIM_POLYGON
||
311 prim
== PIPE_PRIM_LINE_LOOP
||
312 prim
== PIPE_PRIM_TRIANGLE_FAN
||
313 prim
== PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY
||
314 (info
->primitive_restart
&&
315 (sctx
->b
.family
< CHIP_POLARIS10
||
316 (prim
!= PIPE_PRIM_POINTS
&&
317 prim
!= PIPE_PRIM_LINE_STRIP
&&
318 prim
!= PIPE_PRIM_TRIANGLE_STRIP
))) ||
319 info
->count_from_stream_output
)
320 wd_switch_on_eop
= true;
322 /* Hawaii hangs if instancing is enabled and WD_SWITCH_ON_EOP is 0.
323 * We don't know that for indirect drawing, so treat it as
324 * always problematic. */
325 if (sctx
->b
.family
== CHIP_HAWAII
&&
326 (info
->indirect
|| info
->instance_count
> 1))
327 wd_switch_on_eop
= true;
329 /* Performance recommendation for 4 SE Gfx7-8 parts if
330 * instances are smaller than a primgroup.
331 * Assume indirect draws always use small instances.
332 * This is needed for good VS wave utilization.
334 if (sctx
->b
.chip_class
<= VI
&&
335 sctx
->b
.screen
->info
.max_se
>= 4 &&
337 (info
->instance_count
> 1 &&
338 si_num_prims_for_vertices(info
) < primgroup_size
)))
339 wd_switch_on_eop
= true;
341 /* Required on CIK and later. */
342 if (sctx
->b
.screen
->info
.max_se
> 2 && !wd_switch_on_eop
)
343 ia_switch_on_eoi
= true;
345 /* Required by Hawaii and, for some special cases, by VI. */
346 if (ia_switch_on_eoi
&&
347 (sctx
->b
.family
== CHIP_HAWAII
||
348 (sctx
->b
.chip_class
== VI
&&
349 (sctx
->gs_shader
.cso
|| max_primgroup_in_wave
!= 2))))
350 partial_vs_wave
= true;
352 /* Instancing bug on Bonaire. */
353 if (sctx
->b
.family
== CHIP_BONAIRE
&& ia_switch_on_eoi
&&
354 (info
->indirect
|| info
->instance_count
> 1))
355 partial_vs_wave
= true;
357 /* GS hw bug with single-primitive instances and SWITCH_ON_EOI.
358 * The hw doc says all multi-SE chips are affected, but Vulkan
359 * only applies it to Hawaii. Do what Vulkan does.
361 if (sctx
->b
.family
== CHIP_HAWAII
&&
362 sctx
->gs_shader
.cso
&&
365 (info
->instance_count
> 1 &&
366 si_num_prims_for_vertices(info
) <= 1)))
367 sctx
->b
.flags
|= SI_CONTEXT_VGT_FLUSH
;
370 /* If the WD switch is false, the IA switch must be false too. */
371 assert(wd_switch_on_eop
|| !ia_switch_on_eop
);
374 /* If SWITCH_ON_EOI is set, PARTIAL_ES_WAVE must be set too. */
375 if (ia_switch_on_eoi
)
376 partial_es_wave
= true;
378 /* GS requirement. */
379 if (SI_GS_PER_ES
/ primgroup_size
>= sctx
->screen
->gs_table_depth
- 3)
380 partial_es_wave
= true;
382 return S_028AA8_SWITCH_ON_EOP(ia_switch_on_eop
) |
383 S_028AA8_SWITCH_ON_EOI(ia_switch_on_eoi
) |
384 S_028AA8_PARTIAL_VS_WAVE_ON(partial_vs_wave
) |
385 S_028AA8_PARTIAL_ES_WAVE_ON(partial_es_wave
) |
386 S_028AA8_PRIMGROUP_SIZE(primgroup_size
- 1) |
387 S_028AA8_WD_SWITCH_ON_EOP(sctx
->b
.chip_class
>= CIK
? wd_switch_on_eop
: 0) |
388 S_028AA8_MAX_PRIMGRP_IN_WAVE(sctx
->b
.chip_class
>= VI
?
389 max_primgroup_in_wave
: 0);
392 static void si_emit_scratch_reloc(struct si_context
*sctx
)
394 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
396 if (!sctx
->emit_scratch_reloc
)
399 radeon_set_context_reg(cs
, R_0286E8_SPI_TMPRING_SIZE
,
400 sctx
->spi_tmpring_size
);
402 if (sctx
->scratch_buffer
) {
403 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
,
404 sctx
->scratch_buffer
, RADEON_USAGE_READWRITE
,
405 RADEON_PRIO_SCRATCH_BUFFER
);
408 sctx
->emit_scratch_reloc
= false;
411 /* rast_prim is the primitive type after GS. */
412 static void si_emit_rasterizer_prim_state(struct si_context
*sctx
)
414 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
415 unsigned rast_prim
= sctx
->current_rast_prim
;
416 struct si_state_rasterizer
*rs
= sctx
->emitted
.named
.rasterizer
;
418 /* Skip this if not rendering lines. */
419 if (rast_prim
!= PIPE_PRIM_LINES
&&
420 rast_prim
!= PIPE_PRIM_LINE_LOOP
&&
421 rast_prim
!= PIPE_PRIM_LINE_STRIP
&&
422 rast_prim
!= PIPE_PRIM_LINES_ADJACENCY
&&
423 rast_prim
!= PIPE_PRIM_LINE_STRIP_ADJACENCY
)
426 if (rast_prim
== sctx
->last_rast_prim
&&
427 rs
->pa_sc_line_stipple
== sctx
->last_sc_line_stipple
)
430 /* For lines, reset the stipple pattern at each primitive. Otherwise,
431 * reset the stipple pattern at each packet (line strips, line loops).
433 radeon_set_context_reg(cs
, R_028A0C_PA_SC_LINE_STIPPLE
,
434 rs
->pa_sc_line_stipple
|
435 S_028A0C_AUTO_RESET_CNTL(rast_prim
== PIPE_PRIM_LINES
? 1 : 2));
437 sctx
->last_rast_prim
= rast_prim
;
438 sctx
->last_sc_line_stipple
= rs
->pa_sc_line_stipple
;
441 static void si_emit_draw_registers(struct si_context
*sctx
,
442 const struct pipe_draw_info
*info
)
444 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
445 unsigned prim
= si_conv_pipe_prim(info
->mode
);
446 unsigned gs_out_prim
= si_conv_prim_to_gs_out(sctx
->current_rast_prim
);
447 unsigned ia_multi_vgt_param
, num_patches
= 0;
449 /* Polaris needs different VTX_REUSE_DEPTH settings depending on
450 * whether the "fractional odd" tessellation spacing is used.
452 if (sctx
->b
.family
>= CHIP_POLARIS10
) {
453 struct si_shader_selector
*tes
= sctx
->tes_shader
.cso
;
454 unsigned vtx_reuse_depth
= 30;
457 tes
->info
.properties
[TGSI_PROPERTY_TES_SPACING
] ==
458 PIPE_TESS_SPACING_FRACTIONAL_ODD
)
459 vtx_reuse_depth
= 14;
461 if (vtx_reuse_depth
!= sctx
->last_vtx_reuse_depth
) {
462 radeon_set_context_reg(cs
, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL
,
464 sctx
->last_vtx_reuse_depth
= vtx_reuse_depth
;
468 if (sctx
->tes_shader
.cso
)
469 si_emit_derived_tess_state(sctx
, info
, &num_patches
);
471 ia_multi_vgt_param
= si_get_ia_multi_vgt_param(sctx
, info
, num_patches
);
474 if (ia_multi_vgt_param
!= sctx
->last_multi_vgt_param
) {
475 if (sctx
->b
.chip_class
>= CIK
)
476 radeon_set_context_reg_idx(cs
, R_028AA8_IA_MULTI_VGT_PARAM
, 1, ia_multi_vgt_param
);
478 radeon_set_context_reg(cs
, R_028AA8_IA_MULTI_VGT_PARAM
, ia_multi_vgt_param
);
480 sctx
->last_multi_vgt_param
= ia_multi_vgt_param
;
482 if (prim
!= sctx
->last_prim
) {
483 if (sctx
->b
.chip_class
>= CIK
)
484 radeon_set_uconfig_reg_idx(cs
, R_030908_VGT_PRIMITIVE_TYPE
, 1, prim
);
486 radeon_set_config_reg(cs
, R_008958_VGT_PRIMITIVE_TYPE
, prim
);
488 sctx
->last_prim
= prim
;
491 if (gs_out_prim
!= sctx
->last_gs_out_prim
) {
492 radeon_set_context_reg(cs
, R_028A6C_VGT_GS_OUT_PRIM_TYPE
, gs_out_prim
);
493 sctx
->last_gs_out_prim
= gs_out_prim
;
496 /* Primitive restart. */
497 if (info
->primitive_restart
!= sctx
->last_primitive_restart_en
) {
498 radeon_set_context_reg(cs
, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN
, info
->primitive_restart
);
499 sctx
->last_primitive_restart_en
= info
->primitive_restart
;
502 if (info
->primitive_restart
&&
503 (info
->restart_index
!= sctx
->last_restart_index
||
504 sctx
->last_restart_index
== SI_RESTART_INDEX_UNKNOWN
)) {
505 radeon_set_context_reg(cs
, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX
,
506 info
->restart_index
);
507 sctx
->last_restart_index
= info
->restart_index
;
511 static void si_emit_draw_packets(struct si_context
*sctx
,
512 const struct pipe_draw_info
*info
,
513 const struct pipe_index_buffer
*ib
)
515 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
516 unsigned sh_base_reg
= sctx
->shader_userdata
.sh_base
[PIPE_SHADER_VERTEX
];
517 bool render_cond_bit
= sctx
->b
.render_cond
&& !sctx
->b
.render_cond_force_off
;
518 uint32_t index_max_size
= 0;
519 uint64_t index_va
= 0;
521 if (info
->count_from_stream_output
) {
522 struct r600_so_target
*t
=
523 (struct r600_so_target
*)info
->count_from_stream_output
;
524 uint64_t va
= t
->buf_filled_size
->gpu_address
+
525 t
->buf_filled_size_offset
;
527 radeon_set_context_reg(cs
, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE
,
530 radeon_emit(cs
, PKT3(PKT3_COPY_DATA
, 4, 0));
531 radeon_emit(cs
, COPY_DATA_SRC_SEL(COPY_DATA_MEM
) |
532 COPY_DATA_DST_SEL(COPY_DATA_REG
) |
533 COPY_DATA_WR_CONFIRM
);
534 radeon_emit(cs
, va
); /* src address lo */
535 radeon_emit(cs
, va
>> 32); /* src address hi */
536 radeon_emit(cs
, R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE
>> 2);
537 radeon_emit(cs
, 0); /* unused */
539 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
,
540 t
->buf_filled_size
, RADEON_USAGE_READ
,
541 RADEON_PRIO_SO_FILLED_SIZE
);
546 if (ib
->index_size
!= sctx
->last_index_size
) {
547 radeon_emit(cs
, PKT3(PKT3_INDEX_TYPE
, 0, 0));
550 switch (ib
->index_size
) {
552 radeon_emit(cs
, V_028A7C_VGT_INDEX_8
);
555 radeon_emit(cs
, V_028A7C_VGT_INDEX_16
|
556 (SI_BIG_ENDIAN
&& sctx
->b
.chip_class
<= CIK
?
557 V_028A7C_VGT_DMA_SWAP_16_BIT
: 0));
560 radeon_emit(cs
, V_028A7C_VGT_INDEX_32
|
561 (SI_BIG_ENDIAN
&& sctx
->b
.chip_class
<= CIK
?
562 V_028A7C_VGT_DMA_SWAP_32_BIT
: 0));
565 assert(!"unreachable");
569 sctx
->last_index_size
= ib
->index_size
;
572 index_max_size
= (ib
->buffer
->width0
- ib
->offset
) /
574 index_va
= r600_resource(ib
->buffer
)->gpu_address
+ ib
->offset
;
576 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
,
577 (struct r600_resource
*)ib
->buffer
,
578 RADEON_USAGE_READ
, RADEON_PRIO_INDEX_BUFFER
);
580 /* On CI and later, non-indexed draws overwrite VGT_INDEX_TYPE,
581 * so the state must be re-emitted before the next indexed draw.
583 if (sctx
->b
.chip_class
>= CIK
)
584 sctx
->last_index_size
= -1;
587 if (!info
->indirect
) {
590 radeon_emit(cs
, PKT3(PKT3_NUM_INSTANCES
, 0, 0));
591 radeon_emit(cs
, info
->instance_count
);
593 /* Base vertex and start instance. */
594 base_vertex
= info
->indexed
? info
->index_bias
: info
->start
;
596 if (base_vertex
!= sctx
->last_base_vertex
||
597 sctx
->last_base_vertex
== SI_BASE_VERTEX_UNKNOWN
||
598 info
->start_instance
!= sctx
->last_start_instance
||
599 info
->drawid
!= sctx
->last_drawid
||
600 sh_base_reg
!= sctx
->last_sh_base_reg
) {
601 radeon_set_sh_reg_seq(cs
, sh_base_reg
+ SI_SGPR_BASE_VERTEX
* 4, 3);
602 radeon_emit(cs
, base_vertex
);
603 radeon_emit(cs
, info
->start_instance
);
604 radeon_emit(cs
, info
->drawid
);
606 sctx
->last_base_vertex
= base_vertex
;
607 sctx
->last_start_instance
= info
->start_instance
;
608 sctx
->last_drawid
= info
->drawid
;
609 sctx
->last_sh_base_reg
= sh_base_reg
;
612 uint64_t indirect_va
= r600_resource(info
->indirect
)->gpu_address
;
614 assert(indirect_va
% 8 == 0);
616 si_invalidate_draw_sh_constants(sctx
);
618 radeon_emit(cs
, PKT3(PKT3_SET_BASE
, 2, 0));
620 radeon_emit(cs
, indirect_va
);
621 radeon_emit(cs
, indirect_va
>> 32);
623 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
,
624 (struct r600_resource
*)info
->indirect
,
625 RADEON_USAGE_READ
, RADEON_PRIO_DRAW_INDIRECT
);
628 if (info
->indirect
) {
629 unsigned di_src_sel
= info
->indexed
? V_0287F0_DI_SRC_SEL_DMA
630 : V_0287F0_DI_SRC_SEL_AUTO_INDEX
;
632 assert(info
->indirect_offset
% 4 == 0);
635 radeon_emit(cs
, PKT3(PKT3_INDEX_BASE
, 1, 0));
636 radeon_emit(cs
, index_va
);
637 radeon_emit(cs
, index_va
>> 32);
639 radeon_emit(cs
, PKT3(PKT3_INDEX_BUFFER_SIZE
, 0, 0));
640 radeon_emit(cs
, index_max_size
);
643 if (!sctx
->screen
->has_draw_indirect_multi
) {
644 radeon_emit(cs
, PKT3(info
->indexed
? PKT3_DRAW_INDEX_INDIRECT
645 : PKT3_DRAW_INDIRECT
,
646 3, render_cond_bit
));
647 radeon_emit(cs
, info
->indirect_offset
);
648 radeon_emit(cs
, (sh_base_reg
+ SI_SGPR_BASE_VERTEX
* 4 - SI_SH_REG_OFFSET
) >> 2);
649 radeon_emit(cs
, (sh_base_reg
+ SI_SGPR_START_INSTANCE
* 4 - SI_SH_REG_OFFSET
) >> 2);
650 radeon_emit(cs
, di_src_sel
);
652 uint64_t count_va
= 0;
654 if (info
->indirect_params
) {
655 struct r600_resource
*params_buf
=
656 (struct r600_resource
*)info
->indirect_params
;
658 radeon_add_to_buffer_list(
659 &sctx
->b
, &sctx
->b
.gfx
, params_buf
,
660 RADEON_USAGE_READ
, RADEON_PRIO_DRAW_INDIRECT
);
662 count_va
= params_buf
->gpu_address
+ info
->indirect_params_offset
;
665 radeon_emit(cs
, PKT3(info
->indexed
? PKT3_DRAW_INDEX_INDIRECT_MULTI
:
666 PKT3_DRAW_INDIRECT_MULTI
,
667 8, render_cond_bit
));
668 radeon_emit(cs
, info
->indirect_offset
);
669 radeon_emit(cs
, (sh_base_reg
+ SI_SGPR_BASE_VERTEX
* 4 - SI_SH_REG_OFFSET
) >> 2);
670 radeon_emit(cs
, (sh_base_reg
+ SI_SGPR_START_INSTANCE
* 4 - SI_SH_REG_OFFSET
) >> 2);
671 radeon_emit(cs
, ((sh_base_reg
+ SI_SGPR_DRAWID
* 4 - SI_SH_REG_OFFSET
) >> 2) |
672 S_2C3_DRAW_INDEX_ENABLE(1) |
673 S_2C3_COUNT_INDIRECT_ENABLE(!!info
->indirect_params
));
674 radeon_emit(cs
, info
->indirect_count
);
675 radeon_emit(cs
, count_va
);
676 radeon_emit(cs
, count_va
>> 32);
677 radeon_emit(cs
, info
->indirect_stride
);
678 radeon_emit(cs
, di_src_sel
);
682 index_va
+= info
->start
* ib
->index_size
;
684 radeon_emit(cs
, PKT3(PKT3_DRAW_INDEX_2
, 4, render_cond_bit
));
685 radeon_emit(cs
, index_max_size
);
686 radeon_emit(cs
, index_va
);
687 radeon_emit(cs
, (index_va
>> 32UL) & 0xFF);
688 radeon_emit(cs
, info
->count
);
689 radeon_emit(cs
, V_0287F0_DI_SRC_SEL_DMA
);
691 radeon_emit(cs
, PKT3(PKT3_DRAW_INDEX_AUTO
, 1, render_cond_bit
));
692 radeon_emit(cs
, info
->count
);
693 radeon_emit(cs
, V_0287F0_DI_SRC_SEL_AUTO_INDEX
|
694 S_0287F0_USE_OPAQUE(!!info
->count_from_stream_output
));
699 static void si_emit_surface_sync(struct r600_common_context
*rctx
,
700 unsigned cp_coher_cntl
)
702 struct radeon_winsys_cs
*cs
= rctx
->gfx
.cs
;
704 /* ACQUIRE_MEM is only required on a compute ring. */
705 radeon_emit(cs
, PKT3(PKT3_SURFACE_SYNC
, 3, 0));
706 radeon_emit(cs
, cp_coher_cntl
); /* CP_COHER_CNTL */
707 radeon_emit(cs
, 0xffffffff); /* CP_COHER_SIZE */
708 radeon_emit(cs
, 0); /* CP_COHER_BASE */
709 radeon_emit(cs
, 0x0000000A); /* POLL_INTERVAL */
712 void si_emit_cache_flush(struct si_context
*sctx
)
714 struct r600_common_context
*rctx
= &sctx
->b
;
715 struct radeon_winsys_cs
*cs
= rctx
->gfx
.cs
;
716 uint32_t cp_coher_cntl
= 0;
718 /* SI has a bug that it always flushes ICACHE and KCACHE if either
719 * bit is set. An alternative way is to write SQC_CACHES, but that
720 * doesn't seem to work reliably. Since the bug doesn't affect
721 * correctness (it only does more work than necessary) and
722 * the performance impact is likely negligible, there is no plan
723 * to add a workaround for it.
726 if (rctx
->flags
& SI_CONTEXT_INV_ICACHE
)
727 cp_coher_cntl
|= S_0085F0_SH_ICACHE_ACTION_ENA(1);
728 if (rctx
->flags
& SI_CONTEXT_INV_SMEM_L1
)
729 cp_coher_cntl
|= S_0085F0_SH_KCACHE_ACTION_ENA(1);
731 if (rctx
->flags
& SI_CONTEXT_FLUSH_AND_INV_CB
) {
732 cp_coher_cntl
|= S_0085F0_CB_ACTION_ENA(1) |
733 S_0085F0_CB0_DEST_BASE_ENA(1) |
734 S_0085F0_CB1_DEST_BASE_ENA(1) |
735 S_0085F0_CB2_DEST_BASE_ENA(1) |
736 S_0085F0_CB3_DEST_BASE_ENA(1) |
737 S_0085F0_CB4_DEST_BASE_ENA(1) |
738 S_0085F0_CB5_DEST_BASE_ENA(1) |
739 S_0085F0_CB6_DEST_BASE_ENA(1) |
740 S_0085F0_CB7_DEST_BASE_ENA(1);
742 /* Necessary for DCC */
743 if (rctx
->chip_class
>= VI
) {
744 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE_EOP
, 4, 0));
745 radeon_emit(cs
, EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_DATA_TS
) |
753 if (rctx
->flags
& SI_CONTEXT_FLUSH_AND_INV_DB
) {
754 cp_coher_cntl
|= S_0085F0_DB_ACTION_ENA(1) |
755 S_0085F0_DB_DEST_BASE_ENA(1);
758 if (rctx
->flags
& SI_CONTEXT_FLUSH_AND_INV_CB_META
) {
759 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
760 radeon_emit(cs
, EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_META
) | EVENT_INDEX(0));
761 /* needed for wait for idle in SURFACE_SYNC */
762 assert(rctx
->flags
& SI_CONTEXT_FLUSH_AND_INV_CB
);
764 if (rctx
->flags
& SI_CONTEXT_FLUSH_AND_INV_DB_META
) {
765 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
766 radeon_emit(cs
, EVENT_TYPE(V_028A90_FLUSH_AND_INV_DB_META
) | EVENT_INDEX(0));
767 /* needed for wait for idle in SURFACE_SYNC */
768 assert(rctx
->flags
& SI_CONTEXT_FLUSH_AND_INV_DB
);
771 /* Wait for shader engines to go idle.
772 * VS and PS waits are unnecessary if SURFACE_SYNC is going to wait
773 * for everything including CB/DB cache flushes.
775 if (!(rctx
->flags
& (SI_CONTEXT_FLUSH_AND_INV_CB
|
776 SI_CONTEXT_FLUSH_AND_INV_DB
))) {
777 if (rctx
->flags
& SI_CONTEXT_PS_PARTIAL_FLUSH
) {
778 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
779 radeon_emit(cs
, EVENT_TYPE(V_028A90_PS_PARTIAL_FLUSH
) | EVENT_INDEX(4));
780 /* Only count explicit shader flushes, not implicit ones
781 * done by SURFACE_SYNC.
783 rctx
->num_vs_flushes
++;
784 rctx
->num_ps_flushes
++;
785 } else if (rctx
->flags
& SI_CONTEXT_VS_PARTIAL_FLUSH
) {
786 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
787 radeon_emit(cs
, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH
) | EVENT_INDEX(4));
788 rctx
->num_vs_flushes
++;
792 if (rctx
->flags
& SI_CONTEXT_CS_PARTIAL_FLUSH
&&
793 sctx
->compute_is_busy
) {
794 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
795 radeon_emit(cs
, EVENT_TYPE(V_028A90_CS_PARTIAL_FLUSH
| EVENT_INDEX(4)));
796 rctx
->num_cs_flushes
++;
797 sctx
->compute_is_busy
= false;
800 /* VGT state synchronization. */
801 if (rctx
->flags
& SI_CONTEXT_VGT_FLUSH
) {
802 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
803 radeon_emit(cs
, EVENT_TYPE(V_028A90_VGT_FLUSH
) | EVENT_INDEX(0));
805 if (rctx
->flags
& SI_CONTEXT_VGT_STREAMOUT_SYNC
) {
806 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
807 radeon_emit(cs
, EVENT_TYPE(V_028A90_VGT_STREAMOUT_SYNC
) | EVENT_INDEX(0));
810 /* Make sure ME is idle (it executes most packets) before continuing.
811 * This prevents read-after-write hazards between PFP and ME.
814 (rctx
->flags
& (SI_CONTEXT_CS_PARTIAL_FLUSH
|
815 SI_CONTEXT_INV_VMEM_L1
|
816 SI_CONTEXT_INV_GLOBAL_L2
|
817 SI_CONTEXT_WRITEBACK_GLOBAL_L2
))) {
818 radeon_emit(cs
, PKT3(PKT3_PFP_SYNC_ME
, 0, 0));
822 /* When one of the CP_COHER_CNTL.DEST_BASE flags is set, SURFACE_SYNC
823 * waits for idle. Therefore, it should be last. SURFACE_SYNC is done
826 * cp_coher_cntl should contain all necessary flags except TC flags
829 * SI-CIK don't support L2 write-back.
831 if (rctx
->flags
& SI_CONTEXT_INV_GLOBAL_L2
||
832 (rctx
->chip_class
<= CIK
&&
833 (rctx
->flags
& SI_CONTEXT_WRITEBACK_GLOBAL_L2
))) {
834 /* Invalidate L1 & L2. (L1 is always invalidated)
835 * WB must be set on VI+ when TC_ACTION is set.
837 si_emit_surface_sync(rctx
, cp_coher_cntl
|
838 S_0085F0_TC_ACTION_ENA(1) |
839 S_0301F0_TC_WB_ACTION_ENA(rctx
->chip_class
>= VI
));
842 /* L1 invalidation and L2 writeback must be done separately,
843 * because both operations can't be done together.
845 if (rctx
->flags
& SI_CONTEXT_WRITEBACK_GLOBAL_L2
) {
847 * NC = apply to non-coherent MTYPEs
848 * (i.e. MTYPE <= 1, which is what we use everywhere)
850 * WB doesn't work without NC.
852 si_emit_surface_sync(rctx
, cp_coher_cntl
|
853 S_0301F0_TC_WB_ACTION_ENA(1) |
854 S_0301F0_TC_NC_ACTION_ENA(1));
857 if (rctx
->flags
& SI_CONTEXT_INV_VMEM_L1
) {
858 /* Invalidate per-CU VMEM L1. */
859 si_emit_surface_sync(rctx
, cp_coher_cntl
|
860 S_0085F0_TCL1_ACTION_ENA(1));
865 /* If TC flushes haven't cleared this... */
867 si_emit_surface_sync(rctx
, cp_coher_cntl
);
869 if (rctx
->flags
& R600_CONTEXT_START_PIPELINE_STATS
) {
870 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
871 radeon_emit(cs
, EVENT_TYPE(V_028A90_PIPELINESTAT_START
) |
873 } else if (rctx
->flags
& R600_CONTEXT_STOP_PIPELINE_STATS
) {
874 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
875 radeon_emit(cs
, EVENT_TYPE(V_028A90_PIPELINESTAT_STOP
) |
882 static void si_get_draw_start_count(struct si_context
*sctx
,
883 const struct pipe_draw_info
*info
,
884 unsigned *start
, unsigned *count
)
886 if (info
->indirect
) {
887 struct r600_resource
*indirect
=
888 (struct r600_resource
*)info
->indirect
;
889 int *data
= r600_buffer_map_sync_with_rings(&sctx
->b
,
890 indirect
, PIPE_TRANSFER_READ
);
891 data
+= info
->indirect_offset
/sizeof(int);
895 *start
= info
->start
;
896 *count
= info
->count
;
900 void si_ce_pre_draw_synchronization(struct si_context
*sctx
)
902 if (sctx
->ce_need_synchronization
) {
903 radeon_emit(sctx
->ce_ib
, PKT3(PKT3_INCREMENT_CE_COUNTER
, 0, 0));
904 radeon_emit(sctx
->ce_ib
, 1);
906 radeon_emit(sctx
->b
.gfx
.cs
, PKT3(PKT3_WAIT_ON_CE_COUNTER
, 0, 0));
907 radeon_emit(sctx
->b
.gfx
.cs
, 1);
911 void si_ce_post_draw_synchronization(struct si_context
*sctx
)
913 if (sctx
->ce_need_synchronization
) {
914 radeon_emit(sctx
->b
.gfx
.cs
, PKT3(PKT3_INCREMENT_DE_COUNTER
, 0, 0));
915 radeon_emit(sctx
->b
.gfx
.cs
, 0);
917 sctx
->ce_need_synchronization
= false;
921 void si_draw_vbo(struct pipe_context
*ctx
, const struct pipe_draw_info
*info
)
923 struct si_context
*sctx
= (struct si_context
*)ctx
;
924 struct si_state_rasterizer
*rs
= sctx
->queued
.named
.rasterizer
;
925 struct pipe_index_buffer ib
= {};
926 unsigned mask
, dirty_fb_counter
, dirty_tex_counter
, rast_prim
;
928 if (likely(!info
->indirect
)) {
929 /* SI-CI treat instance_count==0 as instance_count==1. There is
930 * no workaround for indirect draws, but we can at least skip
933 if (unlikely(!info
->instance_count
))
936 /* Handle count == 0. */
937 if (unlikely(!info
->count
&&
938 (info
->indexed
|| !info
->count_from_stream_output
)))
942 if (unlikely(!sctx
->vs_shader
.cso
)) {
946 if (unlikely(!sctx
->ps_shader
.cso
&& (!rs
|| !rs
->rasterizer_discard
))) {
950 if (unlikely(!!sctx
->tes_shader
.cso
!= (info
->mode
== PIPE_PRIM_PATCHES
))) {
955 /* Re-emit the framebuffer state if needed. */
956 dirty_fb_counter
= p_atomic_read(&sctx
->b
.screen
->dirty_fb_counter
);
957 if (unlikely(dirty_fb_counter
!= sctx
->b
.last_dirty_fb_counter
)) {
958 sctx
->b
.last_dirty_fb_counter
= dirty_fb_counter
;
959 sctx
->framebuffer
.dirty_cbufs
|=
960 ((1 << sctx
->framebuffer
.state
.nr_cbufs
) - 1);
961 sctx
->framebuffer
.dirty_zsbuf
= true;
962 si_mark_atom_dirty(sctx
, &sctx
->framebuffer
.atom
);
965 /* Invalidate & recompute texture descriptors if needed. */
966 dirty_tex_counter
= p_atomic_read(&sctx
->b
.screen
->dirty_tex_descriptor_counter
);
967 if (unlikely(dirty_tex_counter
!= sctx
->b
.last_dirty_tex_descriptor_counter
)) {
968 sctx
->b
.last_dirty_tex_descriptor_counter
= dirty_tex_counter
;
969 si_update_all_texture_descriptors(sctx
);
972 si_decompress_graphics_textures(sctx
);
974 /* Set the rasterization primitive type.
976 * This must be done after si_decompress_textures, which can call
977 * draw_vbo recursively, and before si_update_shaders, which uses
978 * current_rast_prim for this draw_vbo call. */
979 if (sctx
->gs_shader
.cso
)
980 rast_prim
= sctx
->gs_shader
.cso
->gs_output_prim
;
981 else if (sctx
->tes_shader
.cso
)
982 rast_prim
= sctx
->tes_shader
.cso
->info
.properties
[TGSI_PROPERTY_TES_PRIM_MODE
];
984 rast_prim
= info
->mode
;
986 if (rast_prim
!= sctx
->current_rast_prim
) {
987 sctx
->current_rast_prim
= rast_prim
;
988 sctx
->do_update_shaders
= true;
991 if (sctx
->do_update_shaders
&& !si_update_shaders(sctx
))
994 if (!si_upload_graphics_shader_descriptors(sctx
))
998 /* Initialize the index buffer struct. */
999 pipe_resource_reference(&ib
.buffer
, sctx
->index_buffer
.buffer
);
1000 ib
.user_buffer
= sctx
->index_buffer
.user_buffer
;
1001 ib
.index_size
= sctx
->index_buffer
.index_size
;
1002 ib
.offset
= sctx
->index_buffer
.offset
;
1004 /* Translate or upload, if needed. */
1005 /* 8-bit indices are supported on VI. */
1006 if (sctx
->b
.chip_class
<= CIK
&& ib
.index_size
== 1) {
1007 struct pipe_resource
*out_buffer
= NULL
;
1008 unsigned out_offset
, start
, count
, start_offset
;
1011 si_get_draw_start_count(sctx
, info
, &start
, &count
);
1012 start_offset
= start
* ib
.index_size
;
1014 u_upload_alloc(sctx
->b
.uploader
, start_offset
, count
* 2, 256,
1015 &out_offset
, &out_buffer
, &ptr
);
1017 pipe_resource_reference(&ib
.buffer
, NULL
);
1021 util_shorten_ubyte_elts_to_userptr(&sctx
->b
.b
, &ib
, 0,
1022 ib
.offset
+ start_offset
,
1025 pipe_resource_reference(&ib
.buffer
, NULL
);
1026 ib
.user_buffer
= NULL
;
1027 ib
.buffer
= out_buffer
;
1028 /* info->start will be added by the drawing code */
1029 ib
.offset
= out_offset
- start_offset
;
1031 } else if (ib
.user_buffer
&& !ib
.buffer
) {
1032 unsigned start
, count
, start_offset
;
1034 si_get_draw_start_count(sctx
, info
, &start
, &count
);
1035 start_offset
= start
* ib
.index_size
;
1037 u_upload_data(sctx
->b
.uploader
, start_offset
, count
* ib
.index_size
,
1038 256, (char*)ib
.user_buffer
+ start_offset
,
1039 &ib
.offset
, &ib
.buffer
);
1042 /* info->start will be added by the drawing code */
1043 ib
.offset
-= start_offset
;
1047 /* VI reads index buffers through TC L2. */
1048 if (info
->indexed
&& sctx
->b
.chip_class
<= CIK
&&
1049 r600_resource(ib
.buffer
)->TC_L2_dirty
) {
1050 sctx
->b
.flags
|= SI_CONTEXT_WRITEBACK_GLOBAL_L2
;
1051 r600_resource(ib
.buffer
)->TC_L2_dirty
= false;
1054 if (info
->indirect
&& r600_resource(info
->indirect
)->TC_L2_dirty
) {
1055 sctx
->b
.flags
|= SI_CONTEXT_WRITEBACK_GLOBAL_L2
;
1056 r600_resource(info
->indirect
)->TC_L2_dirty
= false;
1059 if (info
->indirect_params
&&
1060 r600_resource(info
->indirect_params
)->TC_L2_dirty
) {
1061 sctx
->b
.flags
|= SI_CONTEXT_WRITEBACK_GLOBAL_L2
;
1062 r600_resource(info
->indirect_params
)->TC_L2_dirty
= false;
1065 /* Add buffer sizes for memory checking in need_cs_space. */
1066 if (sctx
->emit_scratch_reloc
&& sctx
->scratch_buffer
)
1067 r600_context_add_resource_size(ctx
, &sctx
->scratch_buffer
->b
.b
);
1069 r600_context_add_resource_size(ctx
, info
->indirect
);
1071 si_need_cs_space(sctx
);
1073 /* Since we've called r600_context_add_resource_size for vertex buffers,
1074 * this must be called after si_need_cs_space, because we must let
1075 * need_cs_space flush before we add buffers to the buffer list.
1077 if (!si_upload_vertex_buffer_descriptors(sctx
))
1080 /* Flushed caches prior to emitting states. */
1082 si_emit_cache_flush(sctx
);
1085 mask
= sctx
->dirty_atoms
;
1087 struct r600_atom
*atom
= sctx
->atoms
.array
[u_bit_scan(&mask
)];
1089 atom
->emit(&sctx
->b
, atom
);
1091 sctx
->dirty_atoms
= 0;
1093 si_pm4_emit_dirty(sctx
);
1094 si_emit_scratch_reloc(sctx
);
1095 si_emit_rasterizer_prim_state(sctx
);
1096 si_emit_draw_registers(sctx
, info
);
1098 si_ce_pre_draw_synchronization(sctx
);
1100 si_emit_draw_packets(sctx
, info
, &ib
);
1102 si_ce_post_draw_synchronization(sctx
);
1104 if (sctx
->trace_buf
)
1105 si_trace_emit(sctx
);
1107 /* Workaround for a VGT hang when streamout is enabled.
1108 * It must be done after drawing. */
1109 if ((sctx
->b
.family
== CHIP_HAWAII
||
1110 sctx
->b
.family
== CHIP_TONGA
||
1111 sctx
->b
.family
== CHIP_FIJI
) &&
1112 r600_get_strmout_en(&sctx
->b
)) {
1113 sctx
->b
.flags
|= SI_CONTEXT_VGT_STREAMOUT_SYNC
;
1116 /* Set the depth buffer as dirty. */
1117 if (sctx
->framebuffer
.state
.zsbuf
) {
1118 struct pipe_surface
*surf
= sctx
->framebuffer
.state
.zsbuf
;
1119 struct r600_texture
*rtex
= (struct r600_texture
*)surf
->texture
;
1121 if (!rtex
->tc_compatible_htile
)
1122 rtex
->dirty_level_mask
|= 1 << surf
->u
.tex
.level
;
1124 if (rtex
->surface
.flags
& RADEON_SURF_SBUFFER
)
1125 rtex
->stencil_dirty_level_mask
|= 1 << surf
->u
.tex
.level
;
1127 if (sctx
->framebuffer
.compressed_cb_mask
) {
1128 struct pipe_surface
*surf
;
1129 struct r600_texture
*rtex
;
1130 unsigned mask
= sctx
->framebuffer
.compressed_cb_mask
;
1133 unsigned i
= u_bit_scan(&mask
);
1134 surf
= sctx
->framebuffer
.state
.cbufs
[i
];
1135 rtex
= (struct r600_texture
*)surf
->texture
;
1137 if (rtex
->fmask
.size
)
1138 rtex
->dirty_level_mask
|= 1 << surf
->u
.tex
.level
;
1139 if (rtex
->dcc_gather_statistics
)
1140 rtex
->separate_dcc_dirty
= true;
1144 pipe_resource_reference(&ib
.buffer
, NULL
);
1145 sctx
->b
.num_draw_calls
++;
1146 if (G_0286E8_WAVESIZE(sctx
->spi_tmpring_size
))
1147 sctx
->b
.num_spill_draw_calls
++;
1150 void si_trace_emit(struct si_context
*sctx
)
1152 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
1155 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
, sctx
->trace_buf
,
1156 RADEON_USAGE_READWRITE
, RADEON_PRIO_TRACE
);
1157 radeon_emit(cs
, PKT3(PKT3_WRITE_DATA
, 3, 0));
1158 radeon_emit(cs
, S_370_DST_SEL(V_370_MEMORY_SYNC
) |
1159 S_370_WR_CONFIRM(1) |
1160 S_370_ENGINE_SEL(V_370_ME
));
1161 radeon_emit(cs
, sctx
->trace_buf
->gpu_address
);
1162 radeon_emit(cs
, sctx
->trace_buf
->gpu_address
>> 32);
1163 radeon_emit(cs
, sctx
->trace_id
);
1164 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
1165 radeon_emit(cs
, SI_ENCODE_TRACE_POINT(sctx
->trace_id
));