2 * Copyright 2012 Advanced Micro Devices, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
26 #include "radeon/r600_cs.h"
30 #include "util/u_index_modify.h"
31 #include "util/u_log.h"
32 #include "util/u_upload_mgr.h"
33 #include "util/u_prim.h"
37 /* special primitive types */
38 #define SI_PRIM_RECTANGLE_LIST PIPE_PRIM_MAX
40 static unsigned si_conv_pipe_prim(unsigned mode
)
42 static const unsigned prim_conv
[] = {
43 [PIPE_PRIM_POINTS
] = V_008958_DI_PT_POINTLIST
,
44 [PIPE_PRIM_LINES
] = V_008958_DI_PT_LINELIST
,
45 [PIPE_PRIM_LINE_LOOP
] = V_008958_DI_PT_LINELOOP
,
46 [PIPE_PRIM_LINE_STRIP
] = V_008958_DI_PT_LINESTRIP
,
47 [PIPE_PRIM_TRIANGLES
] = V_008958_DI_PT_TRILIST
,
48 [PIPE_PRIM_TRIANGLE_STRIP
] = V_008958_DI_PT_TRISTRIP
,
49 [PIPE_PRIM_TRIANGLE_FAN
] = V_008958_DI_PT_TRIFAN
,
50 [PIPE_PRIM_QUADS
] = V_008958_DI_PT_QUADLIST
,
51 [PIPE_PRIM_QUAD_STRIP
] = V_008958_DI_PT_QUADSTRIP
,
52 [PIPE_PRIM_POLYGON
] = V_008958_DI_PT_POLYGON
,
53 [PIPE_PRIM_LINES_ADJACENCY
] = V_008958_DI_PT_LINELIST_ADJ
,
54 [PIPE_PRIM_LINE_STRIP_ADJACENCY
] = V_008958_DI_PT_LINESTRIP_ADJ
,
55 [PIPE_PRIM_TRIANGLES_ADJACENCY
] = V_008958_DI_PT_TRILIST_ADJ
,
56 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY
] = V_008958_DI_PT_TRISTRIP_ADJ
,
57 [PIPE_PRIM_PATCHES
] = V_008958_DI_PT_PATCH
,
58 [SI_PRIM_RECTANGLE_LIST
] = V_008958_DI_PT_RECTLIST
60 assert(mode
< ARRAY_SIZE(prim_conv
));
61 return prim_conv
[mode
];
64 static unsigned si_conv_prim_to_gs_out(unsigned mode
)
66 static const int prim_conv
[] = {
67 [PIPE_PRIM_POINTS
] = V_028A6C_OUTPRIM_TYPE_POINTLIST
,
68 [PIPE_PRIM_LINES
] = V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
69 [PIPE_PRIM_LINE_LOOP
] = V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
70 [PIPE_PRIM_LINE_STRIP
] = V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
71 [PIPE_PRIM_TRIANGLES
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
72 [PIPE_PRIM_TRIANGLE_STRIP
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
73 [PIPE_PRIM_TRIANGLE_FAN
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
74 [PIPE_PRIM_QUADS
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
75 [PIPE_PRIM_QUAD_STRIP
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
76 [PIPE_PRIM_POLYGON
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
77 [PIPE_PRIM_LINES_ADJACENCY
] = V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
78 [PIPE_PRIM_LINE_STRIP_ADJACENCY
] = V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
79 [PIPE_PRIM_TRIANGLES_ADJACENCY
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
80 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
81 [PIPE_PRIM_PATCHES
] = V_028A6C_OUTPRIM_TYPE_POINTLIST
,
82 [SI_PRIM_RECTANGLE_LIST
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
84 assert(mode
< ARRAY_SIZE(prim_conv
));
86 return prim_conv
[mode
];
90 * This calculates the LDS size for tessellation shaders (VS, TCS, TES).
91 * LS.LDS_SIZE is shared by all 3 shader stages.
93 * The information about LDS and other non-compile-time parameters is then
94 * written to userdata SGPRs.
96 static void si_emit_derived_tess_state(struct si_context
*sctx
,
97 const struct pipe_draw_info
*info
,
98 unsigned *num_patches
)
100 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx_cs
;
101 struct si_shader
*ls_current
;
102 struct si_shader_selector
*ls
;
103 /* The TES pointer will only be used for sctx->last_tcs.
104 * It would be wrong to think that TCS = TES. */
105 struct si_shader_selector
*tcs
=
106 sctx
->tcs_shader
.cso
? sctx
->tcs_shader
.cso
: sctx
->tes_shader
.cso
;
107 unsigned tess_uses_primid
= sctx
->ia_multi_vgt_param_key
.u
.tess_uses_prim_id
;
108 bool has_primid_instancing_bug
= sctx
->b
.chip_class
== SI
&&
109 sctx
->b
.screen
->info
.max_se
== 1;
110 unsigned tes_sh_base
= sctx
->shader_pointers
.sh_base
[PIPE_SHADER_TESS_EVAL
];
111 unsigned num_tcs_input_cp
= info
->vertices_per_patch
;
112 unsigned num_tcs_output_cp
, num_tcs_inputs
, num_tcs_outputs
;
113 unsigned num_tcs_patch_outputs
;
114 unsigned input_vertex_size
, output_vertex_size
, pervertex_output_patch_size
;
115 unsigned input_patch_size
, output_patch_size
, output_patch0_offset
;
116 unsigned perpatch_output_offset
, lds_size
;
117 unsigned tcs_in_layout
, tcs_out_layout
, tcs_out_offsets
;
118 unsigned offchip_layout
, hardware_lds_size
, ls_hs_config
;
120 /* Since GFX9 has merged LS-HS in the TCS state, set LS = TCS. */
121 if (sctx
->b
.chip_class
>= GFX9
) {
122 if (sctx
->tcs_shader
.cso
)
123 ls_current
= sctx
->tcs_shader
.current
;
125 ls_current
= sctx
->fixed_func_tcs_shader
.current
;
127 ls
= ls_current
->key
.part
.tcs
.ls
;
129 ls_current
= sctx
->vs_shader
.current
;
130 ls
= sctx
->vs_shader
.cso
;
133 if (sctx
->last_ls
== ls_current
&&
134 sctx
->last_tcs
== tcs
&&
135 sctx
->last_tes_sh_base
== tes_sh_base
&&
136 sctx
->last_num_tcs_input_cp
== num_tcs_input_cp
&&
137 (!has_primid_instancing_bug
||
138 (sctx
->last_tess_uses_primid
== tess_uses_primid
))) {
139 *num_patches
= sctx
->last_num_patches
;
143 sctx
->last_ls
= ls_current
;
144 sctx
->last_tcs
= tcs
;
145 sctx
->last_tes_sh_base
= tes_sh_base
;
146 sctx
->last_num_tcs_input_cp
= num_tcs_input_cp
;
147 sctx
->last_tess_uses_primid
= tess_uses_primid
;
149 /* This calculates how shader inputs and outputs among VS, TCS, and TES
150 * are laid out in LDS. */
151 num_tcs_inputs
= util_last_bit64(ls
->outputs_written
);
153 if (sctx
->tcs_shader
.cso
) {
154 num_tcs_outputs
= util_last_bit64(tcs
->outputs_written
);
155 num_tcs_output_cp
= tcs
->info
.properties
[TGSI_PROPERTY_TCS_VERTICES_OUT
];
156 num_tcs_patch_outputs
= util_last_bit64(tcs
->patch_outputs_written
);
158 /* No TCS. Route varyings from LS to TES. */
159 num_tcs_outputs
= num_tcs_inputs
;
160 num_tcs_output_cp
= num_tcs_input_cp
;
161 num_tcs_patch_outputs
= 2; /* TESSINNER + TESSOUTER */
164 input_vertex_size
= num_tcs_inputs
* 16;
165 output_vertex_size
= num_tcs_outputs
* 16;
167 input_patch_size
= num_tcs_input_cp
* input_vertex_size
;
169 pervertex_output_patch_size
= num_tcs_output_cp
* output_vertex_size
;
170 output_patch_size
= pervertex_output_patch_size
+ num_tcs_patch_outputs
* 16;
172 /* Ensure that we only need one wave per SIMD so we don't need to check
173 * resource usage. Also ensures that the number of tcs in and out
174 * vertices per threadgroup are at most 256.
176 *num_patches
= 64 / MAX2(num_tcs_input_cp
, num_tcs_output_cp
) * 4;
178 /* Make sure that the data fits in LDS. This assumes the shaders only
179 * use LDS for the inputs and outputs.
181 * While CIK can use 64K per threadgroup, there is a hang on Stoney
182 * with 2 CUs if we use more than 32K. The closed Vulkan driver also
183 * uses 32K at most on all GCN chips.
185 hardware_lds_size
= 32768;
186 *num_patches
= MIN2(*num_patches
, hardware_lds_size
/ (input_patch_size
+
189 /* Make sure the output data fits in the offchip buffer */
190 *num_patches
= MIN2(*num_patches
,
191 (sctx
->screen
->tess_offchip_block_dw_size
* 4) /
194 /* Not necessary for correctness, but improves performance. The
195 * specific value is taken from the proprietary driver.
197 *num_patches
= MIN2(*num_patches
, 40);
199 if (sctx
->b
.chip_class
== SI
) {
200 /* SI bug workaround, related to power management. Limit LS-HS
201 * threadgroups to only one wave.
203 unsigned one_wave
= 64 / MAX2(num_tcs_input_cp
, num_tcs_output_cp
);
204 *num_patches
= MIN2(*num_patches
, one_wave
);
207 /* The VGT HS block increments the patch ID unconditionally
208 * within a single threadgroup. This results in incorrect
209 * patch IDs when instanced draws are used.
211 * The intended solution is to restrict threadgroups to
212 * a single instance by setting SWITCH_ON_EOI, which
213 * should cause IA to split instances up. However, this
214 * doesn't work correctly on SI when there is no other
217 if (has_primid_instancing_bug
&& tess_uses_primid
)
220 sctx
->last_num_patches
= *num_patches
;
222 output_patch0_offset
= input_patch_size
* *num_patches
;
223 perpatch_output_offset
= output_patch0_offset
+ pervertex_output_patch_size
;
225 /* Compute userdata SGPRs. */
226 assert(((input_vertex_size
/ 4) & ~0xff) == 0);
227 assert(((output_vertex_size
/ 4) & ~0xff) == 0);
228 assert(((input_patch_size
/ 4) & ~0x1fff) == 0);
229 assert(((output_patch_size
/ 4) & ~0x1fff) == 0);
230 assert(((output_patch0_offset
/ 16) & ~0xffff) == 0);
231 assert(((perpatch_output_offset
/ 16) & ~0xffff) == 0);
232 assert(num_tcs_input_cp
<= 32);
233 assert(num_tcs_output_cp
<= 32);
235 uint64_t ring_va
= r600_resource(sctx
->tess_rings
)->gpu_address
;
236 assert((ring_va
& u_bit_consecutive(0, 19)) == 0);
238 tcs_in_layout
= S_VS_STATE_LS_OUT_PATCH_SIZE(input_patch_size
/ 4) |
239 S_VS_STATE_LS_OUT_VERTEX_SIZE(input_vertex_size
/ 4);
240 tcs_out_layout
= (output_patch_size
/ 4) |
241 (num_tcs_input_cp
<< 13) |
243 tcs_out_offsets
= (output_patch0_offset
/ 16) |
244 ((perpatch_output_offset
/ 16) << 16);
245 offchip_layout
= *num_patches
|
246 (num_tcs_output_cp
<< 6) |
247 (pervertex_output_patch_size
* *num_patches
<< 12);
249 /* Compute the LDS size. */
250 lds_size
= output_patch0_offset
+ output_patch_size
* *num_patches
;
252 if (sctx
->b
.chip_class
>= CIK
) {
253 assert(lds_size
<= 65536);
254 lds_size
= align(lds_size
, 512) / 512;
256 assert(lds_size
<= 32768);
257 lds_size
= align(lds_size
, 256) / 256;
260 /* Set SI_SGPR_VS_STATE_BITS. */
261 sctx
->current_vs_state
&= C_VS_STATE_LS_OUT_PATCH_SIZE
&
262 C_VS_STATE_LS_OUT_VERTEX_SIZE
;
263 sctx
->current_vs_state
|= tcs_in_layout
;
265 if (sctx
->b
.chip_class
>= GFX9
) {
266 unsigned hs_rsrc2
= ls_current
->config
.rsrc2
|
267 S_00B42C_LDS_SIZE(lds_size
);
269 radeon_set_sh_reg(cs
, R_00B42C_SPI_SHADER_PGM_RSRC2_HS
, hs_rsrc2
);
271 /* Set userdata SGPRs for merged LS-HS. */
272 radeon_set_sh_reg_seq(cs
,
273 R_00B430_SPI_SHADER_USER_DATA_LS_0
+
274 GFX9_SGPR_TCS_OFFCHIP_LAYOUT
* 4, 3);
275 radeon_emit(cs
, offchip_layout
);
276 radeon_emit(cs
, tcs_out_offsets
);
277 radeon_emit(cs
, tcs_out_layout
);
279 unsigned ls_rsrc2
= ls_current
->config
.rsrc2
;
281 si_multiwave_lds_size_workaround(sctx
->screen
, &lds_size
);
282 ls_rsrc2
|= S_00B52C_LDS_SIZE(lds_size
);
284 /* Due to a hw bug, RSRC2_LS must be written twice with another
285 * LS register written in between. */
286 if (sctx
->b
.chip_class
== CIK
&& sctx
->b
.family
!= CHIP_HAWAII
)
287 radeon_set_sh_reg(cs
, R_00B52C_SPI_SHADER_PGM_RSRC2_LS
, ls_rsrc2
);
288 radeon_set_sh_reg_seq(cs
, R_00B528_SPI_SHADER_PGM_RSRC1_LS
, 2);
289 radeon_emit(cs
, ls_current
->config
.rsrc1
);
290 radeon_emit(cs
, ls_rsrc2
);
292 /* Set userdata SGPRs for TCS. */
293 radeon_set_sh_reg_seq(cs
,
294 R_00B430_SPI_SHADER_USER_DATA_HS_0
+ GFX6_SGPR_TCS_OFFCHIP_LAYOUT
* 4, 4);
295 radeon_emit(cs
, offchip_layout
);
296 radeon_emit(cs
, tcs_out_offsets
);
297 radeon_emit(cs
, tcs_out_layout
);
298 radeon_emit(cs
, tcs_in_layout
);
301 /* Set userdata SGPRs for TES. */
302 radeon_set_sh_reg_seq(cs
, tes_sh_base
+ SI_SGPR_TES_OFFCHIP_LAYOUT
* 4, 2);
303 radeon_emit(cs
, offchip_layout
);
304 radeon_emit(cs
, ring_va
);
306 ls_hs_config
= S_028B58_NUM_PATCHES(*num_patches
) |
307 S_028B58_HS_NUM_INPUT_CP(num_tcs_input_cp
) |
308 S_028B58_HS_NUM_OUTPUT_CP(num_tcs_output_cp
);
310 if (sctx
->b
.chip_class
>= CIK
)
311 radeon_set_context_reg_idx(cs
, R_028B58_VGT_LS_HS_CONFIG
, 2,
314 radeon_set_context_reg(cs
, R_028B58_VGT_LS_HS_CONFIG
,
318 static unsigned si_num_prims_for_vertices(const struct pipe_draw_info
*info
)
320 switch (info
->mode
) {
321 case PIPE_PRIM_PATCHES
:
322 return info
->count
/ info
->vertices_per_patch
;
323 case SI_PRIM_RECTANGLE_LIST
:
324 return info
->count
/ 3;
326 return u_prims_for_vertices(info
->mode
, info
->count
);
331 si_get_init_multi_vgt_param(struct si_screen
*sscreen
,
332 union si_vgt_param_key
*key
)
334 STATIC_ASSERT(sizeof(union si_vgt_param_key
) == 4);
335 unsigned max_primgroup_in_wave
= 2;
337 /* SWITCH_ON_EOP(0) is always preferable. */
338 bool wd_switch_on_eop
= false;
339 bool ia_switch_on_eop
= false;
340 bool ia_switch_on_eoi
= false;
341 bool partial_vs_wave
= false;
342 bool partial_es_wave
= false;
344 if (key
->u
.uses_tess
) {
345 /* SWITCH_ON_EOI must be set if PrimID is used. */
346 if (key
->u
.tess_uses_prim_id
)
347 ia_switch_on_eoi
= true;
349 /* Bug with tessellation and GS on Bonaire and older 2 SE chips. */
350 if ((sscreen
->info
.family
== CHIP_TAHITI
||
351 sscreen
->info
.family
== CHIP_PITCAIRN
||
352 sscreen
->info
.family
== CHIP_BONAIRE
) &&
354 partial_vs_wave
= true;
356 /* Needed for 028B6C_DISTRIBUTION_MODE != 0 */
357 if (sscreen
->has_distributed_tess
) {
358 if (key
->u
.uses_gs
) {
359 if (sscreen
->info
.chip_class
<= VI
)
360 partial_es_wave
= true;
362 /* GPU hang workaround. */
363 if (sscreen
->info
.family
== CHIP_TONGA
||
364 sscreen
->info
.family
== CHIP_FIJI
||
365 sscreen
->info
.family
== CHIP_POLARIS10
||
366 sscreen
->info
.family
== CHIP_POLARIS11
||
367 sscreen
->info
.family
== CHIP_POLARIS12
)
368 partial_vs_wave
= true;
370 partial_vs_wave
= true;
375 /* This is a hardware requirement. */
376 if (key
->u
.line_stipple_enabled
||
377 (sscreen
->debug_flags
& DBG(SWITCH_ON_EOP
))) {
378 ia_switch_on_eop
= true;
379 wd_switch_on_eop
= true;
382 if (sscreen
->info
.chip_class
>= CIK
) {
383 /* WD_SWITCH_ON_EOP has no effect on GPUs with less than
384 * 4 shader engines. Set 1 to pass the assertion below.
385 * The other cases are hardware requirements.
387 * Polaris supports primitive restart with WD_SWITCH_ON_EOP=0
388 * for points, line strips, and tri strips.
390 if (sscreen
->info
.max_se
< 4 ||
391 key
->u
.prim
== PIPE_PRIM_POLYGON
||
392 key
->u
.prim
== PIPE_PRIM_LINE_LOOP
||
393 key
->u
.prim
== PIPE_PRIM_TRIANGLE_FAN
||
394 key
->u
.prim
== PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY
||
395 (key
->u
.primitive_restart
&&
396 (sscreen
->info
.family
< CHIP_POLARIS10
||
397 (key
->u
.prim
!= PIPE_PRIM_POINTS
&&
398 key
->u
.prim
!= PIPE_PRIM_LINE_STRIP
&&
399 key
->u
.prim
!= PIPE_PRIM_TRIANGLE_STRIP
))) ||
400 key
->u
.count_from_stream_output
)
401 wd_switch_on_eop
= true;
403 /* Hawaii hangs if instancing is enabled and WD_SWITCH_ON_EOP is 0.
404 * We don't know that for indirect drawing, so treat it as
405 * always problematic. */
406 if (sscreen
->info
.family
== CHIP_HAWAII
&&
407 key
->u
.uses_instancing
)
408 wd_switch_on_eop
= true;
410 /* Performance recommendation for 4 SE Gfx7-8 parts if
411 * instances are smaller than a primgroup.
412 * Assume indirect draws always use small instances.
413 * This is needed for good VS wave utilization.
415 if (sscreen
->info
.chip_class
<= VI
&&
416 sscreen
->info
.max_se
== 4 &&
417 key
->u
.multi_instances_smaller_than_primgroup
)
418 wd_switch_on_eop
= true;
420 /* Required on CIK and later. */
421 if (sscreen
->info
.max_se
> 2 && !wd_switch_on_eop
)
422 ia_switch_on_eoi
= true;
424 /* Required by Hawaii and, for some special cases, by VI. */
425 if (ia_switch_on_eoi
&&
426 (sscreen
->info
.family
== CHIP_HAWAII
||
427 (sscreen
->info
.chip_class
== VI
&&
428 (key
->u
.uses_gs
|| max_primgroup_in_wave
!= 2))))
429 partial_vs_wave
= true;
431 /* Instancing bug on Bonaire. */
432 if (sscreen
->info
.family
== CHIP_BONAIRE
&& ia_switch_on_eoi
&&
433 key
->u
.uses_instancing
)
434 partial_vs_wave
= true;
436 /* If the WD switch is false, the IA switch must be false too. */
437 assert(wd_switch_on_eop
|| !ia_switch_on_eop
);
440 /* If SWITCH_ON_EOI is set, PARTIAL_ES_WAVE must be set too. */
441 if (sscreen
->info
.chip_class
<= VI
&& ia_switch_on_eoi
)
442 partial_es_wave
= true;
444 return S_028AA8_SWITCH_ON_EOP(ia_switch_on_eop
) |
445 S_028AA8_SWITCH_ON_EOI(ia_switch_on_eoi
) |
446 S_028AA8_PARTIAL_VS_WAVE_ON(partial_vs_wave
) |
447 S_028AA8_PARTIAL_ES_WAVE_ON(partial_es_wave
) |
448 S_028AA8_WD_SWITCH_ON_EOP(sscreen
->info
.chip_class
>= CIK
? wd_switch_on_eop
: 0) |
449 /* The following field was moved to VGT_SHADER_STAGES_EN in GFX9. */
450 S_028AA8_MAX_PRIMGRP_IN_WAVE(sscreen
->info
.chip_class
== VI
?
451 max_primgroup_in_wave
: 0) |
452 S_030960_EN_INST_OPT_BASIC(sscreen
->info
.chip_class
>= GFX9
) |
453 S_030960_EN_INST_OPT_ADV(sscreen
->info
.chip_class
>= GFX9
);
456 void si_init_ia_multi_vgt_param_table(struct si_context
*sctx
)
458 for (int prim
= 0; prim
<= SI_PRIM_RECTANGLE_LIST
; prim
++)
459 for (int uses_instancing
= 0; uses_instancing
< 2; uses_instancing
++)
460 for (int multi_instances
= 0; multi_instances
< 2; multi_instances
++)
461 for (int primitive_restart
= 0; primitive_restart
< 2; primitive_restart
++)
462 for (int count_from_so
= 0; count_from_so
< 2; count_from_so
++)
463 for (int line_stipple
= 0; line_stipple
< 2; line_stipple
++)
464 for (int uses_tess
= 0; uses_tess
< 2; uses_tess
++)
465 for (int tess_uses_primid
= 0; tess_uses_primid
< 2; tess_uses_primid
++)
466 for (int uses_gs
= 0; uses_gs
< 2; uses_gs
++) {
467 union si_vgt_param_key key
;
471 key
.u
.uses_instancing
= uses_instancing
;
472 key
.u
.multi_instances_smaller_than_primgroup
= multi_instances
;
473 key
.u
.primitive_restart
= primitive_restart
;
474 key
.u
.count_from_stream_output
= count_from_so
;
475 key
.u
.line_stipple_enabled
= line_stipple
;
476 key
.u
.uses_tess
= uses_tess
;
477 key
.u
.tess_uses_prim_id
= tess_uses_primid
;
478 key
.u
.uses_gs
= uses_gs
;
480 sctx
->ia_multi_vgt_param
[key
.index
] =
481 si_get_init_multi_vgt_param(sctx
->screen
, &key
);
485 static unsigned si_get_ia_multi_vgt_param(struct si_context
*sctx
,
486 const struct pipe_draw_info
*info
,
487 unsigned num_patches
)
489 union si_vgt_param_key key
= sctx
->ia_multi_vgt_param_key
;
490 unsigned primgroup_size
;
491 unsigned ia_multi_vgt_param
;
493 if (sctx
->tes_shader
.cso
) {
494 primgroup_size
= num_patches
; /* must be a multiple of NUM_PATCHES */
495 } else if (sctx
->gs_shader
.cso
) {
496 primgroup_size
= 64; /* recommended with a GS */
498 primgroup_size
= 128; /* recommended without a GS and tess */
501 key
.u
.prim
= info
->mode
;
502 key
.u
.uses_instancing
= info
->indirect
|| info
->instance_count
> 1;
503 key
.u
.multi_instances_smaller_than_primgroup
=
505 (info
->instance_count
> 1 &&
506 (info
->count_from_stream_output
||
507 si_num_prims_for_vertices(info
) < primgroup_size
));
508 key
.u
.primitive_restart
= info
->primitive_restart
;
509 key
.u
.count_from_stream_output
= info
->count_from_stream_output
!= NULL
;
511 ia_multi_vgt_param
= sctx
->ia_multi_vgt_param
[key
.index
] |
512 S_028AA8_PRIMGROUP_SIZE(primgroup_size
- 1);
514 if (sctx
->gs_shader
.cso
) {
515 /* GS requirement. */
516 if (sctx
->b
.chip_class
<= VI
&&
517 SI_GS_PER_ES
/ primgroup_size
>= sctx
->screen
->gs_table_depth
- 3)
518 ia_multi_vgt_param
|= S_028AA8_PARTIAL_ES_WAVE_ON(1);
520 /* GS hw bug with single-primitive instances and SWITCH_ON_EOI.
521 * The hw doc says all multi-SE chips are affected, but Vulkan
522 * only applies it to Hawaii. Do what Vulkan does.
524 if (sctx
->b
.family
== CHIP_HAWAII
&&
525 G_028AA8_SWITCH_ON_EOI(ia_multi_vgt_param
) &&
527 (info
->instance_count
> 1 &&
528 (info
->count_from_stream_output
||
529 si_num_prims_for_vertices(info
) <= 1))))
530 sctx
->b
.flags
|= SI_CONTEXT_VGT_FLUSH
;
533 return ia_multi_vgt_param
;
536 /* rast_prim is the primitive type after GS. */
537 static void si_emit_rasterizer_prim_state(struct si_context
*sctx
)
539 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx_cs
;
540 enum pipe_prim_type rast_prim
= sctx
->current_rast_prim
;
541 struct si_state_rasterizer
*rs
= sctx
->emitted
.named
.rasterizer
;
543 /* Skip this if not rendering lines. */
544 if (rast_prim
!= PIPE_PRIM_LINES
&&
545 rast_prim
!= PIPE_PRIM_LINE_LOOP
&&
546 rast_prim
!= PIPE_PRIM_LINE_STRIP
&&
547 rast_prim
!= PIPE_PRIM_LINES_ADJACENCY
&&
548 rast_prim
!= PIPE_PRIM_LINE_STRIP_ADJACENCY
)
551 if (rast_prim
== sctx
->last_rast_prim
&&
552 rs
->pa_sc_line_stipple
== sctx
->last_sc_line_stipple
)
555 /* For lines, reset the stipple pattern at each primitive. Otherwise,
556 * reset the stipple pattern at each packet (line strips, line loops).
558 radeon_set_context_reg(cs
, R_028A0C_PA_SC_LINE_STIPPLE
,
559 rs
->pa_sc_line_stipple
|
560 S_028A0C_AUTO_RESET_CNTL(rast_prim
== PIPE_PRIM_LINES
? 1 : 2));
562 sctx
->last_rast_prim
= rast_prim
;
563 sctx
->last_sc_line_stipple
= rs
->pa_sc_line_stipple
;
566 static void si_emit_vs_state(struct si_context
*sctx
,
567 const struct pipe_draw_info
*info
)
569 sctx
->current_vs_state
&= C_VS_STATE_INDEXED
;
570 sctx
->current_vs_state
|= S_VS_STATE_INDEXED(!!info
->index_size
);
572 if (sctx
->num_vs_blit_sgprs
) {
573 /* Re-emit the state after we leave u_blitter. */
574 sctx
->last_vs_state
= ~0;
578 if (sctx
->current_vs_state
!= sctx
->last_vs_state
) {
579 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx_cs
;
581 radeon_set_sh_reg(cs
,
582 sctx
->shader_pointers
.sh_base
[PIPE_SHADER_VERTEX
] +
583 SI_SGPR_VS_STATE_BITS
* 4,
584 sctx
->current_vs_state
);
586 sctx
->last_vs_state
= sctx
->current_vs_state
;
590 static void si_emit_draw_registers(struct si_context
*sctx
,
591 const struct pipe_draw_info
*info
,
592 unsigned num_patches
)
594 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx_cs
;
595 unsigned prim
= si_conv_pipe_prim(info
->mode
);
596 unsigned gs_out_prim
= si_conv_prim_to_gs_out(sctx
->current_rast_prim
);
597 unsigned ia_multi_vgt_param
;
599 ia_multi_vgt_param
= si_get_ia_multi_vgt_param(sctx
, info
, num_patches
);
602 if (ia_multi_vgt_param
!= sctx
->last_multi_vgt_param
) {
603 if (sctx
->b
.chip_class
>= GFX9
)
604 radeon_set_uconfig_reg_idx(cs
, R_030960_IA_MULTI_VGT_PARAM
, 4, ia_multi_vgt_param
);
605 else if (sctx
->b
.chip_class
>= CIK
)
606 radeon_set_context_reg_idx(cs
, R_028AA8_IA_MULTI_VGT_PARAM
, 1, ia_multi_vgt_param
);
608 radeon_set_context_reg(cs
, R_028AA8_IA_MULTI_VGT_PARAM
, ia_multi_vgt_param
);
610 sctx
->last_multi_vgt_param
= ia_multi_vgt_param
;
612 if (prim
!= sctx
->last_prim
) {
613 if (sctx
->b
.chip_class
>= CIK
)
614 radeon_set_uconfig_reg_idx(cs
, R_030908_VGT_PRIMITIVE_TYPE
, 1, prim
);
616 radeon_set_config_reg(cs
, R_008958_VGT_PRIMITIVE_TYPE
, prim
);
618 sctx
->last_prim
= prim
;
621 if (gs_out_prim
!= sctx
->last_gs_out_prim
) {
622 radeon_set_context_reg(cs
, R_028A6C_VGT_GS_OUT_PRIM_TYPE
, gs_out_prim
);
623 sctx
->last_gs_out_prim
= gs_out_prim
;
626 /* Primitive restart. */
627 if (info
->primitive_restart
!= sctx
->last_primitive_restart_en
) {
628 if (sctx
->b
.chip_class
>= GFX9
)
629 radeon_set_uconfig_reg(cs
, R_03092C_VGT_MULTI_PRIM_IB_RESET_EN
,
630 info
->primitive_restart
);
632 radeon_set_context_reg(cs
, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN
,
633 info
->primitive_restart
);
635 sctx
->last_primitive_restart_en
= info
->primitive_restart
;
638 if (info
->primitive_restart
&&
639 (info
->restart_index
!= sctx
->last_restart_index
||
640 sctx
->last_restart_index
== SI_RESTART_INDEX_UNKNOWN
)) {
641 radeon_set_context_reg(cs
, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX
,
642 info
->restart_index
);
643 sctx
->last_restart_index
= info
->restart_index
;
647 static void si_emit_draw_packets(struct si_context
*sctx
,
648 const struct pipe_draw_info
*info
,
649 struct pipe_resource
*indexbuf
,
651 unsigned index_offset
)
653 struct pipe_draw_indirect_info
*indirect
= info
->indirect
;
654 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx_cs
;
655 unsigned sh_base_reg
= sctx
->shader_pointers
.sh_base
[PIPE_SHADER_VERTEX
];
656 bool render_cond_bit
= sctx
->b
.render_cond
&& !sctx
->b
.render_cond_force_off
;
657 uint32_t index_max_size
= 0;
658 uint64_t index_va
= 0;
660 if (info
->count_from_stream_output
) {
661 struct si_streamout_target
*t
=
662 (struct si_streamout_target
*)info
->count_from_stream_output
;
663 uint64_t va
= t
->buf_filled_size
->gpu_address
+
664 t
->buf_filled_size_offset
;
666 radeon_set_context_reg(cs
, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE
,
669 radeon_emit(cs
, PKT3(PKT3_COPY_DATA
, 4, 0));
670 radeon_emit(cs
, COPY_DATA_SRC_SEL(COPY_DATA_MEM
) |
671 COPY_DATA_DST_SEL(COPY_DATA_REG
) |
672 COPY_DATA_WR_CONFIRM
);
673 radeon_emit(cs
, va
); /* src address lo */
674 radeon_emit(cs
, va
>> 32); /* src address hi */
675 radeon_emit(cs
, R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE
>> 2);
676 radeon_emit(cs
, 0); /* unused */
678 radeon_add_to_buffer_list(sctx
, sctx
->b
.gfx_cs
,
679 t
->buf_filled_size
, RADEON_USAGE_READ
,
680 RADEON_PRIO_SO_FILLED_SIZE
);
685 if (index_size
!= sctx
->last_index_size
) {
689 switch (index_size
) {
691 index_type
= V_028A7C_VGT_INDEX_8
;
694 index_type
= V_028A7C_VGT_INDEX_16
|
695 (SI_BIG_ENDIAN
&& sctx
->b
.chip_class
<= CIK
?
696 V_028A7C_VGT_DMA_SWAP_16_BIT
: 0);
699 index_type
= V_028A7C_VGT_INDEX_32
|
700 (SI_BIG_ENDIAN
&& sctx
->b
.chip_class
<= CIK
?
701 V_028A7C_VGT_DMA_SWAP_32_BIT
: 0);
704 assert(!"unreachable");
708 if (sctx
->b
.chip_class
>= GFX9
) {
709 radeon_set_uconfig_reg_idx(cs
, R_03090C_VGT_INDEX_TYPE
,
712 radeon_emit(cs
, PKT3(PKT3_INDEX_TYPE
, 0, 0));
713 radeon_emit(cs
, index_type
);
716 sctx
->last_index_size
= index_size
;
719 index_max_size
= (indexbuf
->width0
- index_offset
) /
721 index_va
= r600_resource(indexbuf
)->gpu_address
+ index_offset
;
723 radeon_add_to_buffer_list(sctx
, sctx
->b
.gfx_cs
,
724 (struct r600_resource
*)indexbuf
,
725 RADEON_USAGE_READ
, RADEON_PRIO_INDEX_BUFFER
);
727 /* On CI and later, non-indexed draws overwrite VGT_INDEX_TYPE,
728 * so the state must be re-emitted before the next indexed draw.
730 if (sctx
->b
.chip_class
>= CIK
)
731 sctx
->last_index_size
= -1;
735 uint64_t indirect_va
= r600_resource(indirect
->buffer
)->gpu_address
;
737 assert(indirect_va
% 8 == 0);
739 si_invalidate_draw_sh_constants(sctx
);
741 radeon_emit(cs
, PKT3(PKT3_SET_BASE
, 2, 0));
743 radeon_emit(cs
, indirect_va
);
744 radeon_emit(cs
, indirect_va
>> 32);
746 radeon_add_to_buffer_list(sctx
, sctx
->b
.gfx_cs
,
747 (struct r600_resource
*)indirect
->buffer
,
748 RADEON_USAGE_READ
, RADEON_PRIO_DRAW_INDIRECT
);
750 unsigned di_src_sel
= index_size
? V_0287F0_DI_SRC_SEL_DMA
751 : V_0287F0_DI_SRC_SEL_AUTO_INDEX
;
753 assert(indirect
->offset
% 4 == 0);
756 radeon_emit(cs
, PKT3(PKT3_INDEX_BASE
, 1, 0));
757 radeon_emit(cs
, index_va
);
758 radeon_emit(cs
, index_va
>> 32);
760 radeon_emit(cs
, PKT3(PKT3_INDEX_BUFFER_SIZE
, 0, 0));
761 radeon_emit(cs
, index_max_size
);
764 if (!sctx
->screen
->has_draw_indirect_multi
) {
765 radeon_emit(cs
, PKT3(index_size
? PKT3_DRAW_INDEX_INDIRECT
766 : PKT3_DRAW_INDIRECT
,
767 3, render_cond_bit
));
768 radeon_emit(cs
, indirect
->offset
);
769 radeon_emit(cs
, (sh_base_reg
+ SI_SGPR_BASE_VERTEX
* 4 - SI_SH_REG_OFFSET
) >> 2);
770 radeon_emit(cs
, (sh_base_reg
+ SI_SGPR_START_INSTANCE
* 4 - SI_SH_REG_OFFSET
) >> 2);
771 radeon_emit(cs
, di_src_sel
);
773 uint64_t count_va
= 0;
775 if (indirect
->indirect_draw_count
) {
776 struct r600_resource
*params_buf
=
777 (struct r600_resource
*)indirect
->indirect_draw_count
;
779 radeon_add_to_buffer_list(
780 sctx
, sctx
->b
.gfx_cs
, params_buf
,
781 RADEON_USAGE_READ
, RADEON_PRIO_DRAW_INDIRECT
);
783 count_va
= params_buf
->gpu_address
+ indirect
->indirect_draw_count_offset
;
786 radeon_emit(cs
, PKT3(index_size
? PKT3_DRAW_INDEX_INDIRECT_MULTI
:
787 PKT3_DRAW_INDIRECT_MULTI
,
788 8, render_cond_bit
));
789 radeon_emit(cs
, indirect
->offset
);
790 radeon_emit(cs
, (sh_base_reg
+ SI_SGPR_BASE_VERTEX
* 4 - SI_SH_REG_OFFSET
) >> 2);
791 radeon_emit(cs
, (sh_base_reg
+ SI_SGPR_START_INSTANCE
* 4 - SI_SH_REG_OFFSET
) >> 2);
792 radeon_emit(cs
, ((sh_base_reg
+ SI_SGPR_DRAWID
* 4 - SI_SH_REG_OFFSET
) >> 2) |
793 S_2C3_DRAW_INDEX_ENABLE(1) |
794 S_2C3_COUNT_INDIRECT_ENABLE(!!indirect
->indirect_draw_count
));
795 radeon_emit(cs
, indirect
->draw_count
);
796 radeon_emit(cs
, count_va
);
797 radeon_emit(cs
, count_va
>> 32);
798 radeon_emit(cs
, indirect
->stride
);
799 radeon_emit(cs
, di_src_sel
);
804 radeon_emit(cs
, PKT3(PKT3_NUM_INSTANCES
, 0, 0));
805 radeon_emit(cs
, info
->instance_count
);
807 /* Base vertex and start instance. */
808 base_vertex
= index_size
? info
->index_bias
: info
->start
;
810 if (sctx
->num_vs_blit_sgprs
) {
811 /* Re-emit draw constants after we leave u_blitter. */
812 si_invalidate_draw_sh_constants(sctx
);
814 /* Blit VS doesn't use BASE_VERTEX, START_INSTANCE, and DRAWID. */
815 radeon_set_sh_reg_seq(cs
, sh_base_reg
+ SI_SGPR_VS_BLIT_DATA
* 4,
816 sctx
->num_vs_blit_sgprs
);
817 radeon_emit_array(cs
, sctx
->vs_blit_sh_data
,
818 sctx
->num_vs_blit_sgprs
);
819 } else if (base_vertex
!= sctx
->last_base_vertex
||
820 sctx
->last_base_vertex
== SI_BASE_VERTEX_UNKNOWN
||
821 info
->start_instance
!= sctx
->last_start_instance
||
822 info
->drawid
!= sctx
->last_drawid
||
823 sh_base_reg
!= sctx
->last_sh_base_reg
) {
824 radeon_set_sh_reg_seq(cs
, sh_base_reg
+ SI_SGPR_BASE_VERTEX
* 4, 3);
825 radeon_emit(cs
, base_vertex
);
826 radeon_emit(cs
, info
->start_instance
);
827 radeon_emit(cs
, info
->drawid
);
829 sctx
->last_base_vertex
= base_vertex
;
830 sctx
->last_start_instance
= info
->start_instance
;
831 sctx
->last_drawid
= info
->drawid
;
832 sctx
->last_sh_base_reg
= sh_base_reg
;
836 index_va
+= info
->start
* index_size
;
838 radeon_emit(cs
, PKT3(PKT3_DRAW_INDEX_2
, 4, render_cond_bit
));
839 radeon_emit(cs
, index_max_size
);
840 radeon_emit(cs
, index_va
);
841 radeon_emit(cs
, index_va
>> 32);
842 radeon_emit(cs
, info
->count
);
843 radeon_emit(cs
, V_0287F0_DI_SRC_SEL_DMA
);
845 radeon_emit(cs
, PKT3(PKT3_DRAW_INDEX_AUTO
, 1, render_cond_bit
));
846 radeon_emit(cs
, info
->count
);
847 radeon_emit(cs
, V_0287F0_DI_SRC_SEL_AUTO_INDEX
|
848 S_0287F0_USE_OPAQUE(!!info
->count_from_stream_output
));
853 static void si_emit_surface_sync(struct si_context
*sctx
,
854 unsigned cp_coher_cntl
)
856 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx_cs
;
858 if (sctx
->b
.chip_class
>= GFX9
) {
859 /* Flush caches and wait for the caches to assert idle. */
860 radeon_emit(cs
, PKT3(PKT3_ACQUIRE_MEM
, 5, 0));
861 radeon_emit(cs
, cp_coher_cntl
); /* CP_COHER_CNTL */
862 radeon_emit(cs
, 0xffffffff); /* CP_COHER_SIZE */
863 radeon_emit(cs
, 0xffffff); /* CP_COHER_SIZE_HI */
864 radeon_emit(cs
, 0); /* CP_COHER_BASE */
865 radeon_emit(cs
, 0); /* CP_COHER_BASE_HI */
866 radeon_emit(cs
, 0x0000000A); /* POLL_INTERVAL */
868 /* ACQUIRE_MEM is only required on a compute ring. */
869 radeon_emit(cs
, PKT3(PKT3_SURFACE_SYNC
, 3, 0));
870 radeon_emit(cs
, cp_coher_cntl
); /* CP_COHER_CNTL */
871 radeon_emit(cs
, 0xffffffff); /* CP_COHER_SIZE */
872 radeon_emit(cs
, 0); /* CP_COHER_BASE */
873 radeon_emit(cs
, 0x0000000A); /* POLL_INTERVAL */
877 void si_emit_cache_flush(struct si_context
*sctx
)
879 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx_cs
;
880 uint32_t flags
= sctx
->b
.flags
;
881 uint32_t cp_coher_cntl
= 0;
882 uint32_t flush_cb_db
= flags
& (SI_CONTEXT_FLUSH_AND_INV_CB
|
883 SI_CONTEXT_FLUSH_AND_INV_DB
);
885 if (flags
& SI_CONTEXT_FLUSH_AND_INV_CB
)
886 sctx
->b
.num_cb_cache_flushes
++;
887 if (flags
& SI_CONTEXT_FLUSH_AND_INV_DB
)
888 sctx
->b
.num_db_cache_flushes
++;
890 /* SI has a bug that it always flushes ICACHE and KCACHE if either
891 * bit is set. An alternative way is to write SQC_CACHES, but that
892 * doesn't seem to work reliably. Since the bug doesn't affect
893 * correctness (it only does more work than necessary) and
894 * the performance impact is likely negligible, there is no plan
895 * to add a workaround for it.
898 if (flags
& SI_CONTEXT_INV_ICACHE
)
899 cp_coher_cntl
|= S_0085F0_SH_ICACHE_ACTION_ENA(1);
900 if (flags
& SI_CONTEXT_INV_SMEM_L1
)
901 cp_coher_cntl
|= S_0085F0_SH_KCACHE_ACTION_ENA(1);
903 if (sctx
->b
.chip_class
<= VI
) {
904 if (flags
& SI_CONTEXT_FLUSH_AND_INV_CB
) {
905 cp_coher_cntl
|= S_0085F0_CB_ACTION_ENA(1) |
906 S_0085F0_CB0_DEST_BASE_ENA(1) |
907 S_0085F0_CB1_DEST_BASE_ENA(1) |
908 S_0085F0_CB2_DEST_BASE_ENA(1) |
909 S_0085F0_CB3_DEST_BASE_ENA(1) |
910 S_0085F0_CB4_DEST_BASE_ENA(1) |
911 S_0085F0_CB5_DEST_BASE_ENA(1) |
912 S_0085F0_CB6_DEST_BASE_ENA(1) |
913 S_0085F0_CB7_DEST_BASE_ENA(1);
915 /* Necessary for DCC */
916 if (sctx
->b
.chip_class
== VI
)
917 si_gfx_write_event_eop(sctx
, V_028A90_FLUSH_AND_INV_CB_DATA_TS
,
918 0, EOP_DATA_SEL_DISCARD
, NULL
,
921 if (flags
& SI_CONTEXT_FLUSH_AND_INV_DB
)
922 cp_coher_cntl
|= S_0085F0_DB_ACTION_ENA(1) |
923 S_0085F0_DB_DEST_BASE_ENA(1);
926 if (flags
& SI_CONTEXT_FLUSH_AND_INV_CB
) {
927 /* Flush CMASK/FMASK/DCC. SURFACE_SYNC will wait for idle. */
928 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
929 radeon_emit(cs
, EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_META
) | EVENT_INDEX(0));
931 if (flags
& (SI_CONTEXT_FLUSH_AND_INV_DB
|
932 SI_CONTEXT_FLUSH_AND_INV_DB_META
)) {
933 /* Flush HTILE. SURFACE_SYNC will wait for idle. */
934 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
935 radeon_emit(cs
, EVENT_TYPE(V_028A90_FLUSH_AND_INV_DB_META
) | EVENT_INDEX(0));
938 /* Wait for shader engines to go idle.
939 * VS and PS waits are unnecessary if SURFACE_SYNC is going to wait
940 * for everything including CB/DB cache flushes.
943 if (flags
& SI_CONTEXT_PS_PARTIAL_FLUSH
) {
944 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
945 radeon_emit(cs
, EVENT_TYPE(V_028A90_PS_PARTIAL_FLUSH
) | EVENT_INDEX(4));
946 /* Only count explicit shader flushes, not implicit ones
947 * done by SURFACE_SYNC.
949 sctx
->b
.num_vs_flushes
++;
950 sctx
->b
.num_ps_flushes
++;
951 } else if (flags
& SI_CONTEXT_VS_PARTIAL_FLUSH
) {
952 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
953 radeon_emit(cs
, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH
) | EVENT_INDEX(4));
954 sctx
->b
.num_vs_flushes
++;
958 if (flags
& SI_CONTEXT_CS_PARTIAL_FLUSH
&&
959 sctx
->compute_is_busy
) {
960 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
961 radeon_emit(cs
, EVENT_TYPE(V_028A90_CS_PARTIAL_FLUSH
| EVENT_INDEX(4)));
962 sctx
->b
.num_cs_flushes
++;
963 sctx
->compute_is_busy
= false;
966 /* VGT state synchronization. */
967 if (flags
& SI_CONTEXT_VGT_FLUSH
) {
968 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
969 radeon_emit(cs
, EVENT_TYPE(V_028A90_VGT_FLUSH
) | EVENT_INDEX(0));
971 if (flags
& SI_CONTEXT_VGT_STREAMOUT_SYNC
) {
972 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
973 radeon_emit(cs
, EVENT_TYPE(V_028A90_VGT_STREAMOUT_SYNC
) | EVENT_INDEX(0));
976 /* GFX9: Wait for idle if we're flushing CB or DB. ACQUIRE_MEM doesn't
977 * wait for idle on GFX9. We have to use a TS event.
979 if (sctx
->b
.chip_class
>= GFX9
&& flush_cb_db
) {
981 unsigned tc_flags
, cb_db_event
;
983 /* Set the CB/DB flush event. */
984 switch (flush_cb_db
) {
985 case SI_CONTEXT_FLUSH_AND_INV_CB
:
986 cb_db_event
= V_028A90_FLUSH_AND_INV_CB_DATA_TS
;
988 case SI_CONTEXT_FLUSH_AND_INV_DB
:
989 cb_db_event
= V_028A90_FLUSH_AND_INV_DB_DATA_TS
;
993 cb_db_event
= V_028A90_CACHE_FLUSH_AND_INV_TS_EVENT
;
996 /* These are the only allowed combinations. If you need to
997 * do multiple operations at once, do them separately.
998 * All operations that invalidate L2 also seem to invalidate
999 * metadata. Volatile (VOL) and WC flushes are not listed here.
1001 * TC | TC_WB = writeback & invalidate L2 & L1
1002 * TC | TC_WB | TC_NC = writeback & invalidate L2 for MTYPE == NC
1003 * TC_WB | TC_NC = writeback L2 for MTYPE == NC
1004 * TC | TC_NC = invalidate L2 for MTYPE == NC
1005 * TC | TC_MD = writeback & invalidate L2 metadata (DCC, etc.)
1006 * TCL1 = invalidate L1
1010 if (flags
& SI_CONTEXT_INV_L2_METADATA
) {
1011 tc_flags
= EVENT_TC_ACTION_ENA
|
1012 EVENT_TC_MD_ACTION_ENA
;
1015 /* Ideally flush TC together with CB/DB. */
1016 if (flags
& SI_CONTEXT_INV_GLOBAL_L2
) {
1017 /* Writeback and invalidate everything in L2 & L1. */
1018 tc_flags
= EVENT_TC_ACTION_ENA
|
1019 EVENT_TC_WB_ACTION_ENA
;
1021 /* Clear the flags. */
1022 flags
&= ~(SI_CONTEXT_INV_GLOBAL_L2
|
1023 SI_CONTEXT_WRITEBACK_GLOBAL_L2
|
1024 SI_CONTEXT_INV_VMEM_L1
);
1025 sctx
->b
.num_L2_invalidates
++;
1028 /* Do the flush (enqueue the event and wait for it). */
1029 va
= sctx
->wait_mem_scratch
->gpu_address
;
1030 sctx
->wait_mem_number
++;
1032 si_gfx_write_event_eop(sctx
, cb_db_event
, tc_flags
,
1033 EOP_DATA_SEL_VALUE_32BIT
,
1034 sctx
->wait_mem_scratch
, va
,
1035 sctx
->wait_mem_number
, SI_NOT_QUERY
);
1036 si_gfx_wait_fence(sctx
, va
, sctx
->wait_mem_number
, 0xffffffff);
1039 /* Make sure ME is idle (it executes most packets) before continuing.
1040 * This prevents read-after-write hazards between PFP and ME.
1042 if (cp_coher_cntl
||
1043 (flags
& (SI_CONTEXT_CS_PARTIAL_FLUSH
|
1044 SI_CONTEXT_INV_VMEM_L1
|
1045 SI_CONTEXT_INV_GLOBAL_L2
|
1046 SI_CONTEXT_WRITEBACK_GLOBAL_L2
))) {
1047 radeon_emit(cs
, PKT3(PKT3_PFP_SYNC_ME
, 0, 0));
1052 * When one of the CP_COHER_CNTL.DEST_BASE flags is set, SURFACE_SYNC
1053 * waits for idle, so it should be last. SURFACE_SYNC is done in PFP.
1055 * cp_coher_cntl should contain all necessary flags except TC flags
1058 * SI-CIK don't support L2 write-back.
1060 if (flags
& SI_CONTEXT_INV_GLOBAL_L2
||
1061 (sctx
->b
.chip_class
<= CIK
&&
1062 (flags
& SI_CONTEXT_WRITEBACK_GLOBAL_L2
))) {
1063 /* Invalidate L1 & L2. (L1 is always invalidated on SI)
1064 * WB must be set on VI+ when TC_ACTION is set.
1066 si_emit_surface_sync(sctx
, cp_coher_cntl
|
1067 S_0085F0_TC_ACTION_ENA(1) |
1068 S_0085F0_TCL1_ACTION_ENA(1) |
1069 S_0301F0_TC_WB_ACTION_ENA(sctx
->b
.chip_class
>= VI
));
1071 sctx
->b
.num_L2_invalidates
++;
1073 /* L1 invalidation and L2 writeback must be done separately,
1074 * because both operations can't be done together.
1076 if (flags
& SI_CONTEXT_WRITEBACK_GLOBAL_L2
) {
1078 * NC = apply to non-coherent MTYPEs
1079 * (i.e. MTYPE <= 1, which is what we use everywhere)
1081 * WB doesn't work without NC.
1083 si_emit_surface_sync(sctx
, cp_coher_cntl
|
1084 S_0301F0_TC_WB_ACTION_ENA(1) |
1085 S_0301F0_TC_NC_ACTION_ENA(1));
1087 sctx
->b
.num_L2_writebacks
++;
1089 if (flags
& SI_CONTEXT_INV_VMEM_L1
) {
1090 /* Invalidate per-CU VMEM L1. */
1091 si_emit_surface_sync(sctx
, cp_coher_cntl
|
1092 S_0085F0_TCL1_ACTION_ENA(1));
1097 /* If TC flushes haven't cleared this... */
1099 si_emit_surface_sync(sctx
, cp_coher_cntl
);
1101 if (flags
& SI_CONTEXT_START_PIPELINE_STATS
) {
1102 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
1103 radeon_emit(cs
, EVENT_TYPE(V_028A90_PIPELINESTAT_START
) |
1105 } else if (flags
& SI_CONTEXT_STOP_PIPELINE_STATS
) {
1106 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
1107 radeon_emit(cs
, EVENT_TYPE(V_028A90_PIPELINESTAT_STOP
) |
1114 static void si_get_draw_start_count(struct si_context
*sctx
,
1115 const struct pipe_draw_info
*info
,
1116 unsigned *start
, unsigned *count
)
1118 struct pipe_draw_indirect_info
*indirect
= info
->indirect
;
1121 unsigned indirect_count
;
1122 struct pipe_transfer
*transfer
;
1123 unsigned begin
, end
;
1127 if (indirect
->indirect_draw_count
) {
1128 data
= pipe_buffer_map_range(&sctx
->b
.b
,
1129 indirect
->indirect_draw_count
,
1130 indirect
->indirect_draw_count_offset
,
1132 PIPE_TRANSFER_READ
, &transfer
);
1134 indirect_count
= *data
;
1136 pipe_buffer_unmap(&sctx
->b
.b
, transfer
);
1138 indirect_count
= indirect
->draw_count
;
1141 if (!indirect_count
) {
1142 *start
= *count
= 0;
1146 map_size
= (indirect_count
- 1) * indirect
->stride
+ 3 * sizeof(unsigned);
1147 data
= pipe_buffer_map_range(&sctx
->b
.b
, indirect
->buffer
,
1148 indirect
->offset
, map_size
,
1149 PIPE_TRANSFER_READ
, &transfer
);
1154 for (unsigned i
= 0; i
< indirect_count
; ++i
) {
1155 unsigned count
= data
[0];
1156 unsigned start
= data
[2];
1159 begin
= MIN2(begin
, start
);
1160 end
= MAX2(end
, start
+ count
);
1163 data
+= indirect
->stride
/ sizeof(unsigned);
1166 pipe_buffer_unmap(&sctx
->b
.b
, transfer
);
1170 *count
= end
- begin
;
1172 *start
= *count
= 0;
1175 *start
= info
->start
;
1176 *count
= info
->count
;
1180 static void si_emit_all_states(struct si_context
*sctx
, const struct pipe_draw_info
*info
,
1181 unsigned skip_atom_mask
)
1183 /* Emit state atoms. */
1184 unsigned mask
= sctx
->dirty_atoms
& ~skip_atom_mask
;
1186 struct r600_atom
*atom
= sctx
->atoms
.array
[u_bit_scan(&mask
)];
1188 atom
->emit(sctx
, atom
);
1190 sctx
->dirty_atoms
&= skip_atom_mask
;
1193 mask
= sctx
->dirty_states
;
1195 unsigned i
= u_bit_scan(&mask
);
1196 struct si_pm4_state
*state
= sctx
->queued
.array
[i
];
1198 if (!state
|| sctx
->emitted
.array
[i
] == state
)
1201 si_pm4_emit(sctx
, state
);
1202 sctx
->emitted
.array
[i
] = state
;
1204 sctx
->dirty_states
= 0;
1206 /* Emit draw states. */
1207 unsigned num_patches
= 0;
1209 si_emit_rasterizer_prim_state(sctx
);
1210 if (sctx
->tes_shader
.cso
)
1211 si_emit_derived_tess_state(sctx
, info
, &num_patches
);
1212 si_emit_vs_state(sctx
, info
);
1213 si_emit_draw_registers(sctx
, info
, num_patches
);
1216 void si_draw_vbo(struct pipe_context
*ctx
, const struct pipe_draw_info
*info
)
1218 struct si_context
*sctx
= (struct si_context
*)ctx
;
1219 struct si_state_rasterizer
*rs
= sctx
->queued
.named
.rasterizer
;
1220 struct pipe_resource
*indexbuf
= info
->index
.resource
;
1221 unsigned dirty_tex_counter
;
1222 enum pipe_prim_type rast_prim
;
1223 unsigned index_size
= info
->index_size
;
1224 unsigned index_offset
= info
->indirect
? info
->start
* index_size
: 0;
1226 if (likely(!info
->indirect
)) {
1227 /* SI-CI treat instance_count==0 as instance_count==1. There is
1228 * no workaround for indirect draws, but we can at least skip
1231 if (unlikely(!info
->instance_count
))
1234 /* Handle count == 0. */
1235 if (unlikely(!info
->count
&&
1236 (index_size
|| !info
->count_from_stream_output
)))
1240 if (unlikely(!sctx
->vs_shader
.cso
)) {
1244 if (unlikely(!sctx
->ps_shader
.cso
&& (!rs
|| !rs
->rasterizer_discard
))) {
1248 if (unlikely(!!sctx
->tes_shader
.cso
!= (info
->mode
== PIPE_PRIM_PATCHES
))) {
1253 /* Recompute and re-emit the texture resource states if needed. */
1254 dirty_tex_counter
= p_atomic_read(&sctx
->b
.screen
->dirty_tex_counter
);
1255 if (unlikely(dirty_tex_counter
!= sctx
->b
.last_dirty_tex_counter
)) {
1256 sctx
->b
.last_dirty_tex_counter
= dirty_tex_counter
;
1257 sctx
->framebuffer
.dirty_cbufs
|=
1258 ((1 << sctx
->framebuffer
.state
.nr_cbufs
) - 1);
1259 sctx
->framebuffer
.dirty_zsbuf
= true;
1260 si_mark_atom_dirty(sctx
, &sctx
->framebuffer
.atom
);
1261 si_update_all_texture_descriptors(sctx
);
1264 si_decompress_textures(sctx
, u_bit_consecutive(0, SI_NUM_GRAPHICS_SHADERS
));
1266 /* Set the rasterization primitive type.
1268 * This must be done after si_decompress_textures, which can call
1269 * draw_vbo recursively, and before si_update_shaders, which uses
1270 * current_rast_prim for this draw_vbo call. */
1271 if (sctx
->gs_shader
.cso
)
1272 rast_prim
= sctx
->gs_shader
.cso
->gs_output_prim
;
1273 else if (sctx
->tes_shader
.cso
) {
1274 if (sctx
->tes_shader
.cso
->info
.properties
[TGSI_PROPERTY_TES_POINT_MODE
])
1275 rast_prim
= PIPE_PRIM_POINTS
;
1277 rast_prim
= sctx
->tes_shader
.cso
->info
.properties
[TGSI_PROPERTY_TES_PRIM_MODE
];
1279 rast_prim
= info
->mode
;
1281 if (rast_prim
!= sctx
->current_rast_prim
) {
1282 bool old_is_poly
= sctx
->current_rast_prim
>= PIPE_PRIM_TRIANGLES
;
1283 bool new_is_poly
= rast_prim
>= PIPE_PRIM_TRIANGLES
;
1284 if (old_is_poly
!= new_is_poly
) {
1285 sctx
->scissors
.dirty_mask
= (1 << SI_MAX_VIEWPORTS
) - 1;
1286 si_mark_atom_dirty(sctx
, &sctx
->scissors
.atom
);
1289 sctx
->current_rast_prim
= rast_prim
;
1290 sctx
->do_update_shaders
= true;
1293 if (sctx
->tes_shader
.cso
&&
1294 sctx
->screen
->has_ls_vgpr_init_bug
) {
1295 /* Determine whether the LS VGPR fix should be applied.
1297 * It is only required when num input CPs > num output CPs,
1298 * which cannot happen with the fixed function TCS. We should
1299 * also update this bit when switching from TCS to fixed
1302 struct si_shader_selector
*tcs
= sctx
->tcs_shader
.cso
;
1305 info
->vertices_per_patch
>
1306 tcs
->info
.properties
[TGSI_PROPERTY_TCS_VERTICES_OUT
];
1308 if (ls_vgpr_fix
!= sctx
->ls_vgpr_fix
) {
1309 sctx
->ls_vgpr_fix
= ls_vgpr_fix
;
1310 sctx
->do_update_shaders
= true;
1314 if (sctx
->gs_shader
.cso
) {
1315 /* Determine whether the GS triangle strip adjacency fix should
1316 * be applied. Rotate every other triangle if
1317 * - triangle strips with adjacency are fed to the GS and
1318 * - primitive restart is disabled (the rotation doesn't help
1319 * when the restart occurs after an odd number of triangles).
1321 bool gs_tri_strip_adj_fix
=
1322 !sctx
->tes_shader
.cso
&&
1323 info
->mode
== PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY
&&
1324 !info
->primitive_restart
;
1326 if (gs_tri_strip_adj_fix
!= sctx
->gs_tri_strip_adj_fix
) {
1327 sctx
->gs_tri_strip_adj_fix
= gs_tri_strip_adj_fix
;
1328 sctx
->do_update_shaders
= true;
1332 if (sctx
->do_update_shaders
&& !si_update_shaders(sctx
))
1336 /* Translate or upload, if needed. */
1337 /* 8-bit indices are supported on VI. */
1338 if (sctx
->b
.chip_class
<= CIK
&& index_size
== 1) {
1339 unsigned start
, count
, start_offset
, size
, offset
;
1342 si_get_draw_start_count(sctx
, info
, &start
, &count
);
1343 start_offset
= start
* 2;
1347 u_upload_alloc(ctx
->stream_uploader
, start_offset
,
1349 si_optimal_tcc_alignment(sctx
, size
),
1350 &offset
, &indexbuf
, &ptr
);
1354 util_shorten_ubyte_elts_to_userptr(&sctx
->b
.b
, info
, 0, 0,
1355 index_offset
+ start
,
1358 /* info->start will be added by the drawing code */
1359 index_offset
= offset
- start_offset
;
1361 } else if (info
->has_user_indices
) {
1362 unsigned start_offset
;
1364 assert(!info
->indirect
);
1365 start_offset
= info
->start
* index_size
;
1368 u_upload_data(ctx
->stream_uploader
, start_offset
,
1369 info
->count
* index_size
,
1370 sctx
->screen
->info
.tcc_cache_line_size
,
1371 (char*)info
->index
.user
+ start_offset
,
1372 &index_offset
, &indexbuf
);
1376 /* info->start will be added by the drawing code */
1377 index_offset
-= start_offset
;
1378 } else if (sctx
->b
.chip_class
<= CIK
&&
1379 r600_resource(indexbuf
)->TC_L2_dirty
) {
1380 /* VI reads index buffers through TC L2, so it doesn't
1382 sctx
->b
.flags
|= SI_CONTEXT_WRITEBACK_GLOBAL_L2
;
1383 r600_resource(indexbuf
)->TC_L2_dirty
= false;
1387 if (info
->indirect
) {
1388 struct pipe_draw_indirect_info
*indirect
= info
->indirect
;
1390 /* Add the buffer size for memory checking in need_cs_space. */
1391 si_context_add_resource_size(sctx
, indirect
->buffer
);
1393 /* Indirect buffers use TC L2 on GFX9, but not older hw. */
1394 if (sctx
->b
.chip_class
<= VI
) {
1395 if (r600_resource(indirect
->buffer
)->TC_L2_dirty
) {
1396 sctx
->b
.flags
|= SI_CONTEXT_WRITEBACK_GLOBAL_L2
;
1397 r600_resource(indirect
->buffer
)->TC_L2_dirty
= false;
1400 if (indirect
->indirect_draw_count
&&
1401 r600_resource(indirect
->indirect_draw_count
)->TC_L2_dirty
) {
1402 sctx
->b
.flags
|= SI_CONTEXT_WRITEBACK_GLOBAL_L2
;
1403 r600_resource(indirect
->indirect_draw_count
)->TC_L2_dirty
= false;
1408 si_need_gfx_cs_space(sctx
);
1410 /* Since we've called r600_context_add_resource_size for vertex buffers,
1411 * this must be called after si_need_cs_space, because we must let
1412 * need_cs_space flush before we add buffers to the buffer list.
1414 if (!si_upload_vertex_buffer_descriptors(sctx
))
1417 /* Vega10/Raven scissor bug workaround. This must be done before VPORT
1418 * scissor registers are changed. There is also a more efficient but
1419 * more involved alternative workaround.
1421 if ((sctx
->b
.family
== CHIP_VEGA10
|| sctx
->b
.family
== CHIP_RAVEN
) &&
1422 si_is_atom_dirty(sctx
, &sctx
->scissors
.atom
)) {
1423 sctx
->b
.flags
|= SI_CONTEXT_PS_PARTIAL_FLUSH
;
1424 si_emit_cache_flush(sctx
);
1427 /* Use optimal packet order based on whether we need to sync the pipeline. */
1428 if (unlikely(sctx
->b
.flags
& (SI_CONTEXT_FLUSH_AND_INV_CB
|
1429 SI_CONTEXT_FLUSH_AND_INV_DB
|
1430 SI_CONTEXT_PS_PARTIAL_FLUSH
|
1431 SI_CONTEXT_CS_PARTIAL_FLUSH
))) {
1432 /* If we have to wait for idle, set all states first, so that all
1433 * SET packets are processed in parallel with previous draw calls.
1434 * Then upload descriptors, set shader pointers, and draw, and
1435 * prefetch at the end. This ensures that the time the CUs
1436 * are idle is very short. (there are only SET_SH packets between
1437 * the wait and the draw)
1439 struct r600_atom
*shader_pointers
= &sctx
->shader_pointers
.atom
;
1440 unsigned masked_atoms
= 1u << shader_pointers
->id
;
1442 if (unlikely(sctx
->b
.flags
& SI_CONTEXT_FLUSH_FOR_RENDER_COND
))
1443 masked_atoms
|= 1u << sctx
->b
.render_cond_atom
.id
;
1445 /* Emit all states except shader pointers and render condition. */
1446 si_emit_all_states(sctx
, info
, masked_atoms
);
1447 si_emit_cache_flush(sctx
);
1449 /* <-- CUs are idle here. */
1450 if (!si_upload_graphics_shader_descriptors(sctx
))
1453 /* Set shader pointers after descriptors are uploaded. */
1454 if (si_is_atom_dirty(sctx
, shader_pointers
))
1455 shader_pointers
->emit(sctx
, NULL
);
1456 if (si_is_atom_dirty(sctx
, &sctx
->b
.render_cond_atom
))
1457 sctx
->b
.render_cond_atom
.emit(sctx
, NULL
);
1458 sctx
->dirty_atoms
= 0;
1460 si_emit_draw_packets(sctx
, info
, indexbuf
, index_size
, index_offset
);
1461 /* <-- CUs are busy here. */
1463 /* Start prefetches after the draw has been started. Both will run
1464 * in parallel, but starting the draw first is more important.
1466 if (sctx
->b
.chip_class
>= CIK
&& sctx
->prefetch_L2_mask
)
1467 cik_emit_prefetch_L2(sctx
);
1469 /* If we don't wait for idle, start prefetches first, then set
1470 * states, and draw at the end.
1473 si_emit_cache_flush(sctx
);
1475 if (sctx
->b
.chip_class
>= CIK
&& sctx
->prefetch_L2_mask
)
1476 cik_emit_prefetch_L2(sctx
);
1478 if (!si_upload_graphics_shader_descriptors(sctx
))
1481 si_emit_all_states(sctx
, info
, 0);
1482 si_emit_draw_packets(sctx
, info
, indexbuf
, index_size
, index_offset
);
1485 if (unlikely(sctx
->current_saved_cs
)) {
1486 si_trace_emit(sctx
);
1487 si_log_draw_state(sctx
, sctx
->b
.log
);
1490 /* Workaround for a VGT hang when streamout is enabled.
1491 * It must be done after drawing. */
1492 if ((sctx
->b
.family
== CHIP_HAWAII
||
1493 sctx
->b
.family
== CHIP_TONGA
||
1494 sctx
->b
.family
== CHIP_FIJI
) &&
1495 si_get_strmout_en(sctx
)) {
1496 sctx
->b
.flags
|= SI_CONTEXT_VGT_STREAMOUT_SYNC
;
1499 if (unlikely(sctx
->decompression_enabled
)) {
1500 sctx
->b
.num_decompress_calls
++;
1502 sctx
->b
.num_draw_calls
++;
1503 if (sctx
->framebuffer
.state
.nr_cbufs
> 1)
1504 sctx
->b
.num_mrt_draw_calls
++;
1505 if (info
->primitive_restart
)
1506 sctx
->b
.num_prim_restart_calls
++;
1507 if (G_0286E8_WAVESIZE(sctx
->spi_tmpring_size
))
1508 sctx
->b
.num_spill_draw_calls
++;
1510 if (index_size
&& indexbuf
!= info
->index
.resource
)
1511 pipe_resource_reference(&indexbuf
, NULL
);
1514 void si_draw_rectangle(struct blitter_context
*blitter
,
1515 void *vertex_elements_cso
,
1516 blitter_get_vs_func get_vs
,
1517 int x1
, int y1
, int x2
, int y2
,
1518 float depth
, unsigned num_instances
,
1519 enum blitter_attrib_type type
,
1520 const union blitter_attrib
*attrib
)
1522 struct pipe_context
*pipe
= util_blitter_get_pipe(blitter
);
1523 struct si_context
*sctx
= (struct si_context
*)pipe
;
1525 /* Pack position coordinates as signed int16. */
1526 sctx
->vs_blit_sh_data
[0] = (uint32_t)(x1
& 0xffff) |
1527 ((uint32_t)(y1
& 0xffff) << 16);
1528 sctx
->vs_blit_sh_data
[1] = (uint32_t)(x2
& 0xffff) |
1529 ((uint32_t)(y2
& 0xffff) << 16);
1530 sctx
->vs_blit_sh_data
[2] = fui(depth
);
1533 case UTIL_BLITTER_ATTRIB_COLOR
:
1534 memcpy(&sctx
->vs_blit_sh_data
[3], attrib
->color
,
1537 case UTIL_BLITTER_ATTRIB_TEXCOORD_XY
:
1538 case UTIL_BLITTER_ATTRIB_TEXCOORD_XYZW
:
1539 memcpy(&sctx
->vs_blit_sh_data
[3], &attrib
->texcoord
,
1540 sizeof(attrib
->texcoord
));
1542 case UTIL_BLITTER_ATTRIB_NONE
:;
1545 pipe
->bind_vs_state(pipe
, si_get_blit_vs(sctx
, type
, num_instances
));
1547 struct pipe_draw_info info
= {};
1548 info
.mode
= SI_PRIM_RECTANGLE_LIST
;
1550 info
.instance_count
= num_instances
;
1552 /* Don't set per-stage shader pointers for VS. */
1553 sctx
->shader_pointers_dirty
&= ~SI_DESCS_SHADER_MASK(VERTEX
);
1554 sctx
->vertex_buffer_pointer_dirty
= false;
1556 si_draw_vbo(pipe
, &info
);
1559 void si_trace_emit(struct si_context
*sctx
)
1561 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx_cs
;
1562 uint64_t va
= sctx
->current_saved_cs
->trace_buf
->gpu_address
;
1563 uint32_t trace_id
= ++sctx
->current_saved_cs
->trace_id
;
1565 radeon_emit(cs
, PKT3(PKT3_WRITE_DATA
, 3, 0));
1566 radeon_emit(cs
, S_370_DST_SEL(V_370_MEMORY_SYNC
) |
1567 S_370_WR_CONFIRM(1) |
1568 S_370_ENGINE_SEL(V_370_ME
));
1569 radeon_emit(cs
, va
);
1570 radeon_emit(cs
, va
>> 32);
1571 radeon_emit(cs
, trace_id
);
1572 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
1573 radeon_emit(cs
, AC_ENCODE_TRACE_POINT(trace_id
));
1576 u_log_flush(sctx
->b
.log
);