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[mesa.git] / src / gallium / drivers / radeonsi / si_state_draw.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Christian König <christian.koenig@amd.com>
25 */
26
27 #include "si_pipe.h"
28 #include "si_shader.h"
29 #include "radeon/r600_cs.h"
30 #include "sid.h"
31
32 #include "util/u_index_modify.h"
33 #include "util/u_upload_mgr.h"
34 #include "util/u_prim.h"
35 #include "util/u_memory.h"
36
37 static unsigned si_conv_pipe_prim(unsigned mode)
38 {
39 static const unsigned prim_conv[] = {
40 [PIPE_PRIM_POINTS] = V_008958_DI_PT_POINTLIST,
41 [PIPE_PRIM_LINES] = V_008958_DI_PT_LINELIST,
42 [PIPE_PRIM_LINE_LOOP] = V_008958_DI_PT_LINELOOP,
43 [PIPE_PRIM_LINE_STRIP] = V_008958_DI_PT_LINESTRIP,
44 [PIPE_PRIM_TRIANGLES] = V_008958_DI_PT_TRILIST,
45 [PIPE_PRIM_TRIANGLE_STRIP] = V_008958_DI_PT_TRISTRIP,
46 [PIPE_PRIM_TRIANGLE_FAN] = V_008958_DI_PT_TRIFAN,
47 [PIPE_PRIM_QUADS] = V_008958_DI_PT_QUADLIST,
48 [PIPE_PRIM_QUAD_STRIP] = V_008958_DI_PT_QUADSTRIP,
49 [PIPE_PRIM_POLYGON] = V_008958_DI_PT_POLYGON,
50 [PIPE_PRIM_LINES_ADJACENCY] = V_008958_DI_PT_LINELIST_ADJ,
51 [PIPE_PRIM_LINE_STRIP_ADJACENCY] = V_008958_DI_PT_LINESTRIP_ADJ,
52 [PIPE_PRIM_TRIANGLES_ADJACENCY] = V_008958_DI_PT_TRILIST_ADJ,
53 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY] = V_008958_DI_PT_TRISTRIP_ADJ,
54 [PIPE_PRIM_PATCHES] = V_008958_DI_PT_PATCH,
55 [R600_PRIM_RECTANGLE_LIST] = V_008958_DI_PT_RECTLIST
56 };
57 assert(mode < ARRAY_SIZE(prim_conv));
58 return prim_conv[mode];
59 }
60
61 static unsigned si_conv_prim_to_gs_out(unsigned mode)
62 {
63 static const int prim_conv[] = {
64 [PIPE_PRIM_POINTS] = V_028A6C_OUTPRIM_TYPE_POINTLIST,
65 [PIPE_PRIM_LINES] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
66 [PIPE_PRIM_LINE_LOOP] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
67 [PIPE_PRIM_LINE_STRIP] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
68 [PIPE_PRIM_TRIANGLES] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
69 [PIPE_PRIM_TRIANGLE_STRIP] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
70 [PIPE_PRIM_TRIANGLE_FAN] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
71 [PIPE_PRIM_QUADS] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
72 [PIPE_PRIM_QUAD_STRIP] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
73 [PIPE_PRIM_POLYGON] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
74 [PIPE_PRIM_LINES_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
75 [PIPE_PRIM_LINE_STRIP_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
76 [PIPE_PRIM_TRIANGLES_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
77 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
78 [PIPE_PRIM_PATCHES] = V_028A6C_OUTPRIM_TYPE_POINTLIST,
79 [R600_PRIM_RECTANGLE_LIST] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
80 };
81 assert(mode < ARRAY_SIZE(prim_conv));
82
83 return prim_conv[mode];
84 }
85
86 /**
87 * This calculates the LDS size for tessellation shaders (VS, TCS, TES).
88 * LS.LDS_SIZE is shared by all 3 shader stages.
89 *
90 * The information about LDS and other non-compile-time parameters is then
91 * written to userdata SGPRs.
92 */
93 static void si_emit_derived_tess_state(struct si_context *sctx,
94 const struct pipe_draw_info *info,
95 unsigned *num_patches)
96 {
97 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
98 struct si_shader_ctx_state *ls = &sctx->vs_shader;
99 /* The TES pointer will only be used for sctx->last_tcs.
100 * It would be wrong to think that TCS = TES. */
101 struct si_shader_selector *tcs =
102 sctx->tcs_shader.cso ? sctx->tcs_shader.cso : sctx->tes_shader.cso;
103 unsigned tes_sh_base = sctx->shader_userdata.sh_base[PIPE_SHADER_TESS_EVAL];
104 unsigned num_tcs_input_cp = info->vertices_per_patch;
105 unsigned num_tcs_output_cp, num_tcs_inputs, num_tcs_outputs;
106 unsigned num_tcs_patch_outputs;
107 unsigned input_vertex_size, output_vertex_size, pervertex_output_patch_size;
108 unsigned input_patch_size, output_patch_size, output_patch0_offset;
109 unsigned perpatch_output_offset, lds_size, ls_rsrc2;
110 unsigned tcs_in_layout, tcs_out_layout, tcs_out_offsets;
111 unsigned offchip_layout;
112
113 *num_patches = 1; /* TODO: calculate this */
114
115 if (sctx->last_ls == ls->current &&
116 sctx->last_tcs == tcs &&
117 sctx->last_tes_sh_base == tes_sh_base &&
118 sctx->last_num_tcs_input_cp == num_tcs_input_cp)
119 return;
120
121 sctx->last_ls = ls->current;
122 sctx->last_tcs = tcs;
123 sctx->last_tes_sh_base = tes_sh_base;
124 sctx->last_num_tcs_input_cp = num_tcs_input_cp;
125
126 /* This calculates how shader inputs and outputs among VS, TCS, and TES
127 * are laid out in LDS. */
128 num_tcs_inputs = util_last_bit64(ls->cso->outputs_written);
129
130 if (sctx->tcs_shader.cso) {
131 num_tcs_outputs = util_last_bit64(tcs->outputs_written);
132 num_tcs_output_cp = tcs->info.properties[TGSI_PROPERTY_TCS_VERTICES_OUT];
133 num_tcs_patch_outputs = util_last_bit64(tcs->patch_outputs_written);
134 } else {
135 /* No TCS. Route varyings from LS to TES. */
136 num_tcs_outputs = num_tcs_inputs;
137 num_tcs_output_cp = num_tcs_input_cp;
138 num_tcs_patch_outputs = 2; /* TESSINNER + TESSOUTER */
139 }
140
141 input_vertex_size = num_tcs_inputs * 16;
142 output_vertex_size = num_tcs_outputs * 16;
143
144 input_patch_size = num_tcs_input_cp * input_vertex_size;
145
146 pervertex_output_patch_size = num_tcs_output_cp * output_vertex_size;
147 output_patch_size = pervertex_output_patch_size + num_tcs_patch_outputs * 16;
148
149 output_patch0_offset = sctx->tcs_shader.cso ? input_patch_size * *num_patches : 0;
150 perpatch_output_offset = output_patch0_offset + pervertex_output_patch_size;
151
152 lds_size = output_patch0_offset + output_patch_size * *num_patches;
153 ls_rsrc2 = ls->current->config.rsrc2;
154
155 if (sctx->b.chip_class >= CIK) {
156 assert(lds_size <= 65536);
157 ls_rsrc2 |= S_00B52C_LDS_SIZE(align(lds_size, 512) / 512);
158 } else {
159 assert(lds_size <= 32768);
160 ls_rsrc2 |= S_00B52C_LDS_SIZE(align(lds_size, 256) / 256);
161 }
162
163 /* Due to a hw bug, RSRC2_LS must be written twice with another
164 * LS register written in between. */
165 if (sctx->b.chip_class == CIK && sctx->b.family != CHIP_HAWAII)
166 radeon_set_sh_reg(cs, R_00B52C_SPI_SHADER_PGM_RSRC2_LS, ls_rsrc2);
167 radeon_set_sh_reg_seq(cs, R_00B528_SPI_SHADER_PGM_RSRC1_LS, 2);
168 radeon_emit(cs, ls->current->config.rsrc1);
169 radeon_emit(cs, ls_rsrc2);
170
171 /* Compute userdata SGPRs. */
172 assert(((input_vertex_size / 4) & ~0xff) == 0);
173 assert(((output_vertex_size / 4) & ~0xff) == 0);
174 assert(((input_patch_size / 4) & ~0x1fff) == 0);
175 assert(((output_patch_size / 4) & ~0x1fff) == 0);
176 assert(((output_patch0_offset / 16) & ~0xffff) == 0);
177 assert(((perpatch_output_offset / 16) & ~0xffff) == 0);
178 assert(num_tcs_input_cp <= 32);
179 assert(num_tcs_output_cp <= 32);
180
181 tcs_in_layout = (input_patch_size / 4) |
182 ((input_vertex_size / 4) << 13);
183 tcs_out_layout = (output_patch_size / 4) |
184 ((output_vertex_size / 4) << 13);
185 tcs_out_offsets = (output_patch0_offset / 16) |
186 ((perpatch_output_offset / 16) << 16);
187 offchip_layout = (pervertex_output_patch_size * *num_patches << 16) |
188 (num_tcs_output_cp << 9) | *num_patches;
189
190 /* Set them for LS. */
191 radeon_set_sh_reg(cs,
192 R_00B530_SPI_SHADER_USER_DATA_LS_0 + SI_SGPR_LS_OUT_LAYOUT * 4,
193 tcs_in_layout);
194
195 /* Set them for TCS. */
196 radeon_set_sh_reg_seq(cs,
197 R_00B430_SPI_SHADER_USER_DATA_HS_0 + SI_SGPR_TCS_OFFCHIP_LAYOUT * 4, 4);
198 radeon_emit(cs, offchip_layout);
199 radeon_emit(cs, tcs_out_offsets);
200 radeon_emit(cs, tcs_out_layout | (num_tcs_input_cp << 26));
201 radeon_emit(cs, tcs_in_layout);
202
203 /* Set them for TES. */
204 radeon_set_sh_reg_seq(cs, tes_sh_base + SI_SGPR_TCS_OFFCHIP_LAYOUT * 4, 3);
205 radeon_emit(cs, offchip_layout);
206 radeon_emit(cs, tcs_out_offsets);
207 radeon_emit(cs, tcs_out_layout | (num_tcs_output_cp << 26));
208 }
209
210 static unsigned si_num_prims_for_vertices(const struct pipe_draw_info *info)
211 {
212 switch (info->mode) {
213 case PIPE_PRIM_PATCHES:
214 return info->count / info->vertices_per_patch;
215 case R600_PRIM_RECTANGLE_LIST:
216 return info->count / 3;
217 default:
218 return u_prims_for_vertices(info->mode, info->count);
219 }
220 }
221
222 static unsigned si_get_ia_multi_vgt_param(struct si_context *sctx,
223 const struct pipe_draw_info *info,
224 unsigned num_patches)
225 {
226 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
227 unsigned prim = info->mode;
228 unsigned primgroup_size = 128; /* recommended without a GS */
229 unsigned max_primgroup_in_wave = 2;
230
231 /* SWITCH_ON_EOP(0) is always preferable. */
232 bool wd_switch_on_eop = false;
233 bool ia_switch_on_eop = false;
234 bool ia_switch_on_eoi = false;
235 bool partial_vs_wave = false;
236 bool partial_es_wave = false;
237
238 if (sctx->gs_shader.cso)
239 primgroup_size = 64; /* recommended with a GS */
240
241 if (sctx->tes_shader.cso) {
242 unsigned num_cp_out =
243 sctx->tcs_shader.cso ?
244 sctx->tcs_shader.cso->info.properties[TGSI_PROPERTY_TCS_VERTICES_OUT] :
245 info->vertices_per_patch;
246 unsigned max_size = 256 / MAX2(info->vertices_per_patch, num_cp_out);
247
248 primgroup_size = MIN2(primgroup_size, max_size);
249
250 /* primgroup_size must be set to a multiple of NUM_PATCHES */
251 primgroup_size = (primgroup_size / num_patches) * num_patches;
252
253 /* SWITCH_ON_EOI must be set if PrimID is used. */
254 if ((sctx->tcs_shader.cso && sctx->tcs_shader.cso->info.uses_primid) ||
255 sctx->tes_shader.cso->info.uses_primid)
256 ia_switch_on_eoi = true;
257
258 /* Bug with tessellation and GS on Bonaire and older 2 SE chips. */
259 if ((sctx->b.family == CHIP_TAHITI ||
260 sctx->b.family == CHIP_PITCAIRN ||
261 sctx->b.family == CHIP_BONAIRE) &&
262 sctx->gs_shader.cso)
263 partial_vs_wave = true;
264 }
265
266 /* This is a hardware requirement. */
267 if ((rs && rs->line_stipple_enable) ||
268 (sctx->b.screen->debug_flags & DBG_SWITCH_ON_EOP)) {
269 ia_switch_on_eop = true;
270 wd_switch_on_eop = true;
271 }
272
273 if (sctx->b.chip_class >= CIK) {
274 /* WD_SWITCH_ON_EOP has no effect on GPUs with less than
275 * 4 shader engines. Set 1 to pass the assertion below.
276 * The other cases are hardware requirements. */
277 if (sctx->b.screen->info.max_se < 4 ||
278 prim == PIPE_PRIM_POLYGON ||
279 prim == PIPE_PRIM_LINE_LOOP ||
280 prim == PIPE_PRIM_TRIANGLE_FAN ||
281 prim == PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY ||
282 info->primitive_restart ||
283 info->count_from_stream_output)
284 wd_switch_on_eop = true;
285
286 /* Hawaii hangs if instancing is enabled and WD_SWITCH_ON_EOP is 0.
287 * We don't know that for indirect drawing, so treat it as
288 * always problematic. */
289 if (sctx->b.family == CHIP_HAWAII &&
290 (info->indirect || info->instance_count > 1))
291 wd_switch_on_eop = true;
292
293 /* Required on CIK and later. */
294 if (sctx->b.screen->info.max_se > 2 && !wd_switch_on_eop)
295 ia_switch_on_eoi = true;
296
297 /* Required by Hawaii and, for some special cases, by VI. */
298 if (ia_switch_on_eoi &&
299 (sctx->b.family == CHIP_HAWAII ||
300 (sctx->b.chip_class == VI &&
301 (sctx->gs_shader.cso || max_primgroup_in_wave != 2))))
302 partial_vs_wave = true;
303
304 /* Instancing bug on Bonaire. */
305 if (sctx->b.family == CHIP_BONAIRE && ia_switch_on_eoi &&
306 (info->indirect || info->instance_count > 1))
307 partial_vs_wave = true;
308
309 /* If the WD switch is false, the IA switch must be false too. */
310 assert(wd_switch_on_eop || !ia_switch_on_eop);
311 }
312
313 /* If SWITCH_ON_EOI is set, PARTIAL_ES_WAVE must be set too. */
314 if (ia_switch_on_eoi)
315 partial_es_wave = true;
316
317 /* GS requirement. */
318 if (SI_GS_PER_ES / primgroup_size >= sctx->screen->gs_table_depth - 3)
319 partial_es_wave = true;
320
321 /* Hw bug with single-primitive instances and SWITCH_ON_EOI
322 * on multi-SE chips. */
323 if (sctx->b.screen->info.max_se >= 2 && ia_switch_on_eoi &&
324 (info->indirect ||
325 (info->instance_count > 1 &&
326 si_num_prims_for_vertices(info) <= 1)))
327 sctx->b.flags |= SI_CONTEXT_VGT_FLUSH;
328
329 return S_028AA8_SWITCH_ON_EOP(ia_switch_on_eop) |
330 S_028AA8_SWITCH_ON_EOI(ia_switch_on_eoi) |
331 S_028AA8_PARTIAL_VS_WAVE_ON(partial_vs_wave) |
332 S_028AA8_PARTIAL_ES_WAVE_ON(partial_es_wave) |
333 S_028AA8_PRIMGROUP_SIZE(primgroup_size - 1) |
334 S_028AA8_WD_SWITCH_ON_EOP(sctx->b.chip_class >= CIK ? wd_switch_on_eop : 0) |
335 S_028AA8_MAX_PRIMGRP_IN_WAVE(sctx->b.chip_class >= VI ?
336 max_primgroup_in_wave : 0);
337 }
338
339 static unsigned si_get_ls_hs_config(struct si_context *sctx,
340 const struct pipe_draw_info *info,
341 unsigned num_patches)
342 {
343 unsigned num_output_cp;
344
345 if (!sctx->tes_shader.cso)
346 return 0;
347
348 num_output_cp = sctx->tcs_shader.cso ?
349 sctx->tcs_shader.cso->info.properties[TGSI_PROPERTY_TCS_VERTICES_OUT] :
350 info->vertices_per_patch;
351
352 return S_028B58_NUM_PATCHES(num_patches) |
353 S_028B58_HS_NUM_INPUT_CP(info->vertices_per_patch) |
354 S_028B58_HS_NUM_OUTPUT_CP(num_output_cp);
355 }
356
357 static void si_emit_scratch_reloc(struct si_context *sctx)
358 {
359 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
360
361 if (!sctx->emit_scratch_reloc)
362 return;
363
364 radeon_set_context_reg(cs, R_0286E8_SPI_TMPRING_SIZE,
365 sctx->spi_tmpring_size);
366
367 if (sctx->scratch_buffer) {
368 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
369 sctx->scratch_buffer, RADEON_USAGE_READWRITE,
370 RADEON_PRIO_SCRATCH_BUFFER);
371
372 }
373 sctx->emit_scratch_reloc = false;
374 }
375
376 /* rast_prim is the primitive type after GS. */
377 static void si_emit_rasterizer_prim_state(struct si_context *sctx)
378 {
379 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
380 unsigned rast_prim = sctx->current_rast_prim;
381 struct si_state_rasterizer *rs = sctx->emitted.named.rasterizer;
382
383 /* Skip this if not rendering lines. */
384 if (rast_prim != PIPE_PRIM_LINES &&
385 rast_prim != PIPE_PRIM_LINE_LOOP &&
386 rast_prim != PIPE_PRIM_LINE_STRIP &&
387 rast_prim != PIPE_PRIM_LINES_ADJACENCY &&
388 rast_prim != PIPE_PRIM_LINE_STRIP_ADJACENCY)
389 return;
390
391 if (rast_prim == sctx->last_rast_prim &&
392 rs->pa_sc_line_stipple == sctx->last_sc_line_stipple)
393 return;
394
395 radeon_set_context_reg(cs, R_028A0C_PA_SC_LINE_STIPPLE,
396 rs->pa_sc_line_stipple |
397 S_028A0C_AUTO_RESET_CNTL(rast_prim == PIPE_PRIM_LINES ? 1 :
398 rast_prim == PIPE_PRIM_LINE_STRIP ? 2 : 0));
399
400 sctx->last_rast_prim = rast_prim;
401 sctx->last_sc_line_stipple = rs->pa_sc_line_stipple;
402 }
403
404 static void si_emit_draw_registers(struct si_context *sctx,
405 const struct pipe_draw_info *info)
406 {
407 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
408 unsigned prim = si_conv_pipe_prim(info->mode);
409 unsigned gs_out_prim = si_conv_prim_to_gs_out(sctx->current_rast_prim);
410 unsigned ia_multi_vgt_param, ls_hs_config, num_patches = 0;
411
412 if (sctx->tes_shader.cso)
413 si_emit_derived_tess_state(sctx, info, &num_patches);
414
415 ia_multi_vgt_param = si_get_ia_multi_vgt_param(sctx, info, num_patches);
416 ls_hs_config = si_get_ls_hs_config(sctx, info, num_patches);
417
418 /* Draw state. */
419 if (prim != sctx->last_prim ||
420 ia_multi_vgt_param != sctx->last_multi_vgt_param ||
421 ls_hs_config != sctx->last_ls_hs_config) {
422 if (sctx->b.chip_class >= CIK) {
423 radeon_emit(cs, PKT3(PKT3_DRAW_PREAMBLE, 2, 0));
424 radeon_emit(cs, prim); /* VGT_PRIMITIVE_TYPE */
425 radeon_emit(cs, ia_multi_vgt_param); /* IA_MULTI_VGT_PARAM */
426 radeon_emit(cs, ls_hs_config); /* VGT_LS_HS_CONFIG */
427 } else {
428 radeon_set_config_reg(cs, R_008958_VGT_PRIMITIVE_TYPE, prim);
429 radeon_set_context_reg(cs, R_028AA8_IA_MULTI_VGT_PARAM, ia_multi_vgt_param);
430 radeon_set_context_reg(cs, R_028B58_VGT_LS_HS_CONFIG, ls_hs_config);
431 }
432 sctx->last_prim = prim;
433 sctx->last_multi_vgt_param = ia_multi_vgt_param;
434 sctx->last_ls_hs_config = ls_hs_config;
435 }
436
437 if (gs_out_prim != sctx->last_gs_out_prim) {
438 radeon_set_context_reg(cs, R_028A6C_VGT_GS_OUT_PRIM_TYPE, gs_out_prim);
439 sctx->last_gs_out_prim = gs_out_prim;
440 }
441
442 /* Primitive restart. */
443 if (info->primitive_restart != sctx->last_primitive_restart_en) {
444 radeon_set_context_reg(cs, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, info->primitive_restart);
445 sctx->last_primitive_restart_en = info->primitive_restart;
446
447 if (info->primitive_restart &&
448 (info->restart_index != sctx->last_restart_index ||
449 sctx->last_restart_index == SI_RESTART_INDEX_UNKNOWN)) {
450 radeon_set_context_reg(cs, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
451 info->restart_index);
452 sctx->last_restart_index = info->restart_index;
453 }
454 }
455 }
456
457 static void si_emit_draw_packets(struct si_context *sctx,
458 const struct pipe_draw_info *info,
459 const struct pipe_index_buffer *ib)
460 {
461 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
462 unsigned sh_base_reg = sctx->shader_userdata.sh_base[PIPE_SHADER_VERTEX];
463 bool render_cond_bit = sctx->b.render_cond && !sctx->b.render_cond_force_off;
464
465 if (info->count_from_stream_output) {
466 struct r600_so_target *t =
467 (struct r600_so_target*)info->count_from_stream_output;
468 uint64_t va = t->buf_filled_size->gpu_address +
469 t->buf_filled_size_offset;
470
471 radeon_set_context_reg(cs, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE,
472 t->stride_in_dw);
473
474 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
475 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
476 COPY_DATA_DST_SEL(COPY_DATA_REG) |
477 COPY_DATA_WR_CONFIRM);
478 radeon_emit(cs, va); /* src address lo */
479 radeon_emit(cs, va >> 32); /* src address hi */
480 radeon_emit(cs, R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE >> 2);
481 radeon_emit(cs, 0); /* unused */
482
483 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
484 t->buf_filled_size, RADEON_USAGE_READ,
485 RADEON_PRIO_SO_FILLED_SIZE);
486 }
487
488 /* draw packet */
489 if (info->indexed) {
490 radeon_emit(cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
491
492 /* index type */
493 switch (ib->index_size) {
494 case 1:
495 radeon_emit(cs, V_028A7C_VGT_INDEX_8);
496 break;
497 case 2:
498 radeon_emit(cs, V_028A7C_VGT_INDEX_16 |
499 (SI_BIG_ENDIAN && sctx->b.chip_class <= CIK ?
500 V_028A7C_VGT_DMA_SWAP_16_BIT : 0));
501 break;
502 case 4:
503 radeon_emit(cs, V_028A7C_VGT_INDEX_32 |
504 (SI_BIG_ENDIAN && sctx->b.chip_class <= CIK ?
505 V_028A7C_VGT_DMA_SWAP_32_BIT : 0));
506 break;
507 default:
508 assert(!"unreachable");
509 return;
510 }
511 }
512
513 if (!info->indirect) {
514 int base_vertex;
515
516 radeon_emit(cs, PKT3(PKT3_NUM_INSTANCES, 0, 0));
517 radeon_emit(cs, info->instance_count);
518
519 /* Base vertex and start instance. */
520 base_vertex = info->indexed ? info->index_bias : info->start;
521
522 if (base_vertex != sctx->last_base_vertex ||
523 sctx->last_base_vertex == SI_BASE_VERTEX_UNKNOWN ||
524 info->start_instance != sctx->last_start_instance ||
525 sh_base_reg != sctx->last_sh_base_reg) {
526 radeon_set_sh_reg_seq(cs, sh_base_reg + SI_SGPR_BASE_VERTEX * 4, 2);
527 radeon_emit(cs, base_vertex);
528 radeon_emit(cs, info->start_instance);
529
530 sctx->last_base_vertex = base_vertex;
531 sctx->last_start_instance = info->start_instance;
532 sctx->last_sh_base_reg = sh_base_reg;
533 }
534 } else {
535 si_invalidate_draw_sh_constants(sctx);
536
537 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
538 (struct r600_resource *)info->indirect,
539 RADEON_USAGE_READ, RADEON_PRIO_DRAW_INDIRECT);
540 }
541
542 if (info->indexed) {
543 uint32_t index_max_size = (ib->buffer->width0 - ib->offset) /
544 ib->index_size;
545 uint64_t index_va = r600_resource(ib->buffer)->gpu_address + ib->offset;
546
547 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
548 (struct r600_resource *)ib->buffer,
549 RADEON_USAGE_READ, RADEON_PRIO_INDEX_BUFFER);
550
551 if (info->indirect) {
552 uint64_t indirect_va = r600_resource(info->indirect)->gpu_address;
553
554 assert(indirect_va % 8 == 0);
555 assert(index_va % 2 == 0);
556 assert(info->indirect_offset % 4 == 0);
557
558 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
559 radeon_emit(cs, 1);
560 radeon_emit(cs, indirect_va);
561 radeon_emit(cs, indirect_va >> 32);
562
563 radeon_emit(cs, PKT3(PKT3_INDEX_BASE, 1, 0));
564 radeon_emit(cs, index_va);
565 radeon_emit(cs, index_va >> 32);
566
567 radeon_emit(cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
568 radeon_emit(cs, index_max_size);
569
570 radeon_emit(cs, PKT3(PKT3_DRAW_INDEX_INDIRECT, 3, render_cond_bit));
571 radeon_emit(cs, info->indirect_offset);
572 radeon_emit(cs, (sh_base_reg + SI_SGPR_BASE_VERTEX * 4 - SI_SH_REG_OFFSET) >> 2);
573 radeon_emit(cs, (sh_base_reg + SI_SGPR_START_INSTANCE * 4 - SI_SH_REG_OFFSET) >> 2);
574 radeon_emit(cs, V_0287F0_DI_SRC_SEL_DMA);
575 } else {
576 index_va += info->start * ib->index_size;
577
578 radeon_emit(cs, PKT3(PKT3_DRAW_INDEX_2, 4, render_cond_bit));
579 radeon_emit(cs, index_max_size);
580 radeon_emit(cs, index_va);
581 radeon_emit(cs, (index_va >> 32UL) & 0xFF);
582 radeon_emit(cs, info->count);
583 radeon_emit(cs, V_0287F0_DI_SRC_SEL_DMA);
584 }
585 } else {
586 if (info->indirect) {
587 uint64_t indirect_va = r600_resource(info->indirect)->gpu_address;
588
589 assert(indirect_va % 8 == 0);
590 assert(info->indirect_offset % 4 == 0);
591
592 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
593 radeon_emit(cs, 1);
594 radeon_emit(cs, indirect_va);
595 radeon_emit(cs, indirect_va >> 32);
596
597 radeon_emit(cs, PKT3(PKT3_DRAW_INDIRECT, 3, render_cond_bit));
598 radeon_emit(cs, info->indirect_offset);
599 radeon_emit(cs, (sh_base_reg + SI_SGPR_BASE_VERTEX * 4 - SI_SH_REG_OFFSET) >> 2);
600 radeon_emit(cs, (sh_base_reg + SI_SGPR_START_INSTANCE * 4 - SI_SH_REG_OFFSET) >> 2);
601 radeon_emit(cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX);
602 } else {
603 radeon_emit(cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, render_cond_bit));
604 radeon_emit(cs, info->count);
605 radeon_emit(cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
606 S_0287F0_USE_OPAQUE(!!info->count_from_stream_output));
607 }
608 }
609 }
610
611 void si_emit_cache_flush(struct si_context *si_ctx, struct r600_atom *atom)
612 {
613 struct r600_common_context *sctx = &si_ctx->b;
614 struct radeon_winsys_cs *cs = sctx->gfx.cs;
615 uint32_t cp_coher_cntl = 0;
616
617 /* SI has a bug that it always flushes ICACHE and KCACHE if either
618 * bit is set. An alternative way is to write SQC_CACHES, but that
619 * doesn't seem to work reliably. Since the bug doesn't affect
620 * correctness (it only does more work than necessary) and
621 * the performance impact is likely negligible, there is no plan
622 * to add a workaround for it.
623 */
624
625 if (sctx->flags & SI_CONTEXT_INV_ICACHE)
626 cp_coher_cntl |= S_0085F0_SH_ICACHE_ACTION_ENA(1);
627 if (sctx->flags & SI_CONTEXT_INV_SMEM_L1)
628 cp_coher_cntl |= S_0085F0_SH_KCACHE_ACTION_ENA(1);
629
630 if (sctx->flags & SI_CONTEXT_INV_VMEM_L1)
631 cp_coher_cntl |= S_0085F0_TCL1_ACTION_ENA(1);
632 if (sctx->flags & SI_CONTEXT_INV_GLOBAL_L2) {
633 cp_coher_cntl |= S_0085F0_TC_ACTION_ENA(1);
634
635 if (sctx->chip_class >= VI)
636 cp_coher_cntl |= S_0301F0_TC_WB_ACTION_ENA(1);
637 }
638
639 if (sctx->flags & SI_CONTEXT_FLUSH_AND_INV_CB) {
640 cp_coher_cntl |= S_0085F0_CB_ACTION_ENA(1) |
641 S_0085F0_CB0_DEST_BASE_ENA(1) |
642 S_0085F0_CB1_DEST_BASE_ENA(1) |
643 S_0085F0_CB2_DEST_BASE_ENA(1) |
644 S_0085F0_CB3_DEST_BASE_ENA(1) |
645 S_0085F0_CB4_DEST_BASE_ENA(1) |
646 S_0085F0_CB5_DEST_BASE_ENA(1) |
647 S_0085F0_CB6_DEST_BASE_ENA(1) |
648 S_0085F0_CB7_DEST_BASE_ENA(1);
649
650 /* Necessary for DCC */
651 if (sctx->chip_class >= VI) {
652 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, 0));
653 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_DATA_TS) |
654 EVENT_INDEX(5));
655 radeon_emit(cs, 0);
656 radeon_emit(cs, 0);
657 radeon_emit(cs, 0);
658 radeon_emit(cs, 0);
659 }
660 }
661 if (sctx->flags & SI_CONTEXT_FLUSH_AND_INV_DB) {
662 cp_coher_cntl |= S_0085F0_DB_ACTION_ENA(1) |
663 S_0085F0_DB_DEST_BASE_ENA(1);
664 }
665
666 if (sctx->flags & SI_CONTEXT_FLUSH_AND_INV_CB_META) {
667 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
668 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_META) | EVENT_INDEX(0));
669 /* needed for wait for idle in SURFACE_SYNC */
670 assert(sctx->flags & SI_CONTEXT_FLUSH_AND_INV_CB);
671 }
672 if (sctx->flags & SI_CONTEXT_FLUSH_AND_INV_DB_META) {
673 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
674 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_DB_META) | EVENT_INDEX(0));
675 /* needed for wait for idle in SURFACE_SYNC */
676 assert(sctx->flags & SI_CONTEXT_FLUSH_AND_INV_DB);
677 }
678
679 /* Wait for shader engines to go idle.
680 * VS and PS waits are unnecessary if SURFACE_SYNC is going to wait
681 * for everything including CB/DB cache flushes.
682 */
683 if (!(sctx->flags & (SI_CONTEXT_FLUSH_AND_INV_CB |
684 SI_CONTEXT_FLUSH_AND_INV_DB))) {
685 if (sctx->flags & SI_CONTEXT_PS_PARTIAL_FLUSH) {
686 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
687 radeon_emit(cs, EVENT_TYPE(V_028A90_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
688 } else if (sctx->flags & SI_CONTEXT_VS_PARTIAL_FLUSH) {
689 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
690 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
691 }
692 }
693 if (sctx->flags & SI_CONTEXT_CS_PARTIAL_FLUSH) {
694 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
695 radeon_emit(cs, EVENT_TYPE(V_028A90_CS_PARTIAL_FLUSH | EVENT_INDEX(4)));
696 }
697
698 /* VGT state synchronization. */
699 if (sctx->flags & SI_CONTEXT_VGT_FLUSH) {
700 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
701 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
702 }
703 if (sctx->flags & SI_CONTEXT_VGT_STREAMOUT_SYNC) {
704 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
705 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_STREAMOUT_SYNC) | EVENT_INDEX(0));
706 }
707
708 /* Make sure ME is idle (it executes most packets) before continuing.
709 * This prevents read-after-write hazards between PFP and ME.
710 */
711 if (cp_coher_cntl || (sctx->flags & SI_CONTEXT_CS_PARTIAL_FLUSH)) {
712 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
713 radeon_emit(cs, 0);
714 }
715
716 /* When one of the DEST_BASE flags is set, SURFACE_SYNC waits for idle.
717 * Therefore, it should be last. Done in PFP.
718 */
719 if (cp_coher_cntl) {
720 /* ACQUIRE_MEM is only required on a compute ring. */
721 radeon_emit(cs, PKT3(PKT3_SURFACE_SYNC, 3, 0));
722 radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */
723 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
724 radeon_emit(cs, 0); /* CP_COHER_BASE */
725 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
726 }
727
728 if (sctx->flags & R600_CONTEXT_START_PIPELINE_STATS) {
729 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
730 radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_START) |
731 EVENT_INDEX(0));
732 } else if (sctx->flags & R600_CONTEXT_STOP_PIPELINE_STATS) {
733 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
734 radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_STOP) |
735 EVENT_INDEX(0));
736 }
737
738 sctx->flags = 0;
739 }
740
741 static void si_get_draw_start_count(struct si_context *sctx,
742 const struct pipe_draw_info *info,
743 unsigned *start, unsigned *count)
744 {
745 if (info->indirect) {
746 struct r600_resource *indirect =
747 (struct r600_resource*)info->indirect;
748 int *data = r600_buffer_map_sync_with_rings(&sctx->b,
749 indirect, PIPE_TRANSFER_READ);
750 data += info->indirect_offset/sizeof(int);
751 *start = data[2];
752 *count = data[0];
753 } else {
754 *start = info->start;
755 *count = info->count;
756 }
757 }
758
759 void si_ce_pre_draw_synchronization(struct si_context *sctx)
760 {
761 if (sctx->ce_need_synchronization) {
762 radeon_emit(sctx->ce_ib, PKT3(PKT3_INCREMENT_CE_COUNTER, 0, 0));
763 radeon_emit(sctx->ce_ib, 1);
764
765 radeon_emit(sctx->b.gfx.cs, PKT3(PKT3_WAIT_ON_CE_COUNTER, 0, 0));
766 radeon_emit(sctx->b.gfx.cs, 1);
767 }
768 }
769
770 void si_ce_post_draw_synchronization(struct si_context *sctx)
771 {
772 if (sctx->ce_need_synchronization) {
773 radeon_emit(sctx->b.gfx.cs, PKT3(PKT3_INCREMENT_DE_COUNTER, 0, 0));
774 radeon_emit(sctx->b.gfx.cs, 0);
775
776 sctx->ce_need_synchronization = false;
777 }
778 }
779
780 void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info)
781 {
782 struct si_context *sctx = (struct si_context *)ctx;
783 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
784 struct pipe_index_buffer ib = {};
785 unsigned mask, dirty_fb_counter;
786
787 if (!info->count && !info->indirect &&
788 (info->indexed || !info->count_from_stream_output))
789 return;
790
791 if (!sctx->vs_shader.cso) {
792 assert(0);
793 return;
794 }
795 if (!sctx->ps_shader.cso && (!rs || !rs->rasterizer_discard)) {
796 assert(0);
797 return;
798 }
799 if (!!sctx->tes_shader.cso != (info->mode == PIPE_PRIM_PATCHES)) {
800 assert(0);
801 return;
802 }
803
804 /* Re-emit the framebuffer state if needed. */
805 dirty_fb_counter = p_atomic_read(&sctx->b.screen->dirty_fb_counter);
806 if (dirty_fb_counter != sctx->b.last_dirty_fb_counter) {
807 sctx->b.last_dirty_fb_counter = dirty_fb_counter;
808 sctx->framebuffer.dirty_cbufs |=
809 ((1 << sctx->framebuffer.state.nr_cbufs) - 1);
810 sctx->framebuffer.dirty_zsbuf = true;
811 si_mark_atom_dirty(sctx, &sctx->framebuffer.atom);
812 }
813
814 si_decompress_graphics_textures(sctx);
815
816 /* Set the rasterization primitive type.
817 *
818 * This must be done after si_decompress_textures, which can call
819 * draw_vbo recursively, and before si_update_shaders, which uses
820 * current_rast_prim for this draw_vbo call. */
821 if (sctx->gs_shader.cso)
822 sctx->current_rast_prim = sctx->gs_shader.cso->gs_output_prim;
823 else if (sctx->tes_shader.cso)
824 sctx->current_rast_prim =
825 sctx->tes_shader.cso->info.properties[TGSI_PROPERTY_TES_PRIM_MODE];
826 else
827 sctx->current_rast_prim = info->mode;
828
829 if (!si_update_shaders(sctx) ||
830 !si_upload_graphics_shader_descriptors(sctx))
831 return;
832
833 if (info->indexed) {
834 /* Initialize the index buffer struct. */
835 pipe_resource_reference(&ib.buffer, sctx->index_buffer.buffer);
836 ib.user_buffer = sctx->index_buffer.user_buffer;
837 ib.index_size = sctx->index_buffer.index_size;
838 ib.offset = sctx->index_buffer.offset;
839
840 /* Translate or upload, if needed. */
841 /* 8-bit indices are supported on VI. */
842 if (sctx->b.chip_class <= CIK && ib.index_size == 1) {
843 struct pipe_resource *out_buffer = NULL;
844 unsigned out_offset, start, count, start_offset;
845 void *ptr;
846
847 si_get_draw_start_count(sctx, info, &start, &count);
848 start_offset = start * ib.index_size;
849
850 u_upload_alloc(sctx->b.uploader, start_offset, count * 2, 256,
851 &out_offset, &out_buffer, &ptr);
852 if (!out_buffer) {
853 pipe_resource_reference(&ib.buffer, NULL);
854 return;
855 }
856
857 util_shorten_ubyte_elts_to_userptr(&sctx->b.b, &ib, 0,
858 ib.offset + start_offset,
859 count, ptr);
860
861 pipe_resource_reference(&ib.buffer, NULL);
862 ib.user_buffer = NULL;
863 ib.buffer = out_buffer;
864 /* info->start will be added by the drawing code */
865 ib.offset = out_offset - start_offset;
866 ib.index_size = 2;
867 } else if (ib.user_buffer && !ib.buffer) {
868 unsigned start, count, start_offset;
869
870 si_get_draw_start_count(sctx, info, &start, &count);
871 start_offset = start * ib.index_size;
872
873 u_upload_data(sctx->b.uploader, start_offset, count * ib.index_size,
874 256, (char*)ib.user_buffer + start_offset,
875 &ib.offset, &ib.buffer);
876 if (!ib.buffer)
877 return;
878 /* info->start will be added by the drawing code */
879 ib.offset -= start_offset;
880 }
881 }
882
883 /* VI reads index buffers through TC L2. */
884 if (info->indexed && sctx->b.chip_class <= CIK &&
885 r600_resource(ib.buffer)->TC_L2_dirty) {
886 sctx->b.flags |= SI_CONTEXT_INV_GLOBAL_L2;
887 r600_resource(ib.buffer)->TC_L2_dirty = false;
888 }
889
890 /* Check flush flags. */
891 if (sctx->b.flags)
892 si_mark_atom_dirty(sctx, sctx->atoms.s.cache_flush);
893
894 si_need_cs_space(sctx);
895
896 /* Emit states. */
897 mask = sctx->dirty_atoms;
898 while (mask) {
899 struct r600_atom *atom = sctx->atoms.array[u_bit_scan(&mask)];
900
901 atom->emit(&sctx->b, atom);
902 }
903 sctx->dirty_atoms = 0;
904
905 si_pm4_emit_dirty(sctx);
906 si_emit_scratch_reloc(sctx);
907 si_emit_rasterizer_prim_state(sctx);
908 si_emit_draw_registers(sctx, info);
909
910 si_ce_pre_draw_synchronization(sctx);
911
912 si_emit_draw_packets(sctx, info, &ib);
913
914 si_ce_post_draw_synchronization(sctx);
915
916 if (sctx->trace_buf)
917 si_trace_emit(sctx);
918
919 /* Workaround for a VGT hang when streamout is enabled.
920 * It must be done after drawing. */
921 if ((sctx->b.family == CHIP_HAWAII ||
922 sctx->b.family == CHIP_TONGA ||
923 sctx->b.family == CHIP_FIJI) &&
924 r600_get_strmout_en(&sctx->b)) {
925 sctx->b.flags |= SI_CONTEXT_VGT_STREAMOUT_SYNC;
926 }
927
928 /* Set the depth buffer as dirty. */
929 if (sctx->framebuffer.state.zsbuf) {
930 struct pipe_surface *surf = sctx->framebuffer.state.zsbuf;
931 struct r600_texture *rtex = (struct r600_texture *)surf->texture;
932
933 rtex->dirty_level_mask |= 1 << surf->u.tex.level;
934
935 if (rtex->surface.flags & RADEON_SURF_SBUFFER)
936 rtex->stencil_dirty_level_mask |= 1 << surf->u.tex.level;
937 }
938 if (sctx->framebuffer.compressed_cb_mask) {
939 struct pipe_surface *surf;
940 struct r600_texture *rtex;
941 unsigned mask = sctx->framebuffer.compressed_cb_mask;
942
943 do {
944 unsigned i = u_bit_scan(&mask);
945 surf = sctx->framebuffer.state.cbufs[i];
946 rtex = (struct r600_texture*)surf->texture;
947
948 rtex->dirty_level_mask |= 1 << surf->u.tex.level;
949 } while (mask);
950 }
951
952 pipe_resource_reference(&ib.buffer, NULL);
953 sctx->b.num_draw_calls++;
954 }
955
956 void si_trace_emit(struct si_context *sctx)
957 {
958 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
959
960 sctx->trace_id++;
961 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, sctx->trace_buf,
962 RADEON_USAGE_READWRITE, RADEON_PRIO_TRACE);
963 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
964 radeon_emit(cs, S_370_DST_SEL(V_370_MEMORY_SYNC) |
965 S_370_WR_CONFIRM(1) |
966 S_370_ENGINE_SEL(V_370_ME));
967 radeon_emit(cs, sctx->trace_buf->gpu_address);
968 radeon_emit(cs, sctx->trace_buf->gpu_address >> 32);
969 radeon_emit(cs, sctx->trace_id);
970 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
971 radeon_emit(cs, SI_ENCODE_TRACE_POINT(sctx->trace_id));
972 }