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radeonsi: don't crash when cleaning up after an incomplete context
[mesa.git] / src / gallium / drivers / radeonsi / si_state_draw.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Christian König <christian.koenig@amd.com>
25 */
26
27 #include "si_pipe.h"
28 #include "si_shader.h"
29 #include "radeon/r600_cs.h"
30 #include "sid.h"
31
32 #include "util/u_index_modify.h"
33 #include "util/u_upload_mgr.h"
34 #include "util/u_prim.h"
35
36 static void si_decompress_textures(struct si_context *sctx)
37 {
38 if (!sctx->blitter->running) {
39 /* Flush depth textures which need to be flushed. */
40 for (int i = 0; i < SI_NUM_SHADERS; i++) {
41 if (sctx->samplers[i].depth_texture_mask) {
42 si_flush_depth_textures(sctx, &sctx->samplers[i]);
43 }
44 if (sctx->samplers[i].compressed_colortex_mask) {
45 si_decompress_color_textures(sctx, &sctx->samplers[i]);
46 }
47 }
48 }
49 }
50
51 static unsigned si_conv_pipe_prim(unsigned mode)
52 {
53 static const unsigned prim_conv[] = {
54 [PIPE_PRIM_POINTS] = V_008958_DI_PT_POINTLIST,
55 [PIPE_PRIM_LINES] = V_008958_DI_PT_LINELIST,
56 [PIPE_PRIM_LINE_LOOP] = V_008958_DI_PT_LINELOOP,
57 [PIPE_PRIM_LINE_STRIP] = V_008958_DI_PT_LINESTRIP,
58 [PIPE_PRIM_TRIANGLES] = V_008958_DI_PT_TRILIST,
59 [PIPE_PRIM_TRIANGLE_STRIP] = V_008958_DI_PT_TRISTRIP,
60 [PIPE_PRIM_TRIANGLE_FAN] = V_008958_DI_PT_TRIFAN,
61 [PIPE_PRIM_QUADS] = V_008958_DI_PT_QUADLIST,
62 [PIPE_PRIM_QUAD_STRIP] = V_008958_DI_PT_QUADSTRIP,
63 [PIPE_PRIM_POLYGON] = V_008958_DI_PT_POLYGON,
64 [PIPE_PRIM_LINES_ADJACENCY] = V_008958_DI_PT_LINELIST_ADJ,
65 [PIPE_PRIM_LINE_STRIP_ADJACENCY] = V_008958_DI_PT_LINESTRIP_ADJ,
66 [PIPE_PRIM_TRIANGLES_ADJACENCY] = V_008958_DI_PT_TRILIST_ADJ,
67 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY] = V_008958_DI_PT_TRISTRIP_ADJ,
68 [PIPE_PRIM_PATCHES] = V_008958_DI_PT_PATCH,
69 [R600_PRIM_RECTANGLE_LIST] = V_008958_DI_PT_RECTLIST
70 };
71 assert(mode < Elements(prim_conv));
72 return prim_conv[mode];
73 }
74
75 static unsigned si_conv_prim_to_gs_out(unsigned mode)
76 {
77 static const int prim_conv[] = {
78 [PIPE_PRIM_POINTS] = V_028A6C_OUTPRIM_TYPE_POINTLIST,
79 [PIPE_PRIM_LINES] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
80 [PIPE_PRIM_LINE_LOOP] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
81 [PIPE_PRIM_LINE_STRIP] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
82 [PIPE_PRIM_TRIANGLES] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
83 [PIPE_PRIM_TRIANGLE_STRIP] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
84 [PIPE_PRIM_TRIANGLE_FAN] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
85 [PIPE_PRIM_QUADS] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
86 [PIPE_PRIM_QUAD_STRIP] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
87 [PIPE_PRIM_POLYGON] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
88 [PIPE_PRIM_LINES_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
89 [PIPE_PRIM_LINE_STRIP_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
90 [PIPE_PRIM_TRIANGLES_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
91 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
92 [PIPE_PRIM_PATCHES] = V_028A6C_OUTPRIM_TYPE_POINTLIST,
93 [R600_PRIM_RECTANGLE_LIST] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
94 };
95 assert(mode < Elements(prim_conv));
96
97 return prim_conv[mode];
98 }
99
100 /**
101 * This calculates the LDS size for tessellation shaders (VS, TCS, TES).
102 * LS.LDS_SIZE is shared by all 3 shader stages.
103 *
104 * The information about LDS and other non-compile-time parameters is then
105 * written to userdata SGPRs.
106 */
107 static void si_emit_derived_tess_state(struct si_context *sctx,
108 const struct pipe_draw_info *info,
109 unsigned *num_patches)
110 {
111 struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs;
112 struct si_shader_selector *ls = sctx->vs_shader;
113 /* The TES pointer will only be used for sctx->last_tcs.
114 * It would be wrong to think that TCS = TES. */
115 struct si_shader_selector *tcs =
116 sctx->tcs_shader ? sctx->tcs_shader : sctx->tes_shader;
117 unsigned tes_sh_base = sctx->shader_userdata.sh_base[PIPE_SHADER_TESS_EVAL];
118 unsigned num_tcs_input_cp = info->vertices_per_patch;
119 unsigned num_tcs_output_cp, num_tcs_inputs, num_tcs_outputs;
120 unsigned num_tcs_patch_outputs;
121 unsigned input_vertex_size, output_vertex_size, pervertex_output_patch_size;
122 unsigned input_patch_size, output_patch_size, output_patch0_offset;
123 unsigned perpatch_output_offset, lds_size, ls_rsrc2;
124 unsigned tcs_in_layout, tcs_out_layout, tcs_out_offsets;
125
126 *num_patches = 1; /* TODO: calculate this */
127
128 if (sctx->last_ls == ls->current &&
129 sctx->last_tcs == tcs &&
130 sctx->last_tes_sh_base == tes_sh_base &&
131 sctx->last_num_tcs_input_cp == num_tcs_input_cp)
132 return;
133
134 sctx->last_ls = ls->current;
135 sctx->last_tcs = tcs;
136 sctx->last_tes_sh_base = tes_sh_base;
137 sctx->last_num_tcs_input_cp = num_tcs_input_cp;
138
139 /* This calculates how shader inputs and outputs among VS, TCS, and TES
140 * are laid out in LDS. */
141 num_tcs_inputs = util_last_bit64(ls->outputs_written);
142
143 if (sctx->tcs_shader) {
144 num_tcs_outputs = util_last_bit64(tcs->outputs_written);
145 num_tcs_output_cp = tcs->info.properties[TGSI_PROPERTY_TCS_VERTICES_OUT];
146 num_tcs_patch_outputs = util_last_bit64(tcs->patch_outputs_written);
147 } else {
148 /* No TCS. Route varyings from LS to TES. */
149 num_tcs_outputs = num_tcs_inputs;
150 num_tcs_output_cp = num_tcs_input_cp;
151 num_tcs_patch_outputs = 2; /* TESSINNER + TESSOUTER */
152 }
153
154 input_vertex_size = num_tcs_inputs * 16;
155 output_vertex_size = num_tcs_outputs * 16;
156
157 input_patch_size = num_tcs_input_cp * input_vertex_size;
158
159 pervertex_output_patch_size = num_tcs_output_cp * output_vertex_size;
160 output_patch_size = pervertex_output_patch_size + num_tcs_patch_outputs * 16;
161
162 output_patch0_offset = sctx->tcs_shader ? input_patch_size * *num_patches : 0;
163 perpatch_output_offset = output_patch0_offset + pervertex_output_patch_size;
164
165 lds_size = output_patch0_offset + output_patch_size * *num_patches;
166 ls_rsrc2 = ls->current->ls_rsrc2;
167
168 if (sctx->b.chip_class >= CIK) {
169 assert(lds_size <= 65536);
170 ls_rsrc2 |= S_00B52C_LDS_SIZE(align(lds_size, 512) / 512);
171 } else {
172 assert(lds_size <= 32768);
173 ls_rsrc2 |= S_00B52C_LDS_SIZE(align(lds_size, 256) / 256);
174 }
175
176 /* Due to a hw bug, RSRC2_LS must be written twice with another
177 * LS register written in between. */
178 if (sctx->b.chip_class == CIK && sctx->b.family != CHIP_HAWAII)
179 si_write_sh_reg(cs, R_00B52C_SPI_SHADER_PGM_RSRC2_LS, ls_rsrc2);
180 si_write_sh_reg_seq(cs, R_00B528_SPI_SHADER_PGM_RSRC1_LS, 2);
181 radeon_emit(cs, ls->current->ls_rsrc1);
182 radeon_emit(cs, ls_rsrc2);
183
184 /* Compute userdata SGPRs. */
185 assert(((input_vertex_size / 4) & ~0xff) == 0);
186 assert(((output_vertex_size / 4) & ~0xff) == 0);
187 assert(((input_patch_size / 4) & ~0x1fff) == 0);
188 assert(((output_patch_size / 4) & ~0x1fff) == 0);
189 assert(((output_patch0_offset / 16) & ~0xffff) == 0);
190 assert(((perpatch_output_offset / 16) & ~0xffff) == 0);
191 assert(num_tcs_input_cp <= 32);
192 assert(num_tcs_output_cp <= 32);
193
194 tcs_in_layout = (input_patch_size / 4) |
195 ((input_vertex_size / 4) << 13);
196 tcs_out_layout = (output_patch_size / 4) |
197 ((output_vertex_size / 4) << 13);
198 tcs_out_offsets = (output_patch0_offset / 16) |
199 ((perpatch_output_offset / 16) << 16);
200
201 /* Set them for LS. */
202 si_write_sh_reg(cs,
203 R_00B530_SPI_SHADER_USER_DATA_LS_0 + SI_SGPR_LS_OUT_LAYOUT * 4,
204 tcs_in_layout);
205
206 /* Set them for TCS. */
207 si_write_sh_reg_seq(cs,
208 R_00B430_SPI_SHADER_USER_DATA_HS_0 + SI_SGPR_TCS_OUT_OFFSETS * 4, 3);
209 radeon_emit(cs, tcs_out_offsets);
210 radeon_emit(cs, tcs_out_layout | (num_tcs_input_cp << 26));
211 radeon_emit(cs, tcs_in_layout);
212
213 /* Set them for TES. */
214 si_write_sh_reg_seq(cs, tes_sh_base + SI_SGPR_TCS_OUT_OFFSETS * 4, 2);
215 radeon_emit(cs, tcs_out_offsets);
216 radeon_emit(cs, tcs_out_layout | (num_tcs_output_cp << 26));
217 }
218
219 static unsigned si_get_ia_multi_vgt_param(struct si_context *sctx,
220 const struct pipe_draw_info *info,
221 unsigned num_patches)
222 {
223 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
224 unsigned prim = info->mode;
225 unsigned primgroup_size = 128; /* recommended without a GS */
226
227 /* SWITCH_ON_EOP(0) is always preferable. */
228 bool wd_switch_on_eop = false;
229 bool ia_switch_on_eop = false;
230 bool ia_switch_on_eoi = false;
231 bool partial_vs_wave = false;
232 bool partial_es_wave = false;
233
234 if (sctx->gs_shader)
235 primgroup_size = 64; /* recommended with a GS */
236
237 if (sctx->tes_shader) {
238 unsigned num_cp_out =
239 sctx->tcs_shader ?
240 sctx->tcs_shader->info.properties[TGSI_PROPERTY_TCS_VERTICES_OUT] :
241 info->vertices_per_patch;
242 unsigned max_size = 256 / MAX2(info->vertices_per_patch, num_cp_out);
243
244 primgroup_size = MIN2(primgroup_size, max_size);
245
246 /* primgroup_size must be set to a multiple of NUM_PATCHES */
247 primgroup_size = (primgroup_size / num_patches) * num_patches;
248
249 /* SWITCH_ON_EOI must be set if PrimID is used.
250 * If SWITCH_ON_EOI is set, PARTIAL_ES_WAVE must be set too. */
251 if ((sctx->tcs_shader && sctx->tcs_shader->info.uses_primid) ||
252 sctx->tes_shader->info.uses_primid) {
253 ia_switch_on_eoi = true;
254 partial_es_wave = true;
255 }
256
257 /* Bug with tessellation and GS on Bonaire and older 2 SE chips. */
258 if ((sctx->b.family == CHIP_TAHITI ||
259 sctx->b.family == CHIP_PITCAIRN ||
260 sctx->b.family == CHIP_BONAIRE) &&
261 sctx->gs_shader)
262 partial_vs_wave = true;
263 }
264
265 /* This is a hardware requirement. */
266 if ((rs && rs->line_stipple_enable) ||
267 (sctx->b.screen->debug_flags & DBG_SWITCH_ON_EOP)) {
268 ia_switch_on_eop = true;
269 wd_switch_on_eop = true;
270 }
271
272 if (sctx->b.streamout.streamout_enabled ||
273 sctx->b.streamout.prims_gen_query_enabled)
274 partial_vs_wave = true;
275
276 if (sctx->b.chip_class >= CIK) {
277 /* WD_SWITCH_ON_EOP has no effect on GPUs with less than
278 * 4 shader engines. Set 1 to pass the assertion below.
279 * The other cases are hardware requirements. */
280 if (sctx->b.screen->info.max_se < 4 ||
281 prim == PIPE_PRIM_POLYGON ||
282 prim == PIPE_PRIM_LINE_LOOP ||
283 prim == PIPE_PRIM_TRIANGLE_FAN ||
284 prim == PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY ||
285 info->primitive_restart)
286 wd_switch_on_eop = true;
287
288 /* Hawaii hangs if instancing is enabled and WD_SWITCH_ON_EOP is 0.
289 * We don't know that for indirect drawing, so treat it as
290 * always problematic. */
291 if (sctx->b.family == CHIP_HAWAII &&
292 (info->indirect || info->instance_count > 1))
293 wd_switch_on_eop = true;
294
295 /* USE_OPAQUE doesn't work when WD_SWITCH_ON_EOP is 0. */
296 if (info->count_from_stream_output)
297 wd_switch_on_eop = true;
298
299 /* If the WD switch is false, the IA switch must be false too. */
300 assert(wd_switch_on_eop || !ia_switch_on_eop);
301 }
302
303 /* Hw bug with single-primitive instances and SWITCH_ON_EOI
304 * on multi-SE chips. */
305 if (sctx->b.screen->info.max_se >= 2 && ia_switch_on_eoi &&
306 (info->indirect ||
307 (info->instance_count > 1 &&
308 u_prims_for_vertices(info->mode, info->count) <= 1)))
309 sctx->b.flags |= SI_CONTEXT_VGT_FLUSH;
310
311 /* Instancing bug on 2 SE chips. */
312 if (sctx->b.screen->info.max_se == 2 && ia_switch_on_eoi &&
313 (info->indirect || info->instance_count > 1))
314 partial_vs_wave = true;
315
316 return S_028AA8_SWITCH_ON_EOP(ia_switch_on_eop) |
317 S_028AA8_SWITCH_ON_EOI(ia_switch_on_eoi) |
318 S_028AA8_PARTIAL_VS_WAVE_ON(partial_vs_wave) |
319 S_028AA8_PARTIAL_ES_WAVE_ON(partial_es_wave) |
320 S_028AA8_PRIMGROUP_SIZE(primgroup_size - 1) |
321 S_028AA8_WD_SWITCH_ON_EOP(sctx->b.chip_class >= CIK ? wd_switch_on_eop : 0);
322 }
323
324 static unsigned si_get_ls_hs_config(struct si_context *sctx,
325 const struct pipe_draw_info *info,
326 unsigned num_patches)
327 {
328 unsigned num_output_cp;
329
330 if (!sctx->tes_shader)
331 return 0;
332
333 num_output_cp = sctx->tcs_shader ?
334 sctx->tcs_shader->info.properties[TGSI_PROPERTY_TCS_VERTICES_OUT] :
335 info->vertices_per_patch;
336
337 return S_028B58_NUM_PATCHES(num_patches) |
338 S_028B58_HS_NUM_INPUT_CP(info->vertices_per_patch) |
339 S_028B58_HS_NUM_OUTPUT_CP(num_output_cp);
340 }
341
342 static void si_emit_scratch_reloc(struct si_context *sctx)
343 {
344 struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs;
345
346 if (!sctx->emit_scratch_reloc)
347 return;
348
349 r600_write_context_reg(cs, R_0286E8_SPI_TMPRING_SIZE,
350 sctx->spi_tmpring_size);
351
352 if (sctx->scratch_buffer) {
353 r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx,
354 sctx->scratch_buffer, RADEON_USAGE_READWRITE,
355 RADEON_PRIO_SHADER_RESOURCE_RW);
356
357 }
358 sctx->emit_scratch_reloc = false;
359 }
360
361 /* rast_prim is the primitive type after GS. */
362 static void si_emit_rasterizer_prim_state(struct si_context *sctx)
363 {
364 struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs;
365 unsigned rast_prim = sctx->current_rast_prim;
366 struct si_state_rasterizer *rs = sctx->emitted.named.rasterizer;
367
368 /* Skip this if not rendering lines. */
369 if (rast_prim != PIPE_PRIM_LINES &&
370 rast_prim != PIPE_PRIM_LINE_LOOP &&
371 rast_prim != PIPE_PRIM_LINE_STRIP &&
372 rast_prim != PIPE_PRIM_LINES_ADJACENCY &&
373 rast_prim != PIPE_PRIM_LINE_STRIP_ADJACENCY)
374 return;
375
376 if (rast_prim == sctx->last_rast_prim &&
377 rs->pa_sc_line_stipple == sctx->last_sc_line_stipple)
378 return;
379
380 r600_write_context_reg(cs, R_028A0C_PA_SC_LINE_STIPPLE,
381 rs->pa_sc_line_stipple |
382 S_028A0C_AUTO_RESET_CNTL(rast_prim == PIPE_PRIM_LINES ? 1 :
383 rast_prim == PIPE_PRIM_LINE_STRIP ? 2 : 0));
384
385 sctx->last_rast_prim = rast_prim;
386 sctx->last_sc_line_stipple = rs->pa_sc_line_stipple;
387 }
388
389 static void si_emit_draw_registers(struct si_context *sctx,
390 const struct pipe_draw_info *info)
391 {
392 struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs;
393 unsigned prim = si_conv_pipe_prim(info->mode);
394 unsigned gs_out_prim = si_conv_prim_to_gs_out(sctx->current_rast_prim);
395 unsigned ia_multi_vgt_param, ls_hs_config, num_patches = 0;
396
397 if (sctx->tes_shader)
398 si_emit_derived_tess_state(sctx, info, &num_patches);
399
400 ia_multi_vgt_param = si_get_ia_multi_vgt_param(sctx, info, num_patches);
401 ls_hs_config = si_get_ls_hs_config(sctx, info, num_patches);
402
403 /* Draw state. */
404 if (prim != sctx->last_prim ||
405 ia_multi_vgt_param != sctx->last_multi_vgt_param ||
406 ls_hs_config != sctx->last_ls_hs_config) {
407 if (sctx->b.chip_class >= CIK) {
408 radeon_emit(cs, PKT3(PKT3_DRAW_PREAMBLE, 2, 0));
409 radeon_emit(cs, prim); /* VGT_PRIMITIVE_TYPE */
410 radeon_emit(cs, ia_multi_vgt_param); /* IA_MULTI_VGT_PARAM */
411 radeon_emit(cs, ls_hs_config); /* VGT_LS_HS_CONFIG */
412 } else {
413 r600_write_config_reg(cs, R_008958_VGT_PRIMITIVE_TYPE, prim);
414 r600_write_context_reg(cs, R_028AA8_IA_MULTI_VGT_PARAM, ia_multi_vgt_param);
415 r600_write_context_reg(cs, R_028B58_VGT_LS_HS_CONFIG, ls_hs_config);
416 }
417 sctx->last_prim = prim;
418 sctx->last_multi_vgt_param = ia_multi_vgt_param;
419 sctx->last_ls_hs_config = ls_hs_config;
420 }
421
422 if (gs_out_prim != sctx->last_gs_out_prim) {
423 r600_write_context_reg(cs, R_028A6C_VGT_GS_OUT_PRIM_TYPE, gs_out_prim);
424 sctx->last_gs_out_prim = gs_out_prim;
425 }
426
427 /* Primitive restart. */
428 if (info->primitive_restart != sctx->last_primitive_restart_en) {
429 r600_write_context_reg(cs, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, info->primitive_restart);
430 sctx->last_primitive_restart_en = info->primitive_restart;
431
432 if (info->primitive_restart &&
433 (info->restart_index != sctx->last_restart_index ||
434 sctx->last_restart_index == SI_RESTART_INDEX_UNKNOWN)) {
435 r600_write_context_reg(cs, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
436 info->restart_index);
437 sctx->last_restart_index = info->restart_index;
438 }
439 }
440 }
441
442 static void si_emit_draw_packets(struct si_context *sctx,
443 const struct pipe_draw_info *info,
444 const struct pipe_index_buffer *ib)
445 {
446 struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs;
447 unsigned sh_base_reg = sctx->shader_userdata.sh_base[PIPE_SHADER_VERTEX];
448
449 if (info->count_from_stream_output) {
450 struct r600_so_target *t =
451 (struct r600_so_target*)info->count_from_stream_output;
452 uint64_t va = t->buf_filled_size->gpu_address +
453 t->buf_filled_size_offset;
454
455 r600_write_context_reg(cs, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE,
456 t->stride_in_dw);
457
458 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
459 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
460 COPY_DATA_DST_SEL(COPY_DATA_REG) |
461 COPY_DATA_WR_CONFIRM);
462 radeon_emit(cs, va); /* src address lo */
463 radeon_emit(cs, va >> 32); /* src address hi */
464 radeon_emit(cs, R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE >> 2);
465 radeon_emit(cs, 0); /* unused */
466
467 r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx,
468 t->buf_filled_size, RADEON_USAGE_READ,
469 RADEON_PRIO_MIN);
470 }
471
472 /* draw packet */
473 if (info->indexed) {
474 radeon_emit(cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
475
476 if (ib->index_size == 4) {
477 radeon_emit(cs, V_028A7C_VGT_INDEX_32 | (SI_BIG_ENDIAN ?
478 V_028A7C_VGT_DMA_SWAP_32_BIT : 0));
479 } else {
480 radeon_emit(cs, V_028A7C_VGT_INDEX_16 | (SI_BIG_ENDIAN ?
481 V_028A7C_VGT_DMA_SWAP_16_BIT : 0));
482 }
483 }
484
485 if (!info->indirect) {
486 int base_vertex;
487
488 radeon_emit(cs, PKT3(PKT3_NUM_INSTANCES, 0, 0));
489 radeon_emit(cs, info->instance_count);
490
491 /* Base vertex and start instance. */
492 base_vertex = info->indexed ? info->index_bias : info->start;
493
494 if (base_vertex != sctx->last_base_vertex ||
495 sctx->last_base_vertex == SI_BASE_VERTEX_UNKNOWN ||
496 info->start_instance != sctx->last_start_instance ||
497 sh_base_reg != sctx->last_sh_base_reg) {
498 si_write_sh_reg_seq(cs, sh_base_reg + SI_SGPR_BASE_VERTEX * 4, 2);
499 radeon_emit(cs, base_vertex);
500 radeon_emit(cs, info->start_instance);
501
502 sctx->last_base_vertex = base_vertex;
503 sctx->last_start_instance = info->start_instance;
504 sctx->last_sh_base_reg = sh_base_reg;
505 }
506 } else {
507 si_invalidate_draw_sh_constants(sctx);
508
509 r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx,
510 (struct r600_resource *)info->indirect,
511 RADEON_USAGE_READ, RADEON_PRIO_MIN);
512 }
513
514 if (info->indexed) {
515 uint32_t index_max_size = (ib->buffer->width0 - ib->offset) /
516 ib->index_size;
517 uint64_t index_va = r600_resource(ib->buffer)->gpu_address + ib->offset;
518
519 r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx,
520 (struct r600_resource *)ib->buffer,
521 RADEON_USAGE_READ, RADEON_PRIO_MIN);
522
523 if (info->indirect) {
524 uint64_t indirect_va = r600_resource(info->indirect)->gpu_address;
525
526 assert(indirect_va % 8 == 0);
527 assert(index_va % 2 == 0);
528 assert(info->indirect_offset % 4 == 0);
529
530 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
531 radeon_emit(cs, 1);
532 radeon_emit(cs, indirect_va);
533 radeon_emit(cs, indirect_va >> 32);
534
535 radeon_emit(cs, PKT3(PKT3_INDEX_BASE, 1, 0));
536 radeon_emit(cs, index_va);
537 radeon_emit(cs, index_va >> 32);
538
539 radeon_emit(cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
540 radeon_emit(cs, index_max_size);
541
542 radeon_emit(cs, PKT3(PKT3_DRAW_INDEX_INDIRECT, 3, sctx->b.predicate_drawing));
543 radeon_emit(cs, info->indirect_offset);
544 radeon_emit(cs, (sh_base_reg + SI_SGPR_BASE_VERTEX * 4 - SI_SH_REG_OFFSET) >> 2);
545 radeon_emit(cs, (sh_base_reg + SI_SGPR_START_INSTANCE * 4 - SI_SH_REG_OFFSET) >> 2);
546 radeon_emit(cs, V_0287F0_DI_SRC_SEL_DMA);
547 } else {
548 index_va += info->start * ib->index_size;
549
550 radeon_emit(cs, PKT3(PKT3_DRAW_INDEX_2, 4, sctx->b.predicate_drawing));
551 radeon_emit(cs, index_max_size);
552 radeon_emit(cs, index_va);
553 radeon_emit(cs, (index_va >> 32UL) & 0xFF);
554 radeon_emit(cs, info->count);
555 radeon_emit(cs, V_0287F0_DI_SRC_SEL_DMA);
556 }
557 } else {
558 if (info->indirect) {
559 uint64_t indirect_va = r600_resource(info->indirect)->gpu_address;
560
561 assert(indirect_va % 8 == 0);
562 assert(info->indirect_offset % 4 == 0);
563
564 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
565 radeon_emit(cs, 1);
566 radeon_emit(cs, indirect_va);
567 radeon_emit(cs, indirect_va >> 32);
568
569 radeon_emit(cs, PKT3(PKT3_DRAW_INDIRECT, 3, sctx->b.predicate_drawing));
570 radeon_emit(cs, info->indirect_offset);
571 radeon_emit(cs, (sh_base_reg + SI_SGPR_BASE_VERTEX * 4 - SI_SH_REG_OFFSET) >> 2);
572 radeon_emit(cs, (sh_base_reg + SI_SGPR_START_INSTANCE * 4 - SI_SH_REG_OFFSET) >> 2);
573 radeon_emit(cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX);
574 } else {
575 radeon_emit(cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, sctx->b.predicate_drawing));
576 radeon_emit(cs, info->count);
577 radeon_emit(cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
578 S_0287F0_USE_OPAQUE(!!info->count_from_stream_output));
579 }
580 }
581 }
582
583 #define BOTH_ICACHE_KCACHE (SI_CONTEXT_INV_ICACHE | SI_CONTEXT_INV_KCACHE)
584
585 void si_emit_cache_flush(struct r600_common_context *sctx, struct r600_atom *atom)
586 {
587 struct radeon_winsys_cs *cs = sctx->rings.gfx.cs;
588 uint32_t cp_coher_cntl = 0;
589 uint32_t compute =
590 PKT3_SHADER_TYPE_S(!!(sctx->flags & SI_CONTEXT_FLAG_COMPUTE));
591
592 /* SI has a bug that it always flushes ICACHE and KCACHE if either
593 * bit is set. An alternative way is to write SQC_CACHES, but that
594 * doesn't seem to work reliably. Since the bug doesn't affect
595 * correctness (it only does more work than necessary) and
596 * the performance impact is likely negligible, there is no plan
597 * to fix it.
598 */
599
600 if (sctx->flags & SI_CONTEXT_INV_ICACHE)
601 cp_coher_cntl |= S_0085F0_SH_ICACHE_ACTION_ENA(1);
602 if (sctx->flags & SI_CONTEXT_INV_KCACHE)
603 cp_coher_cntl |= S_0085F0_SH_KCACHE_ACTION_ENA(1);
604
605 if (sctx->flags & SI_CONTEXT_INV_TC_L1)
606 cp_coher_cntl |= S_0085F0_TCL1_ACTION_ENA(1);
607 if (sctx->flags & SI_CONTEXT_INV_TC_L2)
608 cp_coher_cntl |= S_0085F0_TC_ACTION_ENA(1);
609
610 if (sctx->flags & SI_CONTEXT_FLUSH_AND_INV_CB) {
611 cp_coher_cntl |= S_0085F0_CB_ACTION_ENA(1) |
612 S_0085F0_CB0_DEST_BASE_ENA(1) |
613 S_0085F0_CB1_DEST_BASE_ENA(1) |
614 S_0085F0_CB2_DEST_BASE_ENA(1) |
615 S_0085F0_CB3_DEST_BASE_ENA(1) |
616 S_0085F0_CB4_DEST_BASE_ENA(1) |
617 S_0085F0_CB5_DEST_BASE_ENA(1) |
618 S_0085F0_CB6_DEST_BASE_ENA(1) |
619 S_0085F0_CB7_DEST_BASE_ENA(1);
620 }
621 if (sctx->flags & SI_CONTEXT_FLUSH_AND_INV_DB) {
622 cp_coher_cntl |= S_0085F0_DB_ACTION_ENA(1) |
623 S_0085F0_DB_DEST_BASE_ENA(1);
624 }
625
626 if (sctx->flags & SI_CONTEXT_FLUSH_AND_INV_CB_META) {
627 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0) | compute);
628 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_META) | EVENT_INDEX(0));
629 }
630 if (sctx->flags & SI_CONTEXT_FLUSH_AND_INV_DB_META) {
631 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0) | compute);
632 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_DB_META) | EVENT_INDEX(0));
633 }
634 if (sctx->flags & SI_CONTEXT_FLUSH_WITH_INV_L2) {
635 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0) | compute);
636 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH) | EVENT_INDEX(7) |
637 EVENT_WRITE_INV_L2);
638 }
639
640 /* FLUSH_AND_INV events must be emitted before PS_PARTIAL_FLUSH.
641 * Otherwise, clearing CMASK (CB meta) with CP DMA isn't reliable.
642 *
643 * I think the reason is that FLUSH_AND_INV is only added to a queue
644 * and it is PS_PARTIAL_FLUSH that waits for it to complete.
645 */
646 if (sctx->flags & SI_CONTEXT_PS_PARTIAL_FLUSH) {
647 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0) | compute);
648 radeon_emit(cs, EVENT_TYPE(V_028A90_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
649 } else if (sctx->flags & SI_CONTEXT_VS_PARTIAL_FLUSH) {
650 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0) | compute);
651 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
652 }
653 if (sctx->flags & SI_CONTEXT_CS_PARTIAL_FLUSH) {
654 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0) | compute);
655 radeon_emit(cs, EVENT_TYPE(V_028A90_CS_PARTIAL_FLUSH | EVENT_INDEX(4)));
656 }
657 if (sctx->flags & SI_CONTEXT_VGT_FLUSH) {
658 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0) | compute);
659 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
660 }
661 if (sctx->flags & SI_CONTEXT_VGT_STREAMOUT_SYNC) {
662 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0) | compute);
663 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_STREAMOUT_SYNC) | EVENT_INDEX(0));
664 }
665
666 /* SURFACE_SYNC must be emitted after partial flushes.
667 * It looks like SURFACE_SYNC flushes caches immediately and doesn't
668 * wait for any engines. This should be last.
669 */
670 if (cp_coher_cntl) {
671 if (sctx->chip_class >= CIK) {
672 radeon_emit(cs, PKT3(PKT3_ACQUIRE_MEM, 5, 0) | compute);
673 radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */
674 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
675 radeon_emit(cs, 0xff); /* CP_COHER_SIZE_HI */
676 radeon_emit(cs, 0); /* CP_COHER_BASE */
677 radeon_emit(cs, 0); /* CP_COHER_BASE_HI */
678 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
679 } else {
680 radeon_emit(cs, PKT3(PKT3_SURFACE_SYNC, 3, 0) | compute);
681 radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */
682 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
683 radeon_emit(cs, 0); /* CP_COHER_BASE */
684 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
685 }
686 }
687
688 sctx->flags = 0;
689 }
690
691 const struct r600_atom si_atom_cache_flush = { si_emit_cache_flush, 24 }; /* number of CS dwords */
692
693 static void si_get_draw_start_count(struct si_context *sctx,
694 const struct pipe_draw_info *info,
695 unsigned *start, unsigned *count)
696 {
697 if (info->indirect) {
698 struct r600_resource *indirect =
699 (struct r600_resource*)info->indirect;
700 int *data = r600_buffer_map_sync_with_rings(&sctx->b,
701 indirect, PIPE_TRANSFER_READ);
702 data += info->indirect_offset/sizeof(int);
703 *start = data[2];
704 *count = data[0];
705 } else {
706 *start = info->start;
707 *count = info->count;
708 }
709 }
710
711 void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info)
712 {
713 struct si_context *sctx = (struct si_context *)ctx;
714 struct pipe_index_buffer ib = {};
715 unsigned i;
716
717 if (!info->count && !info->indirect &&
718 (info->indexed || !info->count_from_stream_output))
719 return;
720
721 if (!sctx->ps_shader || !sctx->vs_shader) {
722 assert(0);
723 return;
724 }
725 if (!!sctx->tes_shader != (info->mode == PIPE_PRIM_PATCHES)) {
726 assert(0);
727 return;
728 }
729
730 si_decompress_textures(sctx);
731
732 /* Set the rasterization primitive type.
733 *
734 * This must be done after si_decompress_textures, which can call
735 * draw_vbo recursively, and before si_update_shaders, which uses
736 * current_rast_prim for this draw_vbo call. */
737 if (sctx->gs_shader)
738 sctx->current_rast_prim = sctx->gs_shader->gs_output_prim;
739 else if (sctx->tes_shader)
740 sctx->current_rast_prim =
741 sctx->tes_shader->info.properties[TGSI_PROPERTY_TES_PRIM_MODE];
742 else
743 sctx->current_rast_prim = info->mode;
744
745 si_update_shaders(sctx);
746 if (!si_upload_shader_descriptors(sctx))
747 return;
748
749 if (info->indexed) {
750 /* Initialize the index buffer struct. */
751 pipe_resource_reference(&ib.buffer, sctx->index_buffer.buffer);
752 ib.user_buffer = sctx->index_buffer.user_buffer;
753 ib.index_size = sctx->index_buffer.index_size;
754 ib.offset = sctx->index_buffer.offset;
755
756 /* Translate or upload, if needed. */
757 if (ib.index_size == 1) {
758 struct pipe_resource *out_buffer = NULL;
759 unsigned out_offset, start, count, start_offset;
760 void *ptr;
761
762 si_get_draw_start_count(sctx, info, &start, &count);
763 start_offset = start * ib.index_size;
764
765 u_upload_alloc(sctx->b.uploader, start_offset, count * 2,
766 &out_offset, &out_buffer, &ptr);
767
768 util_shorten_ubyte_elts_to_userptr(&sctx->b.b, &ib, 0,
769 ib.offset + start_offset,
770 count, ptr);
771
772 pipe_resource_reference(&ib.buffer, NULL);
773 ib.user_buffer = NULL;
774 ib.buffer = out_buffer;
775 /* info->start will be added by the drawing code */
776 ib.offset = out_offset - start_offset;
777 ib.index_size = 2;
778 } else if (ib.user_buffer && !ib.buffer) {
779 unsigned start, count, start_offset;
780
781 si_get_draw_start_count(sctx, info, &start, &count);
782 start_offset = start * ib.index_size;
783
784 u_upload_data(sctx->b.uploader, start_offset, count * ib.index_size,
785 (char*)ib.user_buffer + start_offset,
786 &ib.offset, &ib.buffer);
787 /* info->start will be added by the drawing code */
788 ib.offset -= start_offset;
789 }
790 }
791
792 if (info->indexed && r600_resource(ib.buffer)->TC_L2_dirty) {
793 sctx->b.flags |= SI_CONTEXT_INV_TC_L2;
794 r600_resource(ib.buffer)->TC_L2_dirty = false;
795 }
796
797 /* Check flush flags. */
798 if (sctx->b.flags)
799 sctx->atoms.s.cache_flush->dirty = true;
800
801 si_need_cs_space(sctx, 0, TRUE);
802
803 /* Emit states. */
804 for (i = 0; i < SI_NUM_ATOMS(sctx); i++) {
805 if (sctx->atoms.array[i]->dirty) {
806 sctx->atoms.array[i]->emit(&sctx->b, sctx->atoms.array[i]);
807 sctx->atoms.array[i]->dirty = false;
808 }
809 }
810
811 si_pm4_emit_dirty(sctx);
812 si_emit_scratch_reloc(sctx);
813 si_emit_rasterizer_prim_state(sctx);
814 si_emit_draw_registers(sctx, info);
815 si_emit_draw_packets(sctx, info, &ib);
816
817 #if SI_TRACE_CS
818 if (sctx->screen->b.trace_bo) {
819 si_trace_emit(sctx);
820 }
821 #endif
822
823 /* Workaround for a VGT hang when streamout is enabled.
824 * It must be done after drawing. */
825 if (sctx->b.family == CHIP_HAWAII &&
826 (sctx->b.streamout.streamout_enabled ||
827 sctx->b.streamout.prims_gen_query_enabled)) {
828 sctx->b.flags |= SI_CONTEXT_VGT_STREAMOUT_SYNC;
829 }
830
831 /* Set the depth buffer as dirty. */
832 if (sctx->framebuffer.state.zsbuf) {
833 struct pipe_surface *surf = sctx->framebuffer.state.zsbuf;
834 struct r600_texture *rtex = (struct r600_texture *)surf->texture;
835
836 rtex->dirty_level_mask |= 1 << surf->u.tex.level;
837 }
838 if (sctx->framebuffer.compressed_cb_mask) {
839 struct pipe_surface *surf;
840 struct r600_texture *rtex;
841 unsigned mask = sctx->framebuffer.compressed_cb_mask;
842
843 do {
844 unsigned i = u_bit_scan(&mask);
845 surf = sctx->framebuffer.state.cbufs[i];
846 rtex = (struct r600_texture*)surf->texture;
847
848 rtex->dirty_level_mask |= 1 << surf->u.tex.level;
849 } while (mask);
850 }
851
852 pipe_resource_reference(&ib.buffer, NULL);
853 sctx->b.num_draw_calls++;
854 }
855
856 #if SI_TRACE_CS
857 void si_trace_emit(struct si_context *sctx)
858 {
859 struct si_screen *sscreen = sctx->screen;
860 struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs;
861 uint64_t va;
862
863 va = sscreen->b.trace_bo->gpu_address;
864 r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx, sscreen->b.trace_bo,
865 RADEON_USAGE_READWRITE, RADEON_PRIO_MIN);
866 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 4, 0));
867 radeon_emit(cs, PKT3_WRITE_DATA_DST_SEL(PKT3_WRITE_DATA_DST_SEL_MEM_SYNC) |
868 PKT3_WRITE_DATA_WR_CONFIRM |
869 PKT3_WRITE_DATA_ENGINE_SEL(PKT3_WRITE_DATA_ENGINE_SEL_ME));
870 radeon_emit(cs, va & 0xFFFFFFFFUL);
871 radeon_emit(cs, (va >> 32UL) & 0xFFFFFFFFUL);
872 radeon_emit(cs, cs->cdw);
873 radeon_emit(cs, sscreen->b.cs_count);
874 }
875 #endif