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freedreno: update generated headers
[mesa.git] / src / gallium / drivers / radeonsi / si_state_draw.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Christian König <christian.koenig@amd.com>
25 */
26
27 #include "si_pipe.h"
28 #include "radeon/r600_cs.h"
29 #include "sid.h"
30
31 #include "util/u_index_modify.h"
32 #include "util/u_upload_mgr.h"
33 #include "util/u_prim.h"
34
35 static unsigned si_conv_pipe_prim(unsigned mode)
36 {
37 static const unsigned prim_conv[] = {
38 [PIPE_PRIM_POINTS] = V_008958_DI_PT_POINTLIST,
39 [PIPE_PRIM_LINES] = V_008958_DI_PT_LINELIST,
40 [PIPE_PRIM_LINE_LOOP] = V_008958_DI_PT_LINELOOP,
41 [PIPE_PRIM_LINE_STRIP] = V_008958_DI_PT_LINESTRIP,
42 [PIPE_PRIM_TRIANGLES] = V_008958_DI_PT_TRILIST,
43 [PIPE_PRIM_TRIANGLE_STRIP] = V_008958_DI_PT_TRISTRIP,
44 [PIPE_PRIM_TRIANGLE_FAN] = V_008958_DI_PT_TRIFAN,
45 [PIPE_PRIM_QUADS] = V_008958_DI_PT_QUADLIST,
46 [PIPE_PRIM_QUAD_STRIP] = V_008958_DI_PT_QUADSTRIP,
47 [PIPE_PRIM_POLYGON] = V_008958_DI_PT_POLYGON,
48 [PIPE_PRIM_LINES_ADJACENCY] = V_008958_DI_PT_LINELIST_ADJ,
49 [PIPE_PRIM_LINE_STRIP_ADJACENCY] = V_008958_DI_PT_LINESTRIP_ADJ,
50 [PIPE_PRIM_TRIANGLES_ADJACENCY] = V_008958_DI_PT_TRILIST_ADJ,
51 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY] = V_008958_DI_PT_TRISTRIP_ADJ,
52 [PIPE_PRIM_PATCHES] = V_008958_DI_PT_PATCH,
53 [R600_PRIM_RECTANGLE_LIST] = V_008958_DI_PT_RECTLIST
54 };
55 assert(mode < ARRAY_SIZE(prim_conv));
56 return prim_conv[mode];
57 }
58
59 static unsigned si_conv_prim_to_gs_out(unsigned mode)
60 {
61 static const int prim_conv[] = {
62 [PIPE_PRIM_POINTS] = V_028A6C_OUTPRIM_TYPE_POINTLIST,
63 [PIPE_PRIM_LINES] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
64 [PIPE_PRIM_LINE_LOOP] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
65 [PIPE_PRIM_LINE_STRIP] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
66 [PIPE_PRIM_TRIANGLES] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
67 [PIPE_PRIM_TRIANGLE_STRIP] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
68 [PIPE_PRIM_TRIANGLE_FAN] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
69 [PIPE_PRIM_QUADS] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
70 [PIPE_PRIM_QUAD_STRIP] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
71 [PIPE_PRIM_POLYGON] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
72 [PIPE_PRIM_LINES_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
73 [PIPE_PRIM_LINE_STRIP_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
74 [PIPE_PRIM_TRIANGLES_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
75 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
76 [PIPE_PRIM_PATCHES] = V_028A6C_OUTPRIM_TYPE_POINTLIST,
77 [R600_PRIM_RECTANGLE_LIST] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
78 };
79 assert(mode < ARRAY_SIZE(prim_conv));
80
81 return prim_conv[mode];
82 }
83
84 /**
85 * This calculates the LDS size for tessellation shaders (VS, TCS, TES).
86 * LS.LDS_SIZE is shared by all 3 shader stages.
87 *
88 * The information about LDS and other non-compile-time parameters is then
89 * written to userdata SGPRs.
90 */
91 static void si_emit_derived_tess_state(struct si_context *sctx,
92 const struct pipe_draw_info *info,
93 unsigned *num_patches)
94 {
95 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
96 struct si_shader_ctx_state *ls = &sctx->vs_shader;
97 /* The TES pointer will only be used for sctx->last_tcs.
98 * It would be wrong to think that TCS = TES. */
99 struct si_shader_selector *tcs =
100 sctx->tcs_shader.cso ? sctx->tcs_shader.cso : sctx->tes_shader.cso;
101 unsigned tes_sh_base = sctx->shader_userdata.sh_base[PIPE_SHADER_TESS_EVAL];
102 unsigned num_tcs_input_cp = info->vertices_per_patch;
103 unsigned num_tcs_output_cp, num_tcs_inputs, num_tcs_outputs;
104 unsigned num_tcs_patch_outputs;
105 unsigned input_vertex_size, output_vertex_size, pervertex_output_patch_size;
106 unsigned input_patch_size, output_patch_size, output_patch0_offset;
107 unsigned perpatch_output_offset, lds_size, ls_rsrc2;
108 unsigned tcs_in_layout, tcs_out_layout, tcs_out_offsets;
109 unsigned offchip_layout, hardware_lds_size, ls_hs_config;
110
111 if (sctx->last_ls == ls->current &&
112 sctx->last_tcs == tcs &&
113 sctx->last_tes_sh_base == tes_sh_base &&
114 sctx->last_num_tcs_input_cp == num_tcs_input_cp) {
115 *num_patches = sctx->last_num_patches;
116 return;
117 }
118
119 sctx->last_ls = ls->current;
120 sctx->last_tcs = tcs;
121 sctx->last_tes_sh_base = tes_sh_base;
122 sctx->last_num_tcs_input_cp = num_tcs_input_cp;
123
124 /* This calculates how shader inputs and outputs among VS, TCS, and TES
125 * are laid out in LDS. */
126 num_tcs_inputs = util_last_bit64(ls->cso->outputs_written);
127
128 if (sctx->tcs_shader.cso) {
129 num_tcs_outputs = util_last_bit64(tcs->outputs_written);
130 num_tcs_output_cp = tcs->info.properties[TGSI_PROPERTY_TCS_VERTICES_OUT];
131 num_tcs_patch_outputs = util_last_bit64(tcs->patch_outputs_written);
132 } else {
133 /* No TCS. Route varyings from LS to TES. */
134 num_tcs_outputs = num_tcs_inputs;
135 num_tcs_output_cp = num_tcs_input_cp;
136 num_tcs_patch_outputs = 2; /* TESSINNER + TESSOUTER */
137 }
138
139 input_vertex_size = num_tcs_inputs * 16;
140 output_vertex_size = num_tcs_outputs * 16;
141
142 input_patch_size = num_tcs_input_cp * input_vertex_size;
143
144 pervertex_output_patch_size = num_tcs_output_cp * output_vertex_size;
145 output_patch_size = pervertex_output_patch_size + num_tcs_patch_outputs * 16;
146
147 /* Ensure that we only need one wave per SIMD so we don't need to check
148 * resource usage. Also ensures that the number of tcs in and out
149 * vertices per threadgroup are at most 256.
150 */
151 *num_patches = 64 / MAX2(num_tcs_input_cp, num_tcs_output_cp) * 4;
152
153 /* Make sure that the data fits in LDS. This assumes the shaders only
154 * use LDS for the inputs and outputs.
155 */
156 hardware_lds_size = sctx->b.chip_class >= CIK ? 65536 : 32768;
157 *num_patches = MIN2(*num_patches, hardware_lds_size / (input_patch_size +
158 output_patch_size));
159
160 /* Make sure the output data fits in the offchip buffer */
161 *num_patches = MIN2(*num_patches,
162 (sctx->screen->tess_offchip_block_dw_size * 4) /
163 output_patch_size);
164
165 /* Not necessary for correctness, but improves performance. The
166 * specific value is taken from the proprietary driver.
167 */
168 *num_patches = MIN2(*num_patches, 40);
169 sctx->last_num_patches = *num_patches;
170
171 output_patch0_offset = input_patch_size * *num_patches;
172 perpatch_output_offset = output_patch0_offset + pervertex_output_patch_size;
173
174 lds_size = output_patch0_offset + output_patch_size * *num_patches;
175 ls_rsrc2 = ls->current->config.rsrc2;
176
177 if (sctx->b.chip_class >= CIK) {
178 assert(lds_size <= 65536);
179 ls_rsrc2 |= S_00B52C_LDS_SIZE(align(lds_size, 512) / 512);
180 } else {
181 assert(lds_size <= 32768);
182 ls_rsrc2 |= S_00B52C_LDS_SIZE(align(lds_size, 256) / 256);
183 }
184
185 /* Due to a hw bug, RSRC2_LS must be written twice with another
186 * LS register written in between. */
187 if (sctx->b.chip_class == CIK && sctx->b.family != CHIP_HAWAII)
188 radeon_set_sh_reg(cs, R_00B52C_SPI_SHADER_PGM_RSRC2_LS, ls_rsrc2);
189 radeon_set_sh_reg_seq(cs, R_00B528_SPI_SHADER_PGM_RSRC1_LS, 2);
190 radeon_emit(cs, ls->current->config.rsrc1);
191 radeon_emit(cs, ls_rsrc2);
192
193 /* Compute userdata SGPRs. */
194 assert(((input_vertex_size / 4) & ~0xff) == 0);
195 assert(((output_vertex_size / 4) & ~0xff) == 0);
196 assert(((input_patch_size / 4) & ~0x1fff) == 0);
197 assert(((output_patch_size / 4) & ~0x1fff) == 0);
198 assert(((output_patch0_offset / 16) & ~0xffff) == 0);
199 assert(((perpatch_output_offset / 16) & ~0xffff) == 0);
200 assert(num_tcs_input_cp <= 32);
201 assert(num_tcs_output_cp <= 32);
202
203 tcs_in_layout = (input_patch_size / 4) |
204 ((input_vertex_size / 4) << 13);
205 tcs_out_layout = (output_patch_size / 4) |
206 ((output_vertex_size / 4) << 13);
207 tcs_out_offsets = (output_patch0_offset / 16) |
208 ((perpatch_output_offset / 16) << 16);
209 offchip_layout = (pervertex_output_patch_size * *num_patches << 16) |
210 (num_tcs_output_cp << 9) | *num_patches;
211
212 /* Set them for LS. */
213 radeon_set_sh_reg(cs,
214 R_00B530_SPI_SHADER_USER_DATA_LS_0 + SI_SGPR_LS_OUT_LAYOUT * 4,
215 tcs_in_layout);
216
217 /* Set them for TCS. */
218 radeon_set_sh_reg_seq(cs,
219 R_00B430_SPI_SHADER_USER_DATA_HS_0 + SI_SGPR_TCS_OFFCHIP_LAYOUT * 4, 4);
220 radeon_emit(cs, offchip_layout);
221 radeon_emit(cs, tcs_out_offsets);
222 radeon_emit(cs, tcs_out_layout | (num_tcs_input_cp << 26));
223 radeon_emit(cs, tcs_in_layout);
224
225 /* Set them for TES. */
226 radeon_set_sh_reg_seq(cs, tes_sh_base + SI_SGPR_TCS_OFFCHIP_LAYOUT * 4, 1);
227 radeon_emit(cs, offchip_layout);
228
229 ls_hs_config = S_028B58_NUM_PATCHES(*num_patches) |
230 S_028B58_HS_NUM_INPUT_CP(num_tcs_input_cp) |
231 S_028B58_HS_NUM_OUTPUT_CP(num_tcs_output_cp);
232
233 if (sctx->b.chip_class >= CIK)
234 radeon_set_context_reg_idx(cs, R_028B58_VGT_LS_HS_CONFIG, 2,
235 ls_hs_config);
236 else
237 radeon_set_context_reg(cs, R_028B58_VGT_LS_HS_CONFIG,
238 ls_hs_config);
239 }
240
241 static unsigned si_num_prims_for_vertices(const struct pipe_draw_info *info)
242 {
243 switch (info->mode) {
244 case PIPE_PRIM_PATCHES:
245 return info->count / info->vertices_per_patch;
246 case R600_PRIM_RECTANGLE_LIST:
247 return info->count / 3;
248 default:
249 return u_prims_for_vertices(info->mode, info->count);
250 }
251 }
252
253 static unsigned si_get_ia_multi_vgt_param(struct si_context *sctx,
254 const struct pipe_draw_info *info,
255 unsigned num_patches)
256 {
257 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
258 unsigned prim = info->mode;
259 unsigned primgroup_size = 128; /* recommended without a GS */
260 unsigned max_primgroup_in_wave = 2;
261
262 /* SWITCH_ON_EOP(0) is always preferable. */
263 bool wd_switch_on_eop = false;
264 bool ia_switch_on_eop = false;
265 bool ia_switch_on_eoi = false;
266 bool partial_vs_wave = false;
267 bool partial_es_wave = false;
268
269 if (sctx->gs_shader.cso)
270 primgroup_size = 64; /* recommended with a GS */
271
272 if (sctx->tes_shader.cso) {
273 /* primgroup_size must be set to a multiple of NUM_PATCHES */
274 primgroup_size = num_patches;
275
276 /* SWITCH_ON_EOI must be set if PrimID is used. */
277 if ((sctx->tcs_shader.cso && sctx->tcs_shader.cso->info.uses_primid) ||
278 sctx->tes_shader.cso->info.uses_primid)
279 ia_switch_on_eoi = true;
280
281 /* Bug with tessellation and GS on Bonaire and older 2 SE chips. */
282 if ((sctx->b.family == CHIP_TAHITI ||
283 sctx->b.family == CHIP_PITCAIRN ||
284 sctx->b.family == CHIP_BONAIRE) &&
285 sctx->gs_shader.cso)
286 partial_vs_wave = true;
287
288 /* Needed for 028B6C_DISTRIBUTION_MODE != 0 */
289 if (sctx->screen->has_distributed_tess) {
290 if (sctx->gs_shader.cso)
291 partial_es_wave = true;
292 else
293 partial_vs_wave = true;
294 }
295 }
296
297 /* This is a hardware requirement. */
298 if ((rs && rs->line_stipple_enable) ||
299 (sctx->b.screen->debug_flags & DBG_SWITCH_ON_EOP)) {
300 ia_switch_on_eop = true;
301 wd_switch_on_eop = true;
302 }
303
304 if (sctx->b.chip_class >= CIK) {
305 /* WD_SWITCH_ON_EOP has no effect on GPUs with less than
306 * 4 shader engines. Set 1 to pass the assertion below.
307 * The other cases are hardware requirements.
308 *
309 * Polaris supports primitive restart with WD_SWITCH_ON_EOP=0
310 * for points, line strips, and tri strips.
311 */
312 if (sctx->b.screen->info.max_se < 4 ||
313 prim == PIPE_PRIM_POLYGON ||
314 prim == PIPE_PRIM_LINE_LOOP ||
315 prim == PIPE_PRIM_TRIANGLE_FAN ||
316 prim == PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY ||
317 (info->primitive_restart &&
318 (sctx->b.family < CHIP_POLARIS10 ||
319 (prim != PIPE_PRIM_POINTS &&
320 prim != PIPE_PRIM_LINE_STRIP &&
321 prim != PIPE_PRIM_TRIANGLE_STRIP))) ||
322 info->count_from_stream_output)
323 wd_switch_on_eop = true;
324
325 /* Hawaii hangs if instancing is enabled and WD_SWITCH_ON_EOP is 0.
326 * We don't know that for indirect drawing, so treat it as
327 * always problematic. */
328 if (sctx->b.family == CHIP_HAWAII &&
329 (info->indirect || info->instance_count > 1))
330 wd_switch_on_eop = true;
331
332 /* Performance recommendation for 4 SE Gfx7-8 parts if
333 * instances are smaller than a primgroup.
334 * Assume indirect draws always use small instances.
335 * This is needed for good VS wave utilization.
336 */
337 if (sctx->b.chip_class <= VI &&
338 sctx->b.screen->info.max_se >= 4 &&
339 (info->indirect ||
340 (info->instance_count > 1 &&
341 si_num_prims_for_vertices(info) < primgroup_size)))
342 wd_switch_on_eop = true;
343
344 /* Required on CIK and later. */
345 if (sctx->b.screen->info.max_se > 2 && !wd_switch_on_eop)
346 ia_switch_on_eoi = true;
347
348 /* Required by Hawaii and, for some special cases, by VI. */
349 if (ia_switch_on_eoi &&
350 (sctx->b.family == CHIP_HAWAII ||
351 (sctx->b.chip_class == VI &&
352 (sctx->gs_shader.cso || max_primgroup_in_wave != 2))))
353 partial_vs_wave = true;
354
355 /* Instancing bug on Bonaire. */
356 if (sctx->b.family == CHIP_BONAIRE && ia_switch_on_eoi &&
357 (info->indirect || info->instance_count > 1))
358 partial_vs_wave = true;
359
360 /* GS hw bug with single-primitive instances and SWITCH_ON_EOI.
361 * The hw doc says all multi-SE chips are affected, but Vulkan
362 * only applies it to Hawaii. Do what Vulkan does.
363 */
364 if (sctx->b.family == CHIP_HAWAII &&
365 sctx->gs_shader.cso &&
366 ia_switch_on_eoi &&
367 (info->indirect ||
368 (info->instance_count > 1 &&
369 si_num_prims_for_vertices(info) <= 1)))
370 sctx->b.flags |= SI_CONTEXT_VGT_FLUSH;
371
372
373 /* If the WD switch is false, the IA switch must be false too. */
374 assert(wd_switch_on_eop || !ia_switch_on_eop);
375 }
376
377 /* If SWITCH_ON_EOI is set, PARTIAL_ES_WAVE must be set too. */
378 if (ia_switch_on_eoi)
379 partial_es_wave = true;
380
381 /* GS requirement. */
382 if (SI_GS_PER_ES / primgroup_size >= sctx->screen->gs_table_depth - 3)
383 partial_es_wave = true;
384
385 return S_028AA8_SWITCH_ON_EOP(ia_switch_on_eop) |
386 S_028AA8_SWITCH_ON_EOI(ia_switch_on_eoi) |
387 S_028AA8_PARTIAL_VS_WAVE_ON(partial_vs_wave) |
388 S_028AA8_PARTIAL_ES_WAVE_ON(partial_es_wave) |
389 S_028AA8_PRIMGROUP_SIZE(primgroup_size - 1) |
390 S_028AA8_WD_SWITCH_ON_EOP(sctx->b.chip_class >= CIK ? wd_switch_on_eop : 0) |
391 S_028AA8_MAX_PRIMGRP_IN_WAVE(sctx->b.chip_class >= VI ?
392 max_primgroup_in_wave : 0);
393 }
394
395 static void si_emit_scratch_reloc(struct si_context *sctx)
396 {
397 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
398
399 if (!sctx->emit_scratch_reloc)
400 return;
401
402 radeon_set_context_reg(cs, R_0286E8_SPI_TMPRING_SIZE,
403 sctx->spi_tmpring_size);
404
405 if (sctx->scratch_buffer) {
406 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
407 sctx->scratch_buffer, RADEON_USAGE_READWRITE,
408 RADEON_PRIO_SCRATCH_BUFFER);
409
410 }
411 sctx->emit_scratch_reloc = false;
412 }
413
414 /* rast_prim is the primitive type after GS. */
415 static void si_emit_rasterizer_prim_state(struct si_context *sctx)
416 {
417 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
418 unsigned rast_prim = sctx->current_rast_prim;
419 struct si_state_rasterizer *rs = sctx->emitted.named.rasterizer;
420
421 /* Skip this if not rendering lines. */
422 if (rast_prim != PIPE_PRIM_LINES &&
423 rast_prim != PIPE_PRIM_LINE_LOOP &&
424 rast_prim != PIPE_PRIM_LINE_STRIP &&
425 rast_prim != PIPE_PRIM_LINES_ADJACENCY &&
426 rast_prim != PIPE_PRIM_LINE_STRIP_ADJACENCY)
427 return;
428
429 if (rast_prim == sctx->last_rast_prim &&
430 rs->pa_sc_line_stipple == sctx->last_sc_line_stipple)
431 return;
432
433 /* For lines, reset the stipple pattern at each primitive. Otherwise,
434 * reset the stipple pattern at each packet (line strips, line loops).
435 */
436 radeon_set_context_reg(cs, R_028A0C_PA_SC_LINE_STIPPLE,
437 rs->pa_sc_line_stipple |
438 S_028A0C_AUTO_RESET_CNTL(rast_prim == PIPE_PRIM_LINES ? 1 : 2));
439
440 sctx->last_rast_prim = rast_prim;
441 sctx->last_sc_line_stipple = rs->pa_sc_line_stipple;
442 }
443
444 static void si_emit_draw_registers(struct si_context *sctx,
445 const struct pipe_draw_info *info)
446 {
447 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
448 unsigned prim = si_conv_pipe_prim(info->mode);
449 unsigned gs_out_prim = si_conv_prim_to_gs_out(sctx->current_rast_prim);
450 unsigned ia_multi_vgt_param, num_patches = 0;
451
452 /* Polaris needs different VTX_REUSE_DEPTH settings depending on
453 * whether the "fractional odd" tessellation spacing is used.
454 */
455 if (sctx->b.family >= CHIP_POLARIS10) {
456 struct si_shader_selector *tes = sctx->tes_shader.cso;
457 unsigned vtx_reuse_depth = 30;
458
459 if (tes &&
460 tes->info.properties[TGSI_PROPERTY_TES_SPACING] ==
461 PIPE_TESS_SPACING_FRACTIONAL_ODD)
462 vtx_reuse_depth = 14;
463
464 if (vtx_reuse_depth != sctx->last_vtx_reuse_depth) {
465 radeon_set_context_reg(cs, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
466 vtx_reuse_depth);
467 sctx->last_vtx_reuse_depth = vtx_reuse_depth;
468 }
469 }
470
471 if (sctx->tes_shader.cso)
472 si_emit_derived_tess_state(sctx, info, &num_patches);
473
474 ia_multi_vgt_param = si_get_ia_multi_vgt_param(sctx, info, num_patches);
475
476 /* Draw state. */
477 if (ia_multi_vgt_param != sctx->last_multi_vgt_param) {
478 if (sctx->b.chip_class >= CIK)
479 radeon_set_context_reg_idx(cs, R_028AA8_IA_MULTI_VGT_PARAM, 1, ia_multi_vgt_param);
480 else
481 radeon_set_context_reg(cs, R_028AA8_IA_MULTI_VGT_PARAM, ia_multi_vgt_param);
482
483 sctx->last_multi_vgt_param = ia_multi_vgt_param;
484 }
485 if (prim != sctx->last_prim) {
486 if (sctx->b.chip_class >= CIK)
487 radeon_set_uconfig_reg_idx(cs, R_030908_VGT_PRIMITIVE_TYPE, 1, prim);
488 else
489 radeon_set_config_reg(cs, R_008958_VGT_PRIMITIVE_TYPE, prim);
490
491 sctx->last_prim = prim;
492 }
493
494 if (gs_out_prim != sctx->last_gs_out_prim) {
495 radeon_set_context_reg(cs, R_028A6C_VGT_GS_OUT_PRIM_TYPE, gs_out_prim);
496 sctx->last_gs_out_prim = gs_out_prim;
497 }
498
499 /* Primitive restart. */
500 if (info->primitive_restart != sctx->last_primitive_restart_en) {
501 radeon_set_context_reg(cs, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, info->primitive_restart);
502 sctx->last_primitive_restart_en = info->primitive_restart;
503
504 }
505 if (info->primitive_restart &&
506 (info->restart_index != sctx->last_restart_index ||
507 sctx->last_restart_index == SI_RESTART_INDEX_UNKNOWN)) {
508 radeon_set_context_reg(cs, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
509 info->restart_index);
510 sctx->last_restart_index = info->restart_index;
511 }
512 }
513
514 static void si_emit_draw_packets(struct si_context *sctx,
515 const struct pipe_draw_info *info,
516 const struct pipe_index_buffer *ib)
517 {
518 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
519 unsigned sh_base_reg = sctx->shader_userdata.sh_base[PIPE_SHADER_VERTEX];
520 bool render_cond_bit = sctx->b.render_cond && !sctx->b.render_cond_force_off;
521 uint32_t index_max_size = 0;
522 uint64_t index_va = 0;
523
524 if (info->count_from_stream_output) {
525 struct r600_so_target *t =
526 (struct r600_so_target*)info->count_from_stream_output;
527 uint64_t va = t->buf_filled_size->gpu_address +
528 t->buf_filled_size_offset;
529
530 radeon_set_context_reg(cs, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE,
531 t->stride_in_dw);
532
533 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
534 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
535 COPY_DATA_DST_SEL(COPY_DATA_REG) |
536 COPY_DATA_WR_CONFIRM);
537 radeon_emit(cs, va); /* src address lo */
538 radeon_emit(cs, va >> 32); /* src address hi */
539 radeon_emit(cs, R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE >> 2);
540 radeon_emit(cs, 0); /* unused */
541
542 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
543 t->buf_filled_size, RADEON_USAGE_READ,
544 RADEON_PRIO_SO_FILLED_SIZE);
545 }
546
547 /* draw packet */
548 if (info->indexed) {
549 if (ib->index_size != sctx->last_index_size) {
550 radeon_emit(cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
551
552 /* index type */
553 switch (ib->index_size) {
554 case 1:
555 radeon_emit(cs, V_028A7C_VGT_INDEX_8);
556 break;
557 case 2:
558 radeon_emit(cs, V_028A7C_VGT_INDEX_16 |
559 (SI_BIG_ENDIAN && sctx->b.chip_class <= CIK ?
560 V_028A7C_VGT_DMA_SWAP_16_BIT : 0));
561 break;
562 case 4:
563 radeon_emit(cs, V_028A7C_VGT_INDEX_32 |
564 (SI_BIG_ENDIAN && sctx->b.chip_class <= CIK ?
565 V_028A7C_VGT_DMA_SWAP_32_BIT : 0));
566 break;
567 default:
568 assert(!"unreachable");
569 return;
570 }
571
572 sctx->last_index_size = ib->index_size;
573 }
574
575 index_max_size = (ib->buffer->width0 - ib->offset) /
576 ib->index_size;
577 index_va = r600_resource(ib->buffer)->gpu_address + ib->offset;
578
579 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
580 (struct r600_resource *)ib->buffer,
581 RADEON_USAGE_READ, RADEON_PRIO_INDEX_BUFFER);
582 } else {
583 /* On CI and later, non-indexed draws overwrite VGT_INDEX_TYPE,
584 * so the state must be re-emitted before the next indexed draw.
585 */
586 if (sctx->b.chip_class >= CIK)
587 sctx->last_index_size = -1;
588 }
589
590 if (!info->indirect) {
591 int base_vertex;
592
593 radeon_emit(cs, PKT3(PKT3_NUM_INSTANCES, 0, 0));
594 radeon_emit(cs, info->instance_count);
595
596 /* Base vertex and start instance. */
597 base_vertex = info->indexed ? info->index_bias : info->start;
598
599 if (base_vertex != sctx->last_base_vertex ||
600 sctx->last_base_vertex == SI_BASE_VERTEX_UNKNOWN ||
601 info->start_instance != sctx->last_start_instance ||
602 info->drawid != sctx->last_drawid ||
603 sh_base_reg != sctx->last_sh_base_reg) {
604 radeon_set_sh_reg_seq(cs, sh_base_reg + SI_SGPR_BASE_VERTEX * 4, 3);
605 radeon_emit(cs, base_vertex);
606 radeon_emit(cs, info->start_instance);
607 radeon_emit(cs, info->drawid);
608
609 sctx->last_base_vertex = base_vertex;
610 sctx->last_start_instance = info->start_instance;
611 sctx->last_drawid = info->drawid;
612 sctx->last_sh_base_reg = sh_base_reg;
613 }
614 } else {
615 uint64_t indirect_va = r600_resource(info->indirect)->gpu_address;
616
617 assert(indirect_va % 8 == 0);
618
619 si_invalidate_draw_sh_constants(sctx);
620
621 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
622 radeon_emit(cs, 1);
623 radeon_emit(cs, indirect_va);
624 radeon_emit(cs, indirect_va >> 32);
625
626 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
627 (struct r600_resource *)info->indirect,
628 RADEON_USAGE_READ, RADEON_PRIO_DRAW_INDIRECT);
629 }
630
631 if (info->indirect) {
632 unsigned di_src_sel = info->indexed ? V_0287F0_DI_SRC_SEL_DMA
633 : V_0287F0_DI_SRC_SEL_AUTO_INDEX;
634
635 assert(info->indirect_offset % 4 == 0);
636
637 if (info->indexed) {
638 radeon_emit(cs, PKT3(PKT3_INDEX_BASE, 1, 0));
639 radeon_emit(cs, index_va);
640 radeon_emit(cs, index_va >> 32);
641
642 radeon_emit(cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
643 radeon_emit(cs, index_max_size);
644 }
645
646 if (!sctx->screen->has_draw_indirect_multi) {
647 radeon_emit(cs, PKT3(info->indexed ? PKT3_DRAW_INDEX_INDIRECT
648 : PKT3_DRAW_INDIRECT,
649 3, render_cond_bit));
650 radeon_emit(cs, info->indirect_offset);
651 radeon_emit(cs, (sh_base_reg + SI_SGPR_BASE_VERTEX * 4 - SI_SH_REG_OFFSET) >> 2);
652 radeon_emit(cs, (sh_base_reg + SI_SGPR_START_INSTANCE * 4 - SI_SH_REG_OFFSET) >> 2);
653 radeon_emit(cs, di_src_sel);
654 } else {
655 uint64_t count_va = 0;
656
657 if (info->indirect_params) {
658 struct r600_resource *params_buf =
659 (struct r600_resource *)info->indirect_params;
660
661 radeon_add_to_buffer_list(
662 &sctx->b, &sctx->b.gfx, params_buf,
663 RADEON_USAGE_READ, RADEON_PRIO_DRAW_INDIRECT);
664
665 count_va = params_buf->gpu_address + info->indirect_params_offset;
666 }
667
668 radeon_emit(cs, PKT3(info->indexed ? PKT3_DRAW_INDEX_INDIRECT_MULTI :
669 PKT3_DRAW_INDIRECT_MULTI,
670 8, render_cond_bit));
671 radeon_emit(cs, info->indirect_offset);
672 radeon_emit(cs, (sh_base_reg + SI_SGPR_BASE_VERTEX * 4 - SI_SH_REG_OFFSET) >> 2);
673 radeon_emit(cs, (sh_base_reg + SI_SGPR_START_INSTANCE * 4 - SI_SH_REG_OFFSET) >> 2);
674 radeon_emit(cs, ((sh_base_reg + SI_SGPR_DRAWID * 4 - SI_SH_REG_OFFSET) >> 2) |
675 S_2C3_DRAW_INDEX_ENABLE(1) |
676 S_2C3_COUNT_INDIRECT_ENABLE(!!info->indirect_params));
677 radeon_emit(cs, info->indirect_count);
678 radeon_emit(cs, count_va);
679 radeon_emit(cs, count_va >> 32);
680 radeon_emit(cs, info->indirect_stride);
681 radeon_emit(cs, di_src_sel);
682 }
683 } else {
684 if (info->indexed) {
685 index_va += info->start * ib->index_size;
686
687 radeon_emit(cs, PKT3(PKT3_DRAW_INDEX_2, 4, render_cond_bit));
688 radeon_emit(cs, index_max_size);
689 radeon_emit(cs, index_va);
690 radeon_emit(cs, (index_va >> 32UL) & 0xFF);
691 radeon_emit(cs, info->count);
692 radeon_emit(cs, V_0287F0_DI_SRC_SEL_DMA);
693 } else {
694 radeon_emit(cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, render_cond_bit));
695 radeon_emit(cs, info->count);
696 radeon_emit(cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
697 S_0287F0_USE_OPAQUE(!!info->count_from_stream_output));
698 }
699 }
700 }
701
702 static void si_emit_surface_sync(struct r600_common_context *rctx,
703 unsigned cp_coher_cntl)
704 {
705 struct radeon_winsys_cs *cs = rctx->gfx.cs;
706
707 /* ACQUIRE_MEM is only required on a compute ring. */
708 radeon_emit(cs, PKT3(PKT3_SURFACE_SYNC, 3, 0));
709 radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */
710 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
711 radeon_emit(cs, 0); /* CP_COHER_BASE */
712 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
713 }
714
715 void si_emit_cache_flush(struct si_context *sctx)
716 {
717 struct r600_common_context *rctx = &sctx->b;
718 struct radeon_winsys_cs *cs = rctx->gfx.cs;
719 uint32_t cp_coher_cntl = 0;
720
721 /* SI has a bug that it always flushes ICACHE and KCACHE if either
722 * bit is set. An alternative way is to write SQC_CACHES, but that
723 * doesn't seem to work reliably. Since the bug doesn't affect
724 * correctness (it only does more work than necessary) and
725 * the performance impact is likely negligible, there is no plan
726 * to add a workaround for it.
727 */
728
729 if (rctx->flags & SI_CONTEXT_INV_ICACHE)
730 cp_coher_cntl |= S_0085F0_SH_ICACHE_ACTION_ENA(1);
731 if (rctx->flags & SI_CONTEXT_INV_SMEM_L1)
732 cp_coher_cntl |= S_0085F0_SH_KCACHE_ACTION_ENA(1);
733
734 if (rctx->flags & SI_CONTEXT_FLUSH_AND_INV_CB) {
735 cp_coher_cntl |= S_0085F0_CB_ACTION_ENA(1) |
736 S_0085F0_CB0_DEST_BASE_ENA(1) |
737 S_0085F0_CB1_DEST_BASE_ENA(1) |
738 S_0085F0_CB2_DEST_BASE_ENA(1) |
739 S_0085F0_CB3_DEST_BASE_ENA(1) |
740 S_0085F0_CB4_DEST_BASE_ENA(1) |
741 S_0085F0_CB5_DEST_BASE_ENA(1) |
742 S_0085F0_CB6_DEST_BASE_ENA(1) |
743 S_0085F0_CB7_DEST_BASE_ENA(1);
744
745 /* Necessary for DCC */
746 if (rctx->chip_class == VI)
747 r600_gfx_write_event_eop(rctx, V_028A90_FLUSH_AND_INV_CB_DATA_TS,
748 0, 0, NULL, 0, 0, 0);
749 }
750 if (rctx->flags & SI_CONTEXT_FLUSH_AND_INV_DB) {
751 cp_coher_cntl |= S_0085F0_DB_ACTION_ENA(1) |
752 S_0085F0_DB_DEST_BASE_ENA(1);
753 }
754
755 if (rctx->flags & SI_CONTEXT_FLUSH_AND_INV_CB_META) {
756 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
757 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_META) | EVENT_INDEX(0));
758 /* needed for wait for idle in SURFACE_SYNC */
759 assert(rctx->flags & SI_CONTEXT_FLUSH_AND_INV_CB);
760 }
761 if (rctx->flags & SI_CONTEXT_FLUSH_AND_INV_DB_META) {
762 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
763 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_DB_META) | EVENT_INDEX(0));
764 /* needed for wait for idle in SURFACE_SYNC */
765 assert(rctx->flags & SI_CONTEXT_FLUSH_AND_INV_DB);
766 }
767
768 /* Wait for shader engines to go idle.
769 * VS and PS waits are unnecessary if SURFACE_SYNC is going to wait
770 * for everything including CB/DB cache flushes.
771 */
772 if (!(rctx->flags & (SI_CONTEXT_FLUSH_AND_INV_CB |
773 SI_CONTEXT_FLUSH_AND_INV_DB))) {
774 if (rctx->flags & SI_CONTEXT_PS_PARTIAL_FLUSH) {
775 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
776 radeon_emit(cs, EVENT_TYPE(V_028A90_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
777 /* Only count explicit shader flushes, not implicit ones
778 * done by SURFACE_SYNC.
779 */
780 rctx->num_vs_flushes++;
781 rctx->num_ps_flushes++;
782 } else if (rctx->flags & SI_CONTEXT_VS_PARTIAL_FLUSH) {
783 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
784 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
785 rctx->num_vs_flushes++;
786 }
787 }
788
789 if (rctx->flags & SI_CONTEXT_CS_PARTIAL_FLUSH &&
790 sctx->compute_is_busy) {
791 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
792 radeon_emit(cs, EVENT_TYPE(V_028A90_CS_PARTIAL_FLUSH | EVENT_INDEX(4)));
793 rctx->num_cs_flushes++;
794 sctx->compute_is_busy = false;
795 }
796
797 /* VGT state synchronization. */
798 if (rctx->flags & SI_CONTEXT_VGT_FLUSH) {
799 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
800 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
801 }
802 if (rctx->flags & SI_CONTEXT_VGT_STREAMOUT_SYNC) {
803 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
804 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_STREAMOUT_SYNC) | EVENT_INDEX(0));
805 }
806
807 /* Make sure ME is idle (it executes most packets) before continuing.
808 * This prevents read-after-write hazards between PFP and ME.
809 */
810 if (cp_coher_cntl ||
811 (rctx->flags & (SI_CONTEXT_CS_PARTIAL_FLUSH |
812 SI_CONTEXT_INV_VMEM_L1 |
813 SI_CONTEXT_INV_GLOBAL_L2 |
814 SI_CONTEXT_WRITEBACK_GLOBAL_L2))) {
815 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
816 radeon_emit(cs, 0);
817 }
818
819 /* When one of the CP_COHER_CNTL.DEST_BASE flags is set, SURFACE_SYNC
820 * waits for idle. Therefore, it should be last. SURFACE_SYNC is done
821 * in PFP.
822 *
823 * cp_coher_cntl should contain all necessary flags except TC flags
824 * at this point.
825 *
826 * SI-CIK don't support L2 write-back.
827 */
828 if (rctx->flags & SI_CONTEXT_INV_GLOBAL_L2 ||
829 (rctx->chip_class <= CIK &&
830 (rctx->flags & SI_CONTEXT_WRITEBACK_GLOBAL_L2))) {
831 /* Invalidate L1 & L2. (L1 is always invalidated)
832 * WB must be set on VI+ when TC_ACTION is set.
833 */
834 si_emit_surface_sync(rctx, cp_coher_cntl |
835 S_0085F0_TC_ACTION_ENA(1) |
836 S_0301F0_TC_WB_ACTION_ENA(rctx->chip_class >= VI));
837 cp_coher_cntl = 0;
838 } else {
839 /* L1 invalidation and L2 writeback must be done separately,
840 * because both operations can't be done together.
841 */
842 if (rctx->flags & SI_CONTEXT_WRITEBACK_GLOBAL_L2) {
843 /* WB = write-back
844 * NC = apply to non-coherent MTYPEs
845 * (i.e. MTYPE <= 1, which is what we use everywhere)
846 *
847 * WB doesn't work without NC.
848 */
849 si_emit_surface_sync(rctx, cp_coher_cntl |
850 S_0301F0_TC_WB_ACTION_ENA(1) |
851 S_0301F0_TC_NC_ACTION_ENA(1));
852 cp_coher_cntl = 0;
853 }
854 if (rctx->flags & SI_CONTEXT_INV_VMEM_L1) {
855 /* Invalidate per-CU VMEM L1. */
856 si_emit_surface_sync(rctx, cp_coher_cntl |
857 S_0085F0_TCL1_ACTION_ENA(1));
858 cp_coher_cntl = 0;
859 }
860 }
861
862 /* If TC flushes haven't cleared this... */
863 if (cp_coher_cntl)
864 si_emit_surface_sync(rctx, cp_coher_cntl);
865
866 if (rctx->flags & R600_CONTEXT_START_PIPELINE_STATS) {
867 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
868 radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_START) |
869 EVENT_INDEX(0));
870 } else if (rctx->flags & R600_CONTEXT_STOP_PIPELINE_STATS) {
871 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
872 radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_STOP) |
873 EVENT_INDEX(0));
874 }
875
876 rctx->flags = 0;
877 }
878
879 static void si_get_draw_start_count(struct si_context *sctx,
880 const struct pipe_draw_info *info,
881 unsigned *start, unsigned *count)
882 {
883 if (info->indirect) {
884 struct r600_resource *indirect =
885 (struct r600_resource*)info->indirect;
886 int *data = r600_buffer_map_sync_with_rings(&sctx->b,
887 indirect, PIPE_TRANSFER_READ);
888 data += info->indirect_offset/sizeof(int);
889 *start = data[2];
890 *count = data[0];
891 } else {
892 *start = info->start;
893 *count = info->count;
894 }
895 }
896
897 void si_ce_pre_draw_synchronization(struct si_context *sctx)
898 {
899 if (sctx->ce_need_synchronization) {
900 radeon_emit(sctx->ce_ib, PKT3(PKT3_INCREMENT_CE_COUNTER, 0, 0));
901 radeon_emit(sctx->ce_ib, 1);
902
903 radeon_emit(sctx->b.gfx.cs, PKT3(PKT3_WAIT_ON_CE_COUNTER, 0, 0));
904 radeon_emit(sctx->b.gfx.cs, 1);
905 }
906 }
907
908 void si_ce_post_draw_synchronization(struct si_context *sctx)
909 {
910 if (sctx->ce_need_synchronization) {
911 radeon_emit(sctx->b.gfx.cs, PKT3(PKT3_INCREMENT_DE_COUNTER, 0, 0));
912 radeon_emit(sctx->b.gfx.cs, 0);
913
914 sctx->ce_need_synchronization = false;
915 }
916 }
917
918 void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info)
919 {
920 struct si_context *sctx = (struct si_context *)ctx;
921 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
922 struct pipe_index_buffer ib = {};
923 unsigned mask, dirty_fb_counter, dirty_tex_counter, rast_prim;
924
925 if (likely(!info->indirect)) {
926 /* SI-CI treat instance_count==0 as instance_count==1. There is
927 * no workaround for indirect draws, but we can at least skip
928 * direct draws.
929 */
930 if (unlikely(!info->instance_count))
931 return;
932
933 /* Handle count == 0. */
934 if (unlikely(!info->count &&
935 (info->indexed || !info->count_from_stream_output)))
936 return;
937 }
938
939 if (unlikely(!sctx->vs_shader.cso)) {
940 assert(0);
941 return;
942 }
943 if (unlikely(!sctx->ps_shader.cso && (!rs || !rs->rasterizer_discard))) {
944 assert(0);
945 return;
946 }
947 if (unlikely(!!sctx->tes_shader.cso != (info->mode == PIPE_PRIM_PATCHES))) {
948 assert(0);
949 return;
950 }
951
952 /* Re-emit the framebuffer state if needed. */
953 dirty_fb_counter = p_atomic_read(&sctx->b.screen->dirty_fb_counter);
954 if (unlikely(dirty_fb_counter != sctx->b.last_dirty_fb_counter)) {
955 sctx->b.last_dirty_fb_counter = dirty_fb_counter;
956 sctx->framebuffer.dirty_cbufs |=
957 ((1 << sctx->framebuffer.state.nr_cbufs) - 1);
958 sctx->framebuffer.dirty_zsbuf = true;
959 si_mark_atom_dirty(sctx, &sctx->framebuffer.atom);
960 }
961
962 /* Invalidate & recompute texture descriptors if needed. */
963 dirty_tex_counter = p_atomic_read(&sctx->b.screen->dirty_tex_descriptor_counter);
964 if (unlikely(dirty_tex_counter != sctx->b.last_dirty_tex_descriptor_counter)) {
965 sctx->b.last_dirty_tex_descriptor_counter = dirty_tex_counter;
966 si_update_all_texture_descriptors(sctx);
967 }
968
969 si_decompress_graphics_textures(sctx);
970
971 /* Set the rasterization primitive type.
972 *
973 * This must be done after si_decompress_textures, which can call
974 * draw_vbo recursively, and before si_update_shaders, which uses
975 * current_rast_prim for this draw_vbo call. */
976 if (sctx->gs_shader.cso)
977 rast_prim = sctx->gs_shader.cso->gs_output_prim;
978 else if (sctx->tes_shader.cso)
979 rast_prim = sctx->tes_shader.cso->info.properties[TGSI_PROPERTY_TES_PRIM_MODE];
980 else
981 rast_prim = info->mode;
982
983 if (rast_prim != sctx->current_rast_prim) {
984 sctx->current_rast_prim = rast_prim;
985 sctx->do_update_shaders = true;
986 }
987
988 if (sctx->gs_shader.cso) {
989 /* Determine whether the GS triangle strip adjacency fix should
990 * be applied. Rotate every other triangle if
991 * - triangle strips with adjacency are fed to the GS and
992 * - primitive restart is disabled (the rotation doesn't help
993 * when the restart occurs after an odd number of triangles).
994 */
995 bool gs_tri_strip_adj_fix =
996 !sctx->tes_shader.cso &&
997 info->mode == PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY &&
998 !info->primitive_restart;
999
1000 if (gs_tri_strip_adj_fix != sctx->gs_tri_strip_adj_fix) {
1001 sctx->gs_tri_strip_adj_fix = gs_tri_strip_adj_fix;
1002 sctx->do_update_shaders = true;
1003 }
1004 }
1005
1006 if (sctx->do_update_shaders && !si_update_shaders(sctx))
1007 return;
1008
1009 if (!si_upload_graphics_shader_descriptors(sctx))
1010 return;
1011
1012 if (info->indexed) {
1013 /* Initialize the index buffer struct. */
1014 pipe_resource_reference(&ib.buffer, sctx->index_buffer.buffer);
1015 ib.user_buffer = sctx->index_buffer.user_buffer;
1016 ib.index_size = sctx->index_buffer.index_size;
1017 ib.offset = sctx->index_buffer.offset;
1018
1019 /* Translate or upload, if needed. */
1020 /* 8-bit indices are supported on VI. */
1021 if (sctx->b.chip_class <= CIK && ib.index_size == 1) {
1022 struct pipe_resource *out_buffer = NULL;
1023 unsigned out_offset, start, count, start_offset;
1024 void *ptr;
1025
1026 si_get_draw_start_count(sctx, info, &start, &count);
1027 start_offset = start * ib.index_size;
1028
1029 u_upload_alloc(sctx->b.uploader, start_offset, count * 2, 256,
1030 &out_offset, &out_buffer, &ptr);
1031 if (!out_buffer) {
1032 pipe_resource_reference(&ib.buffer, NULL);
1033 return;
1034 }
1035
1036 util_shorten_ubyte_elts_to_userptr(&sctx->b.b, &ib, 0,
1037 ib.offset + start_offset,
1038 count, ptr);
1039
1040 pipe_resource_reference(&ib.buffer, NULL);
1041 ib.user_buffer = NULL;
1042 ib.buffer = out_buffer;
1043 /* info->start will be added by the drawing code */
1044 ib.offset = out_offset - start_offset;
1045 ib.index_size = 2;
1046 } else if (ib.user_buffer && !ib.buffer) {
1047 unsigned start, count, start_offset;
1048
1049 si_get_draw_start_count(sctx, info, &start, &count);
1050 start_offset = start * ib.index_size;
1051
1052 u_upload_data(sctx->b.uploader, start_offset, count * ib.index_size,
1053 256, (char*)ib.user_buffer + start_offset,
1054 &ib.offset, &ib.buffer);
1055 if (!ib.buffer)
1056 return;
1057 /* info->start will be added by the drawing code */
1058 ib.offset -= start_offset;
1059 }
1060 }
1061
1062 /* VI reads index buffers through TC L2. */
1063 if (info->indexed && sctx->b.chip_class <= CIK &&
1064 r600_resource(ib.buffer)->TC_L2_dirty) {
1065 sctx->b.flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
1066 r600_resource(ib.buffer)->TC_L2_dirty = false;
1067 }
1068
1069 if (info->indirect && r600_resource(info->indirect)->TC_L2_dirty) {
1070 sctx->b.flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
1071 r600_resource(info->indirect)->TC_L2_dirty = false;
1072 }
1073
1074 if (info->indirect_params &&
1075 r600_resource(info->indirect_params)->TC_L2_dirty) {
1076 sctx->b.flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
1077 r600_resource(info->indirect_params)->TC_L2_dirty = false;
1078 }
1079
1080 /* Add buffer sizes for memory checking in need_cs_space. */
1081 if (sctx->emit_scratch_reloc && sctx->scratch_buffer)
1082 r600_context_add_resource_size(ctx, &sctx->scratch_buffer->b.b);
1083 if (info->indirect)
1084 r600_context_add_resource_size(ctx, info->indirect);
1085
1086 si_need_cs_space(sctx);
1087
1088 /* Since we've called r600_context_add_resource_size for vertex buffers,
1089 * this must be called after si_need_cs_space, because we must let
1090 * need_cs_space flush before we add buffers to the buffer list.
1091 */
1092 if (!si_upload_vertex_buffer_descriptors(sctx))
1093 return;
1094
1095 /* Flushed caches prior to emitting states. */
1096 if (sctx->b.flags)
1097 si_emit_cache_flush(sctx);
1098
1099 /* Emit states. */
1100 mask = sctx->dirty_atoms;
1101 while (mask) {
1102 struct r600_atom *atom = sctx->atoms.array[u_bit_scan(&mask)];
1103
1104 atom->emit(&sctx->b, atom);
1105 }
1106 sctx->dirty_atoms = 0;
1107
1108 si_pm4_emit_dirty(sctx);
1109 si_emit_scratch_reloc(sctx);
1110 si_emit_rasterizer_prim_state(sctx);
1111 si_emit_draw_registers(sctx, info);
1112
1113 si_ce_pre_draw_synchronization(sctx);
1114
1115 si_emit_draw_packets(sctx, info, &ib);
1116
1117 si_ce_post_draw_synchronization(sctx);
1118
1119 if (sctx->trace_buf)
1120 si_trace_emit(sctx);
1121
1122 /* Workaround for a VGT hang when streamout is enabled.
1123 * It must be done after drawing. */
1124 if ((sctx->b.family == CHIP_HAWAII ||
1125 sctx->b.family == CHIP_TONGA ||
1126 sctx->b.family == CHIP_FIJI) &&
1127 r600_get_strmout_en(&sctx->b)) {
1128 sctx->b.flags |= SI_CONTEXT_VGT_STREAMOUT_SYNC;
1129 }
1130
1131 /* Set the depth buffer as dirty. */
1132 if (sctx->framebuffer.state.zsbuf) {
1133 struct pipe_surface *surf = sctx->framebuffer.state.zsbuf;
1134 struct r600_texture *rtex = (struct r600_texture *)surf->texture;
1135
1136 if (!rtex->tc_compatible_htile)
1137 rtex->dirty_level_mask |= 1 << surf->u.tex.level;
1138
1139 if (rtex->surface.flags & RADEON_SURF_SBUFFER)
1140 rtex->stencil_dirty_level_mask |= 1 << surf->u.tex.level;
1141 }
1142 if (sctx->framebuffer.compressed_cb_mask) {
1143 struct pipe_surface *surf;
1144 struct r600_texture *rtex;
1145 unsigned mask = sctx->framebuffer.compressed_cb_mask;
1146
1147 do {
1148 unsigned i = u_bit_scan(&mask);
1149 surf = sctx->framebuffer.state.cbufs[i];
1150 rtex = (struct r600_texture*)surf->texture;
1151
1152 if (rtex->fmask.size)
1153 rtex->dirty_level_mask |= 1 << surf->u.tex.level;
1154 if (rtex->dcc_gather_statistics)
1155 rtex->separate_dcc_dirty = true;
1156 } while (mask);
1157 }
1158
1159 pipe_resource_reference(&ib.buffer, NULL);
1160 sctx->b.num_draw_calls++;
1161 if (G_0286E8_WAVESIZE(sctx->spi_tmpring_size))
1162 sctx->b.num_spill_draw_calls++;
1163 }
1164
1165 void si_trace_emit(struct si_context *sctx)
1166 {
1167 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
1168
1169 sctx->trace_id++;
1170 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, sctx->trace_buf,
1171 RADEON_USAGE_READWRITE, RADEON_PRIO_TRACE);
1172 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
1173 radeon_emit(cs, S_370_DST_SEL(V_370_MEMORY_SYNC) |
1174 S_370_WR_CONFIRM(1) |
1175 S_370_ENGINE_SEL(V_370_ME));
1176 radeon_emit(cs, sctx->trace_buf->gpu_address);
1177 radeon_emit(cs, sctx->trace_buf->gpu_address >> 32);
1178 radeon_emit(cs, sctx->trace_id);
1179 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1180 radeon_emit(cs, SI_ENCODE_TRACE_POINT(sctx->trace_id));
1181 }