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[mesa.git] / src / gallium / drivers / radeonsi / si_state_draw.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Christian König <christian.koenig@amd.com>
25 */
26
27 #include "si_pipe.h"
28 #include "radeon/r600_cs.h"
29 #include "sid.h"
30 #include "gfx9d.h"
31
32 #include "util/u_index_modify.h"
33 #include "util/u_upload_mgr.h"
34 #include "util/u_prim.h"
35
36 #include "ac_debug.h"
37
38 static unsigned si_conv_pipe_prim(unsigned mode)
39 {
40 static const unsigned prim_conv[] = {
41 [PIPE_PRIM_POINTS] = V_008958_DI_PT_POINTLIST,
42 [PIPE_PRIM_LINES] = V_008958_DI_PT_LINELIST,
43 [PIPE_PRIM_LINE_LOOP] = V_008958_DI_PT_LINELOOP,
44 [PIPE_PRIM_LINE_STRIP] = V_008958_DI_PT_LINESTRIP,
45 [PIPE_PRIM_TRIANGLES] = V_008958_DI_PT_TRILIST,
46 [PIPE_PRIM_TRIANGLE_STRIP] = V_008958_DI_PT_TRISTRIP,
47 [PIPE_PRIM_TRIANGLE_FAN] = V_008958_DI_PT_TRIFAN,
48 [PIPE_PRIM_QUADS] = V_008958_DI_PT_QUADLIST,
49 [PIPE_PRIM_QUAD_STRIP] = V_008958_DI_PT_QUADSTRIP,
50 [PIPE_PRIM_POLYGON] = V_008958_DI_PT_POLYGON,
51 [PIPE_PRIM_LINES_ADJACENCY] = V_008958_DI_PT_LINELIST_ADJ,
52 [PIPE_PRIM_LINE_STRIP_ADJACENCY] = V_008958_DI_PT_LINESTRIP_ADJ,
53 [PIPE_PRIM_TRIANGLES_ADJACENCY] = V_008958_DI_PT_TRILIST_ADJ,
54 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY] = V_008958_DI_PT_TRISTRIP_ADJ,
55 [PIPE_PRIM_PATCHES] = V_008958_DI_PT_PATCH,
56 [R600_PRIM_RECTANGLE_LIST] = V_008958_DI_PT_RECTLIST
57 };
58 assert(mode < ARRAY_SIZE(prim_conv));
59 return prim_conv[mode];
60 }
61
62 static unsigned si_conv_prim_to_gs_out(unsigned mode)
63 {
64 static const int prim_conv[] = {
65 [PIPE_PRIM_POINTS] = V_028A6C_OUTPRIM_TYPE_POINTLIST,
66 [PIPE_PRIM_LINES] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
67 [PIPE_PRIM_LINE_LOOP] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
68 [PIPE_PRIM_LINE_STRIP] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
69 [PIPE_PRIM_TRIANGLES] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
70 [PIPE_PRIM_TRIANGLE_STRIP] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
71 [PIPE_PRIM_TRIANGLE_FAN] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
72 [PIPE_PRIM_QUADS] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
73 [PIPE_PRIM_QUAD_STRIP] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
74 [PIPE_PRIM_POLYGON] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
75 [PIPE_PRIM_LINES_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
76 [PIPE_PRIM_LINE_STRIP_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
77 [PIPE_PRIM_TRIANGLES_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
78 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
79 [PIPE_PRIM_PATCHES] = V_028A6C_OUTPRIM_TYPE_POINTLIST,
80 [R600_PRIM_RECTANGLE_LIST] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
81 };
82 assert(mode < ARRAY_SIZE(prim_conv));
83
84 return prim_conv[mode];
85 }
86
87 /**
88 * This calculates the LDS size for tessellation shaders (VS, TCS, TES).
89 * LS.LDS_SIZE is shared by all 3 shader stages.
90 *
91 * The information about LDS and other non-compile-time parameters is then
92 * written to userdata SGPRs.
93 */
94 static void si_emit_derived_tess_state(struct si_context *sctx,
95 const struct pipe_draw_info *info,
96 unsigned *num_patches)
97 {
98 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
99 struct si_shader *ls_current;
100 struct si_shader_selector *ls;
101 /* The TES pointer will only be used for sctx->last_tcs.
102 * It would be wrong to think that TCS = TES. */
103 struct si_shader_selector *tcs =
104 sctx->tcs_shader.cso ? sctx->tcs_shader.cso : sctx->tes_shader.cso;
105 unsigned tes_sh_base = sctx->shader_userdata.sh_base[PIPE_SHADER_TESS_EVAL];
106 unsigned num_tcs_input_cp = info->vertices_per_patch;
107 unsigned num_tcs_output_cp, num_tcs_inputs, num_tcs_outputs;
108 unsigned num_tcs_patch_outputs;
109 unsigned input_vertex_size, output_vertex_size, pervertex_output_patch_size;
110 unsigned input_patch_size, output_patch_size, output_patch0_offset;
111 unsigned perpatch_output_offset, lds_size;
112 unsigned tcs_in_layout, tcs_out_layout, tcs_out_offsets;
113 unsigned offchip_layout, hardware_lds_size, ls_hs_config;
114
115 /* Since GFX9 has merged LS-HS in the TCS state, set LS = TCS. */
116 if (sctx->b.chip_class >= GFX9) {
117 if (sctx->tcs_shader.cso)
118 ls_current = sctx->tcs_shader.current;
119 else
120 ls_current = sctx->fixed_func_tcs_shader.current;
121
122 ls = ls_current->key.part.tcs.ls;
123 } else {
124 ls_current = sctx->vs_shader.current;
125 ls = sctx->vs_shader.cso;
126 }
127
128 if (sctx->last_ls == ls_current &&
129 sctx->last_tcs == tcs &&
130 sctx->last_tes_sh_base == tes_sh_base &&
131 sctx->last_num_tcs_input_cp == num_tcs_input_cp) {
132 *num_patches = sctx->last_num_patches;
133 return;
134 }
135
136 sctx->last_ls = ls_current;
137 sctx->last_tcs = tcs;
138 sctx->last_tes_sh_base = tes_sh_base;
139 sctx->last_num_tcs_input_cp = num_tcs_input_cp;
140
141 /* This calculates how shader inputs and outputs among VS, TCS, and TES
142 * are laid out in LDS. */
143 num_tcs_inputs = util_last_bit64(ls->outputs_written);
144
145 if (sctx->tcs_shader.cso) {
146 num_tcs_outputs = util_last_bit64(tcs->outputs_written);
147 num_tcs_output_cp = tcs->info.properties[TGSI_PROPERTY_TCS_VERTICES_OUT];
148 num_tcs_patch_outputs = util_last_bit64(tcs->patch_outputs_written);
149 } else {
150 /* No TCS. Route varyings from LS to TES. */
151 num_tcs_outputs = num_tcs_inputs;
152 num_tcs_output_cp = num_tcs_input_cp;
153 num_tcs_patch_outputs = 2; /* TESSINNER + TESSOUTER */
154 }
155
156 input_vertex_size = num_tcs_inputs * 16;
157 output_vertex_size = num_tcs_outputs * 16;
158
159 input_patch_size = num_tcs_input_cp * input_vertex_size;
160
161 pervertex_output_patch_size = num_tcs_output_cp * output_vertex_size;
162 output_patch_size = pervertex_output_patch_size + num_tcs_patch_outputs * 16;
163
164 /* Ensure that we only need one wave per SIMD so we don't need to check
165 * resource usage. Also ensures that the number of tcs in and out
166 * vertices per threadgroup are at most 256.
167 */
168 *num_patches = 64 / MAX2(num_tcs_input_cp, num_tcs_output_cp) * 4;
169
170 /* Make sure that the data fits in LDS. This assumes the shaders only
171 * use LDS for the inputs and outputs.
172 */
173 hardware_lds_size = sctx->b.chip_class >= CIK ? 65536 : 32768;
174 *num_patches = MIN2(*num_patches, hardware_lds_size / (input_patch_size +
175 output_patch_size));
176
177 /* Make sure the output data fits in the offchip buffer */
178 *num_patches = MIN2(*num_patches,
179 (sctx->screen->tess_offchip_block_dw_size * 4) /
180 output_patch_size);
181
182 /* Not necessary for correctness, but improves performance. The
183 * specific value is taken from the proprietary driver.
184 */
185 *num_patches = MIN2(*num_patches, 40);
186
187 /* SI bug workaround - limit LS-HS threadgroups to only one wave. */
188 if (sctx->b.chip_class == SI) {
189 unsigned one_wave = 64 / MAX2(num_tcs_input_cp, num_tcs_output_cp);
190 *num_patches = MIN2(*num_patches, one_wave);
191
192 if (sctx->screen->b.info.max_se == 1) {
193 /* The VGT HS block increments the patch ID unconditionally
194 * within a single threadgroup. This results in incorrect
195 * patch IDs when instanced draws are used.
196 *
197 * The intended solution is to restrict threadgroups to
198 * a single instance by setting SWITCH_ON_EOI, which
199 * should cause IA to split instances up. However, this
200 * doesn't work correctly on SI when there is no other
201 * SE to switch to.
202 */
203 *num_patches = 1;
204 }
205 }
206
207 sctx->last_num_patches = *num_patches;
208
209 output_patch0_offset = input_patch_size * *num_patches;
210 perpatch_output_offset = output_patch0_offset + pervertex_output_patch_size;
211
212 /* Compute userdata SGPRs. */
213 assert(((input_vertex_size / 4) & ~0xff) == 0);
214 assert(((output_vertex_size / 4) & ~0xff) == 0);
215 assert(((input_patch_size / 4) & ~0x1fff) == 0);
216 assert(((output_patch_size / 4) & ~0x1fff) == 0);
217 assert(((output_patch0_offset / 16) & ~0xffff) == 0);
218 assert(((perpatch_output_offset / 16) & ~0xffff) == 0);
219 assert(num_tcs_input_cp <= 32);
220 assert(num_tcs_output_cp <= 32);
221
222 tcs_in_layout = S_VS_STATE_LS_OUT_PATCH_SIZE(input_patch_size / 4) |
223 S_VS_STATE_LS_OUT_VERTEX_SIZE(input_vertex_size / 4);
224 tcs_out_layout = (output_patch_size / 4) |
225 ((output_vertex_size / 4) << 13);
226 tcs_out_offsets = (output_patch0_offset / 16) |
227 ((perpatch_output_offset / 16) << 16);
228 offchip_layout = *num_patches |
229 (num_tcs_output_cp << 6) |
230 (pervertex_output_patch_size * *num_patches << 12);
231
232 /* Compute the LDS size. */
233 lds_size = output_patch0_offset + output_patch_size * *num_patches;
234
235 if (sctx->b.chip_class >= CIK) {
236 assert(lds_size <= 65536);
237 lds_size = align(lds_size, 512) / 512;
238 } else {
239 assert(lds_size <= 32768);
240 lds_size = align(lds_size, 256) / 256;
241 }
242
243 /* Set SI_SGPR_VS_STATE_BITS. */
244 sctx->current_vs_state &= C_VS_STATE_LS_OUT_PATCH_SIZE &
245 C_VS_STATE_LS_OUT_VERTEX_SIZE;
246 sctx->current_vs_state |= tcs_in_layout;
247
248 if (sctx->b.chip_class >= GFX9) {
249 unsigned hs_rsrc2 = ls_current->config.rsrc2 |
250 S_00B42C_LDS_SIZE(lds_size);
251
252 radeon_set_sh_reg(cs, R_00B42C_SPI_SHADER_PGM_RSRC2_HS, hs_rsrc2);
253
254 /* Set userdata SGPRs for merged LS-HS. */
255 radeon_set_sh_reg_seq(cs,
256 R_00B430_SPI_SHADER_USER_DATA_LS_0 +
257 GFX9_SGPR_TCS_OFFCHIP_LAYOUT * 4, 3);
258 radeon_emit(cs, offchip_layout);
259 radeon_emit(cs, tcs_out_offsets);
260 radeon_emit(cs, tcs_out_layout | (num_tcs_input_cp << 26));
261 } else {
262 unsigned ls_rsrc2 = ls_current->config.rsrc2;
263
264 si_multiwave_lds_size_workaround(sctx->screen, &lds_size);
265 ls_rsrc2 |= S_00B52C_LDS_SIZE(lds_size);
266
267 /* Due to a hw bug, RSRC2_LS must be written twice with another
268 * LS register written in between. */
269 if (sctx->b.chip_class == CIK && sctx->b.family != CHIP_HAWAII)
270 radeon_set_sh_reg(cs, R_00B52C_SPI_SHADER_PGM_RSRC2_LS, ls_rsrc2);
271 radeon_set_sh_reg_seq(cs, R_00B528_SPI_SHADER_PGM_RSRC1_LS, 2);
272 radeon_emit(cs, ls_current->config.rsrc1);
273 radeon_emit(cs, ls_rsrc2);
274
275 /* Set userdata SGPRs for TCS. */
276 radeon_set_sh_reg_seq(cs,
277 R_00B430_SPI_SHADER_USER_DATA_HS_0 + GFX6_SGPR_TCS_OFFCHIP_LAYOUT * 4, 4);
278 radeon_emit(cs, offchip_layout);
279 radeon_emit(cs, tcs_out_offsets);
280 radeon_emit(cs, tcs_out_layout | (num_tcs_input_cp << 26));
281 radeon_emit(cs, tcs_in_layout);
282 }
283
284 /* Set userdata SGPRs for TES. */
285 radeon_set_sh_reg_seq(cs, tes_sh_base + SI_SGPR_TES_OFFCHIP_LAYOUT * 4, 2);
286 radeon_emit(cs, offchip_layout);
287 radeon_emit(cs, r600_resource(sctx->tess_offchip_ring)->gpu_address >> 16);
288
289 ls_hs_config = S_028B58_NUM_PATCHES(*num_patches) |
290 S_028B58_HS_NUM_INPUT_CP(num_tcs_input_cp) |
291 S_028B58_HS_NUM_OUTPUT_CP(num_tcs_output_cp);
292
293 if (sctx->b.chip_class >= CIK)
294 radeon_set_context_reg_idx(cs, R_028B58_VGT_LS_HS_CONFIG, 2,
295 ls_hs_config);
296 else
297 radeon_set_context_reg(cs, R_028B58_VGT_LS_HS_CONFIG,
298 ls_hs_config);
299 }
300
301 static unsigned si_num_prims_for_vertices(const struct pipe_draw_info *info)
302 {
303 switch (info->mode) {
304 case PIPE_PRIM_PATCHES:
305 return info->count / info->vertices_per_patch;
306 case R600_PRIM_RECTANGLE_LIST:
307 return info->count / 3;
308 default:
309 return u_prims_for_vertices(info->mode, info->count);
310 }
311 }
312
313 static unsigned
314 si_get_init_multi_vgt_param(struct si_screen *sscreen,
315 union si_vgt_param_key *key)
316 {
317 STATIC_ASSERT(sizeof(union si_vgt_param_key) == 4);
318 unsigned max_primgroup_in_wave = 2;
319
320 /* SWITCH_ON_EOP(0) is always preferable. */
321 bool wd_switch_on_eop = false;
322 bool ia_switch_on_eop = false;
323 bool ia_switch_on_eoi = false;
324 bool partial_vs_wave = false;
325 bool partial_es_wave = false;
326
327 if (key->u.uses_tess) {
328 /* SWITCH_ON_EOI must be set if PrimID is used. */
329 if (key->u.tcs_tes_uses_prim_id)
330 ia_switch_on_eoi = true;
331
332 /* Bug with tessellation and GS on Bonaire and older 2 SE chips. */
333 if ((sscreen->b.family == CHIP_TAHITI ||
334 sscreen->b.family == CHIP_PITCAIRN ||
335 sscreen->b.family == CHIP_BONAIRE) &&
336 key->u.uses_gs)
337 partial_vs_wave = true;
338
339 /* Needed for 028B6C_DISTRIBUTION_MODE != 0 */
340 if (sscreen->has_distributed_tess) {
341 if (key->u.uses_gs) {
342 if (sscreen->b.chip_class <= VI)
343 partial_es_wave = true;
344
345 /* GPU hang workaround. */
346 if (sscreen->b.family == CHIP_TONGA ||
347 sscreen->b.family == CHIP_FIJI ||
348 sscreen->b.family == CHIP_POLARIS10 ||
349 sscreen->b.family == CHIP_POLARIS11 ||
350 sscreen->b.family == CHIP_POLARIS12)
351 partial_vs_wave = true;
352 } else {
353 partial_vs_wave = true;
354 }
355 }
356 }
357
358 /* This is a hardware requirement. */
359 if (key->u.line_stipple_enabled ||
360 (sscreen->b.debug_flags & DBG_SWITCH_ON_EOP)) {
361 ia_switch_on_eop = true;
362 wd_switch_on_eop = true;
363 }
364
365 if (sscreen->b.chip_class >= CIK) {
366 /* WD_SWITCH_ON_EOP has no effect on GPUs with less than
367 * 4 shader engines. Set 1 to pass the assertion below.
368 * The other cases are hardware requirements.
369 *
370 * Polaris supports primitive restart with WD_SWITCH_ON_EOP=0
371 * for points, line strips, and tri strips.
372 */
373 if (sscreen->b.info.max_se < 4 ||
374 key->u.prim == PIPE_PRIM_POLYGON ||
375 key->u.prim == PIPE_PRIM_LINE_LOOP ||
376 key->u.prim == PIPE_PRIM_TRIANGLE_FAN ||
377 key->u.prim == PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY ||
378 (key->u.primitive_restart &&
379 (sscreen->b.family < CHIP_POLARIS10 ||
380 (key->u.prim != PIPE_PRIM_POINTS &&
381 key->u.prim != PIPE_PRIM_LINE_STRIP &&
382 key->u.prim != PIPE_PRIM_TRIANGLE_STRIP))) ||
383 key->u.count_from_stream_output)
384 wd_switch_on_eop = true;
385
386 /* Hawaii hangs if instancing is enabled and WD_SWITCH_ON_EOP is 0.
387 * We don't know that for indirect drawing, so treat it as
388 * always problematic. */
389 if (sscreen->b.family == CHIP_HAWAII &&
390 key->u.uses_instancing)
391 wd_switch_on_eop = true;
392
393 /* Performance recommendation for 4 SE Gfx7-8 parts if
394 * instances are smaller than a primgroup.
395 * Assume indirect draws always use small instances.
396 * This is needed for good VS wave utilization.
397 */
398 if (sscreen->b.chip_class <= VI &&
399 sscreen->b.info.max_se == 4 &&
400 key->u.multi_instances_smaller_than_primgroup)
401 wd_switch_on_eop = true;
402
403 /* Required on CIK and later. */
404 if (sscreen->b.info.max_se > 2 && !wd_switch_on_eop)
405 ia_switch_on_eoi = true;
406
407 /* Required by Hawaii and, for some special cases, by VI. */
408 if (ia_switch_on_eoi &&
409 (sscreen->b.family == CHIP_HAWAII ||
410 (sscreen->b.chip_class == VI &&
411 (key->u.uses_gs || max_primgroup_in_wave != 2))))
412 partial_vs_wave = true;
413
414 /* Instancing bug on Bonaire. */
415 if (sscreen->b.family == CHIP_BONAIRE && ia_switch_on_eoi &&
416 key->u.uses_instancing)
417 partial_vs_wave = true;
418
419 /* If the WD switch is false, the IA switch must be false too. */
420 assert(wd_switch_on_eop || !ia_switch_on_eop);
421 }
422
423 /* If SWITCH_ON_EOI is set, PARTIAL_ES_WAVE must be set too. */
424 if (sscreen->b.chip_class <= VI && ia_switch_on_eoi)
425 partial_es_wave = true;
426
427 return S_028AA8_SWITCH_ON_EOP(ia_switch_on_eop) |
428 S_028AA8_SWITCH_ON_EOI(ia_switch_on_eoi) |
429 S_028AA8_PARTIAL_VS_WAVE_ON(partial_vs_wave) |
430 S_028AA8_PARTIAL_ES_WAVE_ON(partial_es_wave) |
431 S_028AA8_WD_SWITCH_ON_EOP(sscreen->b.chip_class >= CIK ? wd_switch_on_eop : 0) |
432 /* The following field was moved to VGT_SHADER_STAGES_EN in GFX9. */
433 S_028AA8_MAX_PRIMGRP_IN_WAVE(sscreen->b.chip_class == VI ?
434 max_primgroup_in_wave : 0) |
435 S_030960_EN_INST_OPT_BASIC(sscreen->b.chip_class >= GFX9) |
436 S_030960_EN_INST_OPT_ADV(sscreen->b.chip_class >= GFX9);
437 }
438
439 void si_init_ia_multi_vgt_param_table(struct si_context *sctx)
440 {
441 for (int prim = 0; prim <= R600_PRIM_RECTANGLE_LIST; prim++)
442 for (int uses_instancing = 0; uses_instancing < 2; uses_instancing++)
443 for (int multi_instances = 0; multi_instances < 2; multi_instances++)
444 for (int primitive_restart = 0; primitive_restart < 2; primitive_restart++)
445 for (int count_from_so = 0; count_from_so < 2; count_from_so++)
446 for (int line_stipple = 0; line_stipple < 2; line_stipple++)
447 for (int uses_tess = 0; uses_tess < 2; uses_tess++)
448 for (int tess_uses_primid = 0; tess_uses_primid < 2; tess_uses_primid++)
449 for (int uses_gs = 0; uses_gs < 2; uses_gs++) {
450 union si_vgt_param_key key;
451
452 key.index = 0;
453 key.u.prim = prim;
454 key.u.uses_instancing = uses_instancing;
455 key.u.multi_instances_smaller_than_primgroup = multi_instances;
456 key.u.primitive_restart = primitive_restart;
457 key.u.count_from_stream_output = count_from_so;
458 key.u.line_stipple_enabled = line_stipple;
459 key.u.uses_tess = uses_tess;
460 key.u.tcs_tes_uses_prim_id = tess_uses_primid;
461 key.u.uses_gs = uses_gs;
462
463 sctx->ia_multi_vgt_param[key.index] =
464 si_get_init_multi_vgt_param(sctx->screen, &key);
465 }
466 }
467
468 static unsigned si_get_ia_multi_vgt_param(struct si_context *sctx,
469 const struct pipe_draw_info *info,
470 unsigned num_patches)
471 {
472 union si_vgt_param_key key = sctx->ia_multi_vgt_param_key;
473 unsigned primgroup_size;
474 unsigned ia_multi_vgt_param;
475
476 if (sctx->tes_shader.cso) {
477 primgroup_size = num_patches; /* must be a multiple of NUM_PATCHES */
478 } else if (sctx->gs_shader.cso) {
479 primgroup_size = 64; /* recommended with a GS */
480 } else {
481 primgroup_size = 128; /* recommended without a GS and tess */
482 }
483
484 key.u.prim = info->mode;
485 key.u.uses_instancing = info->indirect || info->instance_count > 1;
486 key.u.multi_instances_smaller_than_primgroup =
487 info->indirect ||
488 (info->instance_count > 1 &&
489 (info->count_from_stream_output ||
490 si_num_prims_for_vertices(info) < primgroup_size));
491 key.u.primitive_restart = info->primitive_restart;
492 key.u.count_from_stream_output = info->count_from_stream_output != NULL;
493
494 ia_multi_vgt_param = sctx->ia_multi_vgt_param[key.index] |
495 S_028AA8_PRIMGROUP_SIZE(primgroup_size - 1);
496
497 if (sctx->gs_shader.cso) {
498 /* GS requirement. */
499 if (sctx->b.chip_class <= VI &&
500 SI_GS_PER_ES / primgroup_size >= sctx->screen->gs_table_depth - 3)
501 ia_multi_vgt_param |= S_028AA8_PARTIAL_ES_WAVE_ON(1);
502
503 /* GS hw bug with single-primitive instances and SWITCH_ON_EOI.
504 * The hw doc says all multi-SE chips are affected, but Vulkan
505 * only applies it to Hawaii. Do what Vulkan does.
506 */
507 if (sctx->b.family == CHIP_HAWAII &&
508 G_028AA8_SWITCH_ON_EOI(ia_multi_vgt_param) &&
509 (info->indirect ||
510 (info->instance_count > 1 &&
511 (info->count_from_stream_output ||
512 si_num_prims_for_vertices(info) <= 1))))
513 sctx->b.flags |= SI_CONTEXT_VGT_FLUSH;
514 }
515
516 return ia_multi_vgt_param;
517 }
518
519 /* rast_prim is the primitive type after GS. */
520 static void si_emit_rasterizer_prim_state(struct si_context *sctx)
521 {
522 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
523 enum pipe_prim_type rast_prim = sctx->current_rast_prim;
524 struct si_state_rasterizer *rs = sctx->emitted.named.rasterizer;
525
526 /* Skip this if not rendering lines. */
527 if (rast_prim != PIPE_PRIM_LINES &&
528 rast_prim != PIPE_PRIM_LINE_LOOP &&
529 rast_prim != PIPE_PRIM_LINE_STRIP &&
530 rast_prim != PIPE_PRIM_LINES_ADJACENCY &&
531 rast_prim != PIPE_PRIM_LINE_STRIP_ADJACENCY)
532 return;
533
534 if (rast_prim == sctx->last_rast_prim &&
535 rs->pa_sc_line_stipple == sctx->last_sc_line_stipple)
536 return;
537
538 /* For lines, reset the stipple pattern at each primitive. Otherwise,
539 * reset the stipple pattern at each packet (line strips, line loops).
540 */
541 radeon_set_context_reg(cs, R_028A0C_PA_SC_LINE_STIPPLE,
542 rs->pa_sc_line_stipple |
543 S_028A0C_AUTO_RESET_CNTL(rast_prim == PIPE_PRIM_LINES ? 1 : 2));
544
545 sctx->last_rast_prim = rast_prim;
546 sctx->last_sc_line_stipple = rs->pa_sc_line_stipple;
547 }
548
549 static void si_emit_vs_state(struct si_context *sctx,
550 const struct pipe_draw_info *info)
551 {
552 sctx->current_vs_state &= C_VS_STATE_INDEXED;
553 sctx->current_vs_state |= S_VS_STATE_INDEXED(!!info->indexed);
554
555 if (sctx->current_vs_state != sctx->last_vs_state) {
556 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
557
558 radeon_set_sh_reg(cs,
559 sctx->shader_userdata.sh_base[PIPE_SHADER_VERTEX] +
560 SI_SGPR_VS_STATE_BITS * 4,
561 sctx->current_vs_state);
562
563 sctx->last_vs_state = sctx->current_vs_state;
564 }
565 }
566
567 static void si_emit_draw_registers(struct si_context *sctx,
568 const struct pipe_draw_info *info,
569 unsigned num_patches)
570 {
571 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
572 unsigned prim = si_conv_pipe_prim(info->mode);
573 unsigned gs_out_prim = si_conv_prim_to_gs_out(sctx->current_rast_prim);
574 unsigned ia_multi_vgt_param;
575
576 ia_multi_vgt_param = si_get_ia_multi_vgt_param(sctx, info, num_patches);
577
578 /* Draw state. */
579 if (ia_multi_vgt_param != sctx->last_multi_vgt_param) {
580 if (sctx->b.chip_class >= GFX9)
581 radeon_set_uconfig_reg_idx(cs, R_030960_IA_MULTI_VGT_PARAM, 4, ia_multi_vgt_param);
582 else if (sctx->b.chip_class >= CIK)
583 radeon_set_context_reg_idx(cs, R_028AA8_IA_MULTI_VGT_PARAM, 1, ia_multi_vgt_param);
584 else
585 radeon_set_context_reg(cs, R_028AA8_IA_MULTI_VGT_PARAM, ia_multi_vgt_param);
586
587 sctx->last_multi_vgt_param = ia_multi_vgt_param;
588 }
589 if (prim != sctx->last_prim) {
590 if (sctx->b.chip_class >= CIK)
591 radeon_set_uconfig_reg_idx(cs, R_030908_VGT_PRIMITIVE_TYPE, 1, prim);
592 else
593 radeon_set_config_reg(cs, R_008958_VGT_PRIMITIVE_TYPE, prim);
594
595 sctx->last_prim = prim;
596 }
597
598 if (gs_out_prim != sctx->last_gs_out_prim) {
599 radeon_set_context_reg(cs, R_028A6C_VGT_GS_OUT_PRIM_TYPE, gs_out_prim);
600 sctx->last_gs_out_prim = gs_out_prim;
601 }
602
603 /* Primitive restart. */
604 if (info->primitive_restart != sctx->last_primitive_restart_en) {
605 if (sctx->b.chip_class >= GFX9)
606 radeon_set_uconfig_reg(cs, R_03092C_VGT_MULTI_PRIM_IB_RESET_EN,
607 info->primitive_restart);
608 else
609 radeon_set_context_reg(cs, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN,
610 info->primitive_restart);
611
612 sctx->last_primitive_restart_en = info->primitive_restart;
613
614 }
615 if (info->primitive_restart &&
616 (info->restart_index != sctx->last_restart_index ||
617 sctx->last_restart_index == SI_RESTART_INDEX_UNKNOWN)) {
618 radeon_set_context_reg(cs, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
619 info->restart_index);
620 sctx->last_restart_index = info->restart_index;
621 }
622 }
623
624 static void si_emit_draw_packets(struct si_context *sctx,
625 const struct pipe_draw_info *info,
626 const struct pipe_index_buffer *ib)
627 {
628 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
629 unsigned sh_base_reg = sctx->shader_userdata.sh_base[PIPE_SHADER_VERTEX];
630 bool render_cond_bit = sctx->b.render_cond && !sctx->b.render_cond_force_off;
631 uint32_t index_max_size = 0;
632 uint64_t index_va = 0;
633
634 if (info->count_from_stream_output) {
635 struct r600_so_target *t =
636 (struct r600_so_target*)info->count_from_stream_output;
637 uint64_t va = t->buf_filled_size->gpu_address +
638 t->buf_filled_size_offset;
639
640 radeon_set_context_reg(cs, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE,
641 t->stride_in_dw);
642
643 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
644 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
645 COPY_DATA_DST_SEL(COPY_DATA_REG) |
646 COPY_DATA_WR_CONFIRM);
647 radeon_emit(cs, va); /* src address lo */
648 radeon_emit(cs, va >> 32); /* src address hi */
649 radeon_emit(cs, R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE >> 2);
650 radeon_emit(cs, 0); /* unused */
651
652 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
653 t->buf_filled_size, RADEON_USAGE_READ,
654 RADEON_PRIO_SO_FILLED_SIZE);
655 }
656
657 /* draw packet */
658 if (info->indexed) {
659 if (ib->index_size != sctx->last_index_size) {
660 unsigned index_type;
661
662 /* index type */
663 switch (ib->index_size) {
664 case 1:
665 index_type = V_028A7C_VGT_INDEX_8;
666 break;
667 case 2:
668 index_type = V_028A7C_VGT_INDEX_16 |
669 (SI_BIG_ENDIAN && sctx->b.chip_class <= CIK ?
670 V_028A7C_VGT_DMA_SWAP_16_BIT : 0);
671 break;
672 case 4:
673 index_type = V_028A7C_VGT_INDEX_32 |
674 (SI_BIG_ENDIAN && sctx->b.chip_class <= CIK ?
675 V_028A7C_VGT_DMA_SWAP_32_BIT : 0);
676 break;
677 default:
678 assert(!"unreachable");
679 return;
680 }
681
682 if (sctx->b.chip_class >= GFX9) {
683 radeon_set_uconfig_reg_idx(cs, R_03090C_VGT_INDEX_TYPE,
684 2, index_type);
685 } else {
686 radeon_emit(cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
687 radeon_emit(cs, index_type);
688 }
689
690 sctx->last_index_size = ib->index_size;
691 }
692
693 index_max_size = (ib->buffer->width0 - ib->offset) /
694 ib->index_size;
695 index_va = r600_resource(ib->buffer)->gpu_address + ib->offset;
696
697 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
698 (struct r600_resource *)ib->buffer,
699 RADEON_USAGE_READ, RADEON_PRIO_INDEX_BUFFER);
700 } else {
701 /* On CI and later, non-indexed draws overwrite VGT_INDEX_TYPE,
702 * so the state must be re-emitted before the next indexed draw.
703 */
704 if (sctx->b.chip_class >= CIK)
705 sctx->last_index_size = -1;
706 }
707
708 if (info->indirect) {
709 uint64_t indirect_va = r600_resource(info->indirect)->gpu_address;
710
711 assert(indirect_va % 8 == 0);
712
713 si_invalidate_draw_sh_constants(sctx);
714
715 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
716 radeon_emit(cs, 1);
717 radeon_emit(cs, indirect_va);
718 radeon_emit(cs, indirect_va >> 32);
719
720 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
721 (struct r600_resource *)info->indirect,
722 RADEON_USAGE_READ, RADEON_PRIO_DRAW_INDIRECT);
723
724 unsigned di_src_sel = info->indexed ? V_0287F0_DI_SRC_SEL_DMA
725 : V_0287F0_DI_SRC_SEL_AUTO_INDEX;
726
727 assert(info->indirect_offset % 4 == 0);
728
729 if (info->indexed) {
730 radeon_emit(cs, PKT3(PKT3_INDEX_BASE, 1, 0));
731 radeon_emit(cs, index_va);
732 radeon_emit(cs, index_va >> 32);
733
734 radeon_emit(cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
735 radeon_emit(cs, index_max_size);
736 }
737
738 if (!sctx->screen->has_draw_indirect_multi) {
739 radeon_emit(cs, PKT3(info->indexed ? PKT3_DRAW_INDEX_INDIRECT
740 : PKT3_DRAW_INDIRECT,
741 3, render_cond_bit));
742 radeon_emit(cs, info->indirect_offset);
743 radeon_emit(cs, (sh_base_reg + SI_SGPR_BASE_VERTEX * 4 - SI_SH_REG_OFFSET) >> 2);
744 radeon_emit(cs, (sh_base_reg + SI_SGPR_START_INSTANCE * 4 - SI_SH_REG_OFFSET) >> 2);
745 radeon_emit(cs, di_src_sel);
746 } else {
747 uint64_t count_va = 0;
748
749 if (info->indirect_params) {
750 struct r600_resource *params_buf =
751 (struct r600_resource *)info->indirect_params;
752
753 radeon_add_to_buffer_list(
754 &sctx->b, &sctx->b.gfx, params_buf,
755 RADEON_USAGE_READ, RADEON_PRIO_DRAW_INDIRECT);
756
757 count_va = params_buf->gpu_address + info->indirect_params_offset;
758 }
759
760 radeon_emit(cs, PKT3(info->indexed ? PKT3_DRAW_INDEX_INDIRECT_MULTI :
761 PKT3_DRAW_INDIRECT_MULTI,
762 8, render_cond_bit));
763 radeon_emit(cs, info->indirect_offset);
764 radeon_emit(cs, (sh_base_reg + SI_SGPR_BASE_VERTEX * 4 - SI_SH_REG_OFFSET) >> 2);
765 radeon_emit(cs, (sh_base_reg + SI_SGPR_START_INSTANCE * 4 - SI_SH_REG_OFFSET) >> 2);
766 radeon_emit(cs, ((sh_base_reg + SI_SGPR_DRAWID * 4 - SI_SH_REG_OFFSET) >> 2) |
767 S_2C3_DRAW_INDEX_ENABLE(1) |
768 S_2C3_COUNT_INDIRECT_ENABLE(!!info->indirect_params));
769 radeon_emit(cs, info->indirect_count);
770 radeon_emit(cs, count_va);
771 radeon_emit(cs, count_va >> 32);
772 radeon_emit(cs, info->indirect_stride);
773 radeon_emit(cs, di_src_sel);
774 }
775 } else {
776 int base_vertex;
777
778 radeon_emit(cs, PKT3(PKT3_NUM_INSTANCES, 0, 0));
779 radeon_emit(cs, info->instance_count);
780
781 /* Base vertex and start instance. */
782 base_vertex = info->indexed ? info->index_bias : info->start;
783
784 if (base_vertex != sctx->last_base_vertex ||
785 sctx->last_base_vertex == SI_BASE_VERTEX_UNKNOWN ||
786 info->start_instance != sctx->last_start_instance ||
787 info->drawid != sctx->last_drawid ||
788 sh_base_reg != sctx->last_sh_base_reg) {
789 radeon_set_sh_reg_seq(cs, sh_base_reg + SI_SGPR_BASE_VERTEX * 4, 3);
790 radeon_emit(cs, base_vertex);
791 radeon_emit(cs, info->start_instance);
792 radeon_emit(cs, info->drawid);
793
794 sctx->last_base_vertex = base_vertex;
795 sctx->last_start_instance = info->start_instance;
796 sctx->last_drawid = info->drawid;
797 sctx->last_sh_base_reg = sh_base_reg;
798 }
799
800 if (info->indexed) {
801 index_va += info->start * ib->index_size;
802
803 radeon_emit(cs, PKT3(PKT3_DRAW_INDEX_2, 4, render_cond_bit));
804 radeon_emit(cs, index_max_size);
805 radeon_emit(cs, index_va);
806 radeon_emit(cs, index_va >> 32);
807 radeon_emit(cs, info->count);
808 radeon_emit(cs, V_0287F0_DI_SRC_SEL_DMA);
809 } else {
810 radeon_emit(cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, render_cond_bit));
811 radeon_emit(cs, info->count);
812 radeon_emit(cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
813 S_0287F0_USE_OPAQUE(!!info->count_from_stream_output));
814 }
815 }
816 }
817
818 static void si_emit_surface_sync(struct r600_common_context *rctx,
819 unsigned cp_coher_cntl)
820 {
821 struct radeon_winsys_cs *cs = rctx->gfx.cs;
822
823 if (rctx->chip_class >= GFX9) {
824 /* Flush caches and wait for the caches to assert idle. */
825 radeon_emit(cs, PKT3(PKT3_ACQUIRE_MEM, 5, 0));
826 radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */
827 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
828 radeon_emit(cs, 0xffffff); /* CP_COHER_SIZE_HI */
829 radeon_emit(cs, 0); /* CP_COHER_BASE */
830 radeon_emit(cs, 0); /* CP_COHER_BASE_HI */
831 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
832 } else {
833 /* ACQUIRE_MEM is only required on a compute ring. */
834 radeon_emit(cs, PKT3(PKT3_SURFACE_SYNC, 3, 0));
835 radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */
836 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
837 radeon_emit(cs, 0); /* CP_COHER_BASE */
838 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
839 }
840 }
841
842 void si_emit_cache_flush(struct si_context *sctx)
843 {
844 struct r600_common_context *rctx = &sctx->b;
845 struct radeon_winsys_cs *cs = rctx->gfx.cs;
846 uint32_t cp_coher_cntl = 0;
847 uint32_t flush_cb_db = rctx->flags & (SI_CONTEXT_FLUSH_AND_INV_CB |
848 SI_CONTEXT_FLUSH_AND_INV_DB);
849
850 if (rctx->flags & (SI_CONTEXT_FLUSH_AND_INV_CB |
851 SI_CONTEXT_FLUSH_AND_INV_DB))
852 sctx->b.num_fb_cache_flushes++;
853
854 /* SI has a bug that it always flushes ICACHE and KCACHE if either
855 * bit is set. An alternative way is to write SQC_CACHES, but that
856 * doesn't seem to work reliably. Since the bug doesn't affect
857 * correctness (it only does more work than necessary) and
858 * the performance impact is likely negligible, there is no plan
859 * to add a workaround for it.
860 */
861
862 if (rctx->flags & SI_CONTEXT_INV_ICACHE)
863 cp_coher_cntl |= S_0085F0_SH_ICACHE_ACTION_ENA(1);
864 if (rctx->flags & SI_CONTEXT_INV_SMEM_L1)
865 cp_coher_cntl |= S_0085F0_SH_KCACHE_ACTION_ENA(1);
866
867 if (rctx->chip_class <= VI) {
868 if (rctx->flags & SI_CONTEXT_FLUSH_AND_INV_CB) {
869 cp_coher_cntl |= S_0085F0_CB_ACTION_ENA(1) |
870 S_0085F0_CB0_DEST_BASE_ENA(1) |
871 S_0085F0_CB1_DEST_BASE_ENA(1) |
872 S_0085F0_CB2_DEST_BASE_ENA(1) |
873 S_0085F0_CB3_DEST_BASE_ENA(1) |
874 S_0085F0_CB4_DEST_BASE_ENA(1) |
875 S_0085F0_CB5_DEST_BASE_ENA(1) |
876 S_0085F0_CB6_DEST_BASE_ENA(1) |
877 S_0085F0_CB7_DEST_BASE_ENA(1);
878
879 /* Necessary for DCC */
880 if (rctx->chip_class == VI)
881 r600_gfx_write_event_eop(rctx, V_028A90_FLUSH_AND_INV_CB_DATA_TS,
882 0, 0, NULL, 0, 0, 0);
883 }
884 if (rctx->flags & SI_CONTEXT_FLUSH_AND_INV_DB)
885 cp_coher_cntl |= S_0085F0_DB_ACTION_ENA(1) |
886 S_0085F0_DB_DEST_BASE_ENA(1);
887 }
888
889 if (rctx->flags & SI_CONTEXT_FLUSH_AND_INV_CB) {
890 /* Flush CMASK/FMASK/DCC. SURFACE_SYNC will wait for idle. */
891 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
892 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_META) | EVENT_INDEX(0));
893 }
894 if (rctx->flags & SI_CONTEXT_FLUSH_AND_INV_DB) {
895 /* Flush HTILE. SURFACE_SYNC will wait for idle. */
896 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
897 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_DB_META) | EVENT_INDEX(0));
898 }
899
900 /* Wait for shader engines to go idle.
901 * VS and PS waits are unnecessary if SURFACE_SYNC is going to wait
902 * for everything including CB/DB cache flushes.
903 */
904 if (!flush_cb_db) {
905 if (rctx->flags & SI_CONTEXT_PS_PARTIAL_FLUSH) {
906 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
907 radeon_emit(cs, EVENT_TYPE(V_028A90_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
908 /* Only count explicit shader flushes, not implicit ones
909 * done by SURFACE_SYNC.
910 */
911 rctx->num_vs_flushes++;
912 rctx->num_ps_flushes++;
913 } else if (rctx->flags & SI_CONTEXT_VS_PARTIAL_FLUSH) {
914 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
915 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
916 rctx->num_vs_flushes++;
917 }
918 }
919
920 if (rctx->flags & SI_CONTEXT_CS_PARTIAL_FLUSH &&
921 sctx->compute_is_busy) {
922 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
923 radeon_emit(cs, EVENT_TYPE(V_028A90_CS_PARTIAL_FLUSH | EVENT_INDEX(4)));
924 rctx->num_cs_flushes++;
925 sctx->compute_is_busy = false;
926 }
927
928 /* VGT state synchronization. */
929 if (rctx->flags & SI_CONTEXT_VGT_FLUSH) {
930 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
931 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
932 }
933 if (rctx->flags & SI_CONTEXT_VGT_STREAMOUT_SYNC) {
934 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
935 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_STREAMOUT_SYNC) | EVENT_INDEX(0));
936 }
937
938 /* GFX9: Wait for idle if we're flushing CB or DB. ACQUIRE_MEM doesn't
939 * wait for idle on GFX9. We have to use a TS event.
940 */
941 if (sctx->b.chip_class >= GFX9 && flush_cb_db) {
942 struct r600_resource *rbuf = NULL;
943 uint64_t va;
944 unsigned offset = 0, tc_flags, cb_db_event;
945
946 /* Set the CB/DB flush event. */
947 switch (flush_cb_db) {
948 case SI_CONTEXT_FLUSH_AND_INV_CB:
949 cb_db_event = V_028A90_FLUSH_AND_INV_CB_DATA_TS;
950 break;
951 case SI_CONTEXT_FLUSH_AND_INV_DB:
952 cb_db_event = V_028A90_FLUSH_AND_INV_DB_DATA_TS;
953 break;
954 default:
955 /* both CB & DB */
956 cb_db_event = V_028A90_CACHE_FLUSH_AND_INV_TS_EVENT;
957 }
958
959 /* TC | TC_WB = invalidate L2 data
960 * TC_MD | TC_WB = invalidate L2 metadata
961 * TC | TC_WB | TC_MD = invalidate L2 data & metadata
962 *
963 * The metadata cache must always be invalidated for coherency
964 * between CB/DB and shaders. (metadata = HTILE, CMASK, DCC)
965 *
966 * TC must be invalidated on GFX9 only if the CB/DB surface is
967 * not pipe-aligned. If the surface is RB-aligned, it might not
968 * strictly be pipe-aligned since RB alignment takes precendence.
969 */
970 tc_flags = EVENT_TC_WB_ACTION_ENA |
971 EVENT_TC_MD_ACTION_ENA;
972
973 /* Ideally flush TC together with CB/DB. */
974 if (rctx->flags & SI_CONTEXT_INV_GLOBAL_L2) {
975 tc_flags |= EVENT_TC_ACTION_ENA |
976 EVENT_TCL1_ACTION_ENA;
977
978 /* Clear the flags. */
979 rctx->flags &= ~(SI_CONTEXT_INV_GLOBAL_L2 |
980 SI_CONTEXT_WRITEBACK_GLOBAL_L2 |
981 SI_CONTEXT_INV_VMEM_L1);
982 }
983
984 /* Allocate memory for the fence. */
985 u_suballocator_alloc(rctx->allocator_zeroed_memory, 4, 4,
986 &offset, (struct pipe_resource**)&rbuf);
987 va = rbuf->gpu_address + offset;
988
989 r600_gfx_write_event_eop(rctx, cb_db_event, tc_flags, 1,
990 rbuf, va, 0, 1);
991 r600_gfx_wait_fence(rctx, va, 1, 0xffffffff);
992 }
993
994 /* Make sure ME is idle (it executes most packets) before continuing.
995 * This prevents read-after-write hazards between PFP and ME.
996 */
997 if (cp_coher_cntl ||
998 (rctx->flags & (SI_CONTEXT_CS_PARTIAL_FLUSH |
999 SI_CONTEXT_INV_VMEM_L1 |
1000 SI_CONTEXT_INV_GLOBAL_L2 |
1001 SI_CONTEXT_WRITEBACK_GLOBAL_L2))) {
1002 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1003 radeon_emit(cs, 0);
1004 }
1005
1006 /* SI-CI-VI only:
1007 * When one of the CP_COHER_CNTL.DEST_BASE flags is set, SURFACE_SYNC
1008 * waits for idle, so it should be last. SURFACE_SYNC is done in PFP.
1009 *
1010 * cp_coher_cntl should contain all necessary flags except TC flags
1011 * at this point.
1012 *
1013 * SI-CIK don't support L2 write-back.
1014 */
1015 if (rctx->flags & SI_CONTEXT_INV_GLOBAL_L2 ||
1016 (rctx->chip_class <= CIK &&
1017 (rctx->flags & SI_CONTEXT_WRITEBACK_GLOBAL_L2))) {
1018 /* Invalidate L1 & L2. (L1 is always invalidated on SI)
1019 * WB must be set on VI+ when TC_ACTION is set.
1020 */
1021 si_emit_surface_sync(rctx, cp_coher_cntl |
1022 S_0085F0_TC_ACTION_ENA(1) |
1023 S_0085F0_TCL1_ACTION_ENA(1) |
1024 S_0301F0_TC_WB_ACTION_ENA(rctx->chip_class >= VI));
1025 cp_coher_cntl = 0;
1026 sctx->b.num_L2_invalidates++;
1027 } else {
1028 /* L1 invalidation and L2 writeback must be done separately,
1029 * because both operations can't be done together.
1030 */
1031 if (rctx->flags & SI_CONTEXT_WRITEBACK_GLOBAL_L2) {
1032 /* WB = write-back
1033 * NC = apply to non-coherent MTYPEs
1034 * (i.e. MTYPE <= 1, which is what we use everywhere)
1035 *
1036 * WB doesn't work without NC.
1037 */
1038 si_emit_surface_sync(rctx, cp_coher_cntl |
1039 S_0301F0_TC_WB_ACTION_ENA(1) |
1040 S_0301F0_TC_NC_ACTION_ENA(1));
1041 cp_coher_cntl = 0;
1042 sctx->b.num_L2_writebacks++;
1043 }
1044 if (rctx->flags & SI_CONTEXT_INV_VMEM_L1) {
1045 /* Invalidate per-CU VMEM L1. */
1046 si_emit_surface_sync(rctx, cp_coher_cntl |
1047 S_0085F0_TCL1_ACTION_ENA(1));
1048 cp_coher_cntl = 0;
1049 }
1050 }
1051
1052 /* If TC flushes haven't cleared this... */
1053 if (cp_coher_cntl)
1054 si_emit_surface_sync(rctx, cp_coher_cntl);
1055
1056 if (rctx->flags & R600_CONTEXT_START_PIPELINE_STATS) {
1057 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1058 radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_START) |
1059 EVENT_INDEX(0));
1060 } else if (rctx->flags & R600_CONTEXT_STOP_PIPELINE_STATS) {
1061 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1062 radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_STOP) |
1063 EVENT_INDEX(0));
1064 }
1065
1066 rctx->flags = 0;
1067 }
1068
1069 static void si_get_draw_start_count(struct si_context *sctx,
1070 const struct pipe_draw_info *info,
1071 unsigned *start, unsigned *count)
1072 {
1073 if (info->indirect) {
1074 unsigned indirect_count;
1075 struct pipe_transfer *transfer;
1076 unsigned begin, end;
1077 unsigned map_size;
1078 unsigned *data;
1079
1080 if (info->indirect_params) {
1081 data = pipe_buffer_map_range(&sctx->b.b,
1082 info->indirect_params,
1083 info->indirect_params_offset,
1084 sizeof(unsigned),
1085 PIPE_TRANSFER_READ, &transfer);
1086
1087 indirect_count = *data;
1088
1089 pipe_buffer_unmap(&sctx->b.b, transfer);
1090 } else {
1091 indirect_count = info->indirect_count;
1092 }
1093
1094 if (!indirect_count) {
1095 *start = *count = 0;
1096 return;
1097 }
1098
1099 map_size = (indirect_count - 1) * info->indirect_stride + 3 * sizeof(unsigned);
1100 data = pipe_buffer_map_range(&sctx->b.b, info->indirect,
1101 info->indirect_offset, map_size,
1102 PIPE_TRANSFER_READ, &transfer);
1103
1104 begin = UINT_MAX;
1105 end = 0;
1106
1107 for (unsigned i = 0; i < indirect_count; ++i) {
1108 unsigned count = data[0];
1109 unsigned start = data[2];
1110
1111 if (count > 0) {
1112 begin = MIN2(begin, start);
1113 end = MAX2(end, start + count);
1114 }
1115
1116 data += info->indirect_stride / sizeof(unsigned);
1117 }
1118
1119 pipe_buffer_unmap(&sctx->b.b, transfer);
1120
1121 if (begin < end) {
1122 *start = begin;
1123 *count = end - begin;
1124 } else {
1125 *start = *count = 0;
1126 }
1127 } else {
1128 *start = info->start;
1129 *count = info->count;
1130 }
1131 }
1132
1133 void si_ce_pre_draw_synchronization(struct si_context *sctx)
1134 {
1135 if (sctx->ce_need_synchronization) {
1136 radeon_emit(sctx->ce_ib, PKT3(PKT3_INCREMENT_CE_COUNTER, 0, 0));
1137 radeon_emit(sctx->ce_ib, 1);
1138
1139 radeon_emit(sctx->b.gfx.cs, PKT3(PKT3_WAIT_ON_CE_COUNTER, 0, 0));
1140 radeon_emit(sctx->b.gfx.cs, 1);
1141 }
1142 }
1143
1144 void si_ce_post_draw_synchronization(struct si_context *sctx)
1145 {
1146 if (sctx->ce_need_synchronization) {
1147 radeon_emit(sctx->b.gfx.cs, PKT3(PKT3_INCREMENT_DE_COUNTER, 0, 0));
1148 radeon_emit(sctx->b.gfx.cs, 0);
1149
1150 sctx->ce_need_synchronization = false;
1151 }
1152 }
1153
1154 void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info)
1155 {
1156 struct si_context *sctx = (struct si_context *)ctx;
1157 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
1158 const struct pipe_index_buffer *ib = &sctx->index_buffer;
1159 struct pipe_index_buffer ib_tmp; /* for index buffer uploads only */
1160 unsigned mask, dirty_tex_counter;
1161 enum pipe_prim_type rast_prim;
1162 unsigned num_patches = 0;
1163
1164 if (likely(!info->indirect)) {
1165 /* SI-CI treat instance_count==0 as instance_count==1. There is
1166 * no workaround for indirect draws, but we can at least skip
1167 * direct draws.
1168 */
1169 if (unlikely(!info->instance_count))
1170 return;
1171
1172 /* Handle count == 0. */
1173 if (unlikely(!info->count &&
1174 (info->indexed || !info->count_from_stream_output)))
1175 return;
1176 }
1177
1178 if (unlikely(!sctx->vs_shader.cso)) {
1179 assert(0);
1180 return;
1181 }
1182 if (unlikely(!sctx->ps_shader.cso && (!rs || !rs->rasterizer_discard))) {
1183 assert(0);
1184 return;
1185 }
1186 if (unlikely(!!sctx->tes_shader.cso != (info->mode == PIPE_PRIM_PATCHES))) {
1187 assert(0);
1188 return;
1189 }
1190
1191 /* Recompute and re-emit the texture resource states if needed. */
1192 dirty_tex_counter = p_atomic_read(&sctx->b.screen->dirty_tex_counter);
1193 if (unlikely(dirty_tex_counter != sctx->b.last_dirty_tex_counter)) {
1194 sctx->b.last_dirty_tex_counter = dirty_tex_counter;
1195 sctx->framebuffer.dirty_cbufs |=
1196 ((1 << sctx->framebuffer.state.nr_cbufs) - 1);
1197 sctx->framebuffer.dirty_zsbuf = true;
1198 sctx->framebuffer.do_update_surf_dirtiness = true;
1199 si_mark_atom_dirty(sctx, &sctx->framebuffer.atom);
1200 si_update_all_texture_descriptors(sctx);
1201 }
1202
1203 si_decompress_graphics_textures(sctx);
1204
1205 /* Set the rasterization primitive type.
1206 *
1207 * This must be done after si_decompress_textures, which can call
1208 * draw_vbo recursively, and before si_update_shaders, which uses
1209 * current_rast_prim for this draw_vbo call. */
1210 if (sctx->gs_shader.cso)
1211 rast_prim = sctx->gs_shader.cso->gs_output_prim;
1212 else if (sctx->tes_shader.cso)
1213 rast_prim = sctx->tes_shader.cso->info.properties[TGSI_PROPERTY_TES_PRIM_MODE];
1214 else
1215 rast_prim = info->mode;
1216
1217 if (rast_prim != sctx->current_rast_prim) {
1218 sctx->current_rast_prim = rast_prim;
1219 sctx->do_update_shaders = true;
1220 }
1221
1222 if (sctx->gs_shader.cso) {
1223 /* Determine whether the GS triangle strip adjacency fix should
1224 * be applied. Rotate every other triangle if
1225 * - triangle strips with adjacency are fed to the GS and
1226 * - primitive restart is disabled (the rotation doesn't help
1227 * when the restart occurs after an odd number of triangles).
1228 */
1229 bool gs_tri_strip_adj_fix =
1230 !sctx->tes_shader.cso &&
1231 info->mode == PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY &&
1232 !info->primitive_restart;
1233
1234 if (gs_tri_strip_adj_fix != sctx->gs_tri_strip_adj_fix) {
1235 sctx->gs_tri_strip_adj_fix = gs_tri_strip_adj_fix;
1236 sctx->do_update_shaders = true;
1237 }
1238 }
1239
1240 if (sctx->do_update_shaders && !si_update_shaders(sctx))
1241 return;
1242
1243 if (!si_upload_graphics_shader_descriptors(sctx))
1244 return;
1245
1246 ib_tmp.buffer = NULL;
1247
1248 if (info->indexed) {
1249 /* Translate or upload, if needed. */
1250 /* 8-bit indices are supported on VI. */
1251 if (sctx->b.chip_class <= CIK && ib->index_size == 1) {
1252 unsigned start, count, start_offset, size;
1253 void *ptr;
1254
1255 si_get_draw_start_count(sctx, info, &start, &count);
1256 start_offset = start * 2;
1257 size = count * 2;
1258
1259 u_upload_alloc(ctx->stream_uploader, start_offset,
1260 size,
1261 si_optimal_tcc_alignment(sctx, size),
1262 &ib_tmp.offset, &ib_tmp.buffer, &ptr);
1263 if (!ib_tmp.buffer)
1264 return;
1265
1266 util_shorten_ubyte_elts_to_userptr(&sctx->b.b, ib, 0, 0,
1267 ib->offset + start,
1268 count, ptr);
1269
1270 /* info->start will be added by the drawing code */
1271 ib_tmp.offset -= start_offset;
1272 ib_tmp.index_size = 2;
1273 ib = &ib_tmp;
1274 } else if (ib->user_buffer && !ib->buffer) {
1275 unsigned start_offset;
1276
1277 assert(!info->indirect);
1278 start_offset = info->start * ib->index_size;
1279
1280 u_upload_data(ctx->stream_uploader, start_offset,
1281 info->count * ib->index_size,
1282 sctx->screen->b.info.tcc_cache_line_size,
1283 (char*)ib->user_buffer + start_offset,
1284 &ib_tmp.offset, &ib_tmp.buffer);
1285 if (!ib_tmp.buffer)
1286 return;
1287
1288 /* info->start will be added by the drawing code */
1289 ib_tmp.offset -= start_offset;
1290 ib_tmp.index_size = ib->index_size;
1291 ib = &ib_tmp;
1292 } else if (sctx->b.chip_class <= CIK &&
1293 r600_resource(ib->buffer)->TC_L2_dirty) {
1294 /* VI reads index buffers through TC L2, so it doesn't
1295 * need this. */
1296 sctx->b.flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
1297 r600_resource(ib->buffer)->TC_L2_dirty = false;
1298 }
1299 }
1300
1301 if (info->indirect) {
1302 /* Add the buffer size for memory checking in need_cs_space. */
1303 r600_context_add_resource_size(ctx, info->indirect);
1304
1305 if (r600_resource(info->indirect)->TC_L2_dirty) {
1306 sctx->b.flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
1307 r600_resource(info->indirect)->TC_L2_dirty = false;
1308 }
1309
1310 if (info->indirect_params &&
1311 r600_resource(info->indirect_params)->TC_L2_dirty) {
1312 sctx->b.flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
1313 r600_resource(info->indirect_params)->TC_L2_dirty = false;
1314 }
1315 }
1316
1317 si_need_cs_space(sctx);
1318
1319 /* Since we've called r600_context_add_resource_size for vertex buffers,
1320 * this must be called after si_need_cs_space, because we must let
1321 * need_cs_space flush before we add buffers to the buffer list.
1322 */
1323 if (!si_upload_vertex_buffer_descriptors(sctx))
1324 return;
1325
1326 /* GFX9 scissor bug workaround. There is also a more efficient but
1327 * more involved alternative workaround. */
1328 if (sctx->b.chip_class == GFX9 &&
1329 si_is_atom_dirty(sctx, &sctx->b.scissors.atom))
1330 sctx->b.flags |= SI_CONTEXT_PS_PARTIAL_FLUSH;
1331
1332 /* Flush caches before the first state atom, which does L2 prefetches. */
1333 if (sctx->b.flags)
1334 si_emit_cache_flush(sctx);
1335
1336 /* Emit state atoms. */
1337 mask = sctx->dirty_atoms;
1338 while (mask) {
1339 struct r600_atom *atom = sctx->atoms.array[u_bit_scan(&mask)];
1340
1341 atom->emit(&sctx->b, atom);
1342 }
1343 sctx->dirty_atoms = 0;
1344
1345 /* Emit states. */
1346 mask = sctx->dirty_states;
1347 while (mask) {
1348 unsigned i = u_bit_scan(&mask);
1349 struct si_pm4_state *state = sctx->queued.array[i];
1350
1351 if (!state || sctx->emitted.array[i] == state)
1352 continue;
1353
1354 si_pm4_emit(sctx, state);
1355 sctx->emitted.array[i] = state;
1356 }
1357 sctx->dirty_states = 0;
1358
1359 si_emit_rasterizer_prim_state(sctx);
1360 if (sctx->tes_shader.cso)
1361 si_emit_derived_tess_state(sctx, info, &num_patches);
1362 si_emit_vs_state(sctx, info);
1363 si_emit_draw_registers(sctx, info, num_patches);
1364
1365 si_ce_pre_draw_synchronization(sctx);
1366 si_emit_draw_packets(sctx, info, ib);
1367 si_ce_post_draw_synchronization(sctx);
1368
1369 if (sctx->trace_buf)
1370 si_trace_emit(sctx);
1371
1372 /* Workaround for a VGT hang when streamout is enabled.
1373 * It must be done after drawing. */
1374 if ((sctx->b.family == CHIP_HAWAII ||
1375 sctx->b.family == CHIP_TONGA ||
1376 sctx->b.family == CHIP_FIJI) &&
1377 r600_get_strmout_en(&sctx->b)) {
1378 sctx->b.flags |= SI_CONTEXT_VGT_STREAMOUT_SYNC;
1379 }
1380
1381 if (sctx->framebuffer.do_update_surf_dirtiness) {
1382 /* Set the depth buffer as dirty. */
1383 if (sctx->framebuffer.state.zsbuf) {
1384 struct pipe_surface *surf = sctx->framebuffer.state.zsbuf;
1385 struct r600_texture *rtex = (struct r600_texture *)surf->texture;
1386
1387 if (!rtex->tc_compatible_htile)
1388 rtex->dirty_level_mask |= 1 << surf->u.tex.level;
1389
1390 if (rtex->surface.flags & RADEON_SURF_SBUFFER)
1391 rtex->stencil_dirty_level_mask |= 1 << surf->u.tex.level;
1392 }
1393 if (sctx->framebuffer.compressed_cb_mask) {
1394 struct pipe_surface *surf;
1395 struct r600_texture *rtex;
1396 unsigned mask = sctx->framebuffer.compressed_cb_mask;
1397
1398 do {
1399 unsigned i = u_bit_scan(&mask);
1400 surf = sctx->framebuffer.state.cbufs[i];
1401 rtex = (struct r600_texture*)surf->texture;
1402
1403 if (rtex->fmask.size)
1404 rtex->dirty_level_mask |= 1 << surf->u.tex.level;
1405 if (rtex->dcc_gather_statistics)
1406 rtex->separate_dcc_dirty = true;
1407 } while (mask);
1408 }
1409 sctx->framebuffer.do_update_surf_dirtiness = false;
1410 }
1411
1412 pipe_resource_reference(&ib_tmp.buffer, NULL);
1413 sctx->b.num_draw_calls++;
1414 if (info->primitive_restart)
1415 sctx->b.num_prim_restart_calls++;
1416 if (G_0286E8_WAVESIZE(sctx->spi_tmpring_size))
1417 sctx->b.num_spill_draw_calls++;
1418 }
1419
1420 void si_trace_emit(struct si_context *sctx)
1421 {
1422 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
1423
1424 sctx->trace_id++;
1425 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, sctx->trace_buf,
1426 RADEON_USAGE_READWRITE, RADEON_PRIO_TRACE);
1427 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
1428 radeon_emit(cs, S_370_DST_SEL(V_370_MEMORY_SYNC) |
1429 S_370_WR_CONFIRM(1) |
1430 S_370_ENGINE_SEL(V_370_ME));
1431 radeon_emit(cs, sctx->trace_buf->gpu_address);
1432 radeon_emit(cs, sctx->trace_buf->gpu_address >> 32);
1433 radeon_emit(cs, sctx->trace_id);
1434 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1435 radeon_emit(cs, AC_ENCODE_TRACE_POINT(sctx->trace_id));
1436 }