2 * Copyright 2012 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 * Christian König <christian.koenig@amd.com>
28 #include "radeon/r600_cs.h"
32 #include "util/u_index_modify.h"
33 #include "util/u_upload_mgr.h"
34 #include "util/u_prim.h"
38 static unsigned si_conv_pipe_prim(unsigned mode
)
40 static const unsigned prim_conv
[] = {
41 [PIPE_PRIM_POINTS
] = V_008958_DI_PT_POINTLIST
,
42 [PIPE_PRIM_LINES
] = V_008958_DI_PT_LINELIST
,
43 [PIPE_PRIM_LINE_LOOP
] = V_008958_DI_PT_LINELOOP
,
44 [PIPE_PRIM_LINE_STRIP
] = V_008958_DI_PT_LINESTRIP
,
45 [PIPE_PRIM_TRIANGLES
] = V_008958_DI_PT_TRILIST
,
46 [PIPE_PRIM_TRIANGLE_STRIP
] = V_008958_DI_PT_TRISTRIP
,
47 [PIPE_PRIM_TRIANGLE_FAN
] = V_008958_DI_PT_TRIFAN
,
48 [PIPE_PRIM_QUADS
] = V_008958_DI_PT_QUADLIST
,
49 [PIPE_PRIM_QUAD_STRIP
] = V_008958_DI_PT_QUADSTRIP
,
50 [PIPE_PRIM_POLYGON
] = V_008958_DI_PT_POLYGON
,
51 [PIPE_PRIM_LINES_ADJACENCY
] = V_008958_DI_PT_LINELIST_ADJ
,
52 [PIPE_PRIM_LINE_STRIP_ADJACENCY
] = V_008958_DI_PT_LINESTRIP_ADJ
,
53 [PIPE_PRIM_TRIANGLES_ADJACENCY
] = V_008958_DI_PT_TRILIST_ADJ
,
54 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY
] = V_008958_DI_PT_TRISTRIP_ADJ
,
55 [PIPE_PRIM_PATCHES
] = V_008958_DI_PT_PATCH
,
56 [R600_PRIM_RECTANGLE_LIST
] = V_008958_DI_PT_RECTLIST
58 assert(mode
< ARRAY_SIZE(prim_conv
));
59 return prim_conv
[mode
];
62 static unsigned si_conv_prim_to_gs_out(unsigned mode
)
64 static const int prim_conv
[] = {
65 [PIPE_PRIM_POINTS
] = V_028A6C_OUTPRIM_TYPE_POINTLIST
,
66 [PIPE_PRIM_LINES
] = V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
67 [PIPE_PRIM_LINE_LOOP
] = V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
68 [PIPE_PRIM_LINE_STRIP
] = V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
69 [PIPE_PRIM_TRIANGLES
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
70 [PIPE_PRIM_TRIANGLE_STRIP
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
71 [PIPE_PRIM_TRIANGLE_FAN
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
72 [PIPE_PRIM_QUADS
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
73 [PIPE_PRIM_QUAD_STRIP
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
74 [PIPE_PRIM_POLYGON
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
75 [PIPE_PRIM_LINES_ADJACENCY
] = V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
76 [PIPE_PRIM_LINE_STRIP_ADJACENCY
] = V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
77 [PIPE_PRIM_TRIANGLES_ADJACENCY
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
78 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
79 [PIPE_PRIM_PATCHES
] = V_028A6C_OUTPRIM_TYPE_POINTLIST
,
80 [R600_PRIM_RECTANGLE_LIST
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
82 assert(mode
< ARRAY_SIZE(prim_conv
));
84 return prim_conv
[mode
];
88 * This calculates the LDS size for tessellation shaders (VS, TCS, TES).
89 * LS.LDS_SIZE is shared by all 3 shader stages.
91 * The information about LDS and other non-compile-time parameters is then
92 * written to userdata SGPRs.
94 static void si_emit_derived_tess_state(struct si_context
*sctx
,
95 const struct pipe_draw_info
*info
,
96 unsigned *num_patches
)
98 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
99 struct si_shader
*ls_current
;
100 struct si_shader_selector
*ls
;
101 /* The TES pointer will only be used for sctx->last_tcs.
102 * It would be wrong to think that TCS = TES. */
103 struct si_shader_selector
*tcs
=
104 sctx
->tcs_shader
.cso
? sctx
->tcs_shader
.cso
: sctx
->tes_shader
.cso
;
105 unsigned tes_sh_base
= sctx
->shader_userdata
.sh_base
[PIPE_SHADER_TESS_EVAL
];
106 unsigned num_tcs_input_cp
= info
->vertices_per_patch
;
107 unsigned num_tcs_output_cp
, num_tcs_inputs
, num_tcs_outputs
;
108 unsigned num_tcs_patch_outputs
;
109 unsigned input_vertex_size
, output_vertex_size
, pervertex_output_patch_size
;
110 unsigned input_patch_size
, output_patch_size
, output_patch0_offset
;
111 unsigned perpatch_output_offset
, lds_size
;
112 unsigned tcs_in_layout
, tcs_out_layout
, tcs_out_offsets
;
113 unsigned offchip_layout
, hardware_lds_size
, ls_hs_config
;
115 /* Since GFX9 has merged LS-HS in the TCS state, set LS = TCS. */
116 if (sctx
->b
.chip_class
>= GFX9
) {
117 if (sctx
->tcs_shader
.cso
)
118 ls_current
= sctx
->tcs_shader
.current
;
120 ls_current
= sctx
->fixed_func_tcs_shader
.current
;
122 ls
= ls_current
->key
.part
.tcs
.ls
;
124 ls_current
= sctx
->vs_shader
.current
;
125 ls
= sctx
->vs_shader
.cso
;
128 if (sctx
->last_ls
== ls_current
&&
129 sctx
->last_tcs
== tcs
&&
130 sctx
->last_tes_sh_base
== tes_sh_base
&&
131 sctx
->last_num_tcs_input_cp
== num_tcs_input_cp
) {
132 *num_patches
= sctx
->last_num_patches
;
136 sctx
->last_ls
= ls_current
;
137 sctx
->last_tcs
= tcs
;
138 sctx
->last_tes_sh_base
= tes_sh_base
;
139 sctx
->last_num_tcs_input_cp
= num_tcs_input_cp
;
141 /* This calculates how shader inputs and outputs among VS, TCS, and TES
142 * are laid out in LDS. */
143 num_tcs_inputs
= util_last_bit64(ls
->outputs_written
);
145 if (sctx
->tcs_shader
.cso
) {
146 num_tcs_outputs
= util_last_bit64(tcs
->outputs_written
);
147 num_tcs_output_cp
= tcs
->info
.properties
[TGSI_PROPERTY_TCS_VERTICES_OUT
];
148 num_tcs_patch_outputs
= util_last_bit64(tcs
->patch_outputs_written
);
150 /* No TCS. Route varyings from LS to TES. */
151 num_tcs_outputs
= num_tcs_inputs
;
152 num_tcs_output_cp
= num_tcs_input_cp
;
153 num_tcs_patch_outputs
= 2; /* TESSINNER + TESSOUTER */
156 input_vertex_size
= num_tcs_inputs
* 16;
157 output_vertex_size
= num_tcs_outputs
* 16;
159 input_patch_size
= num_tcs_input_cp
* input_vertex_size
;
161 pervertex_output_patch_size
= num_tcs_output_cp
* output_vertex_size
;
162 output_patch_size
= pervertex_output_patch_size
+ num_tcs_patch_outputs
* 16;
164 /* Ensure that we only need one wave per SIMD so we don't need to check
165 * resource usage. Also ensures that the number of tcs in and out
166 * vertices per threadgroup are at most 256.
168 *num_patches
= 64 / MAX2(num_tcs_input_cp
, num_tcs_output_cp
) * 4;
170 /* Make sure that the data fits in LDS. This assumes the shaders only
171 * use LDS for the inputs and outputs.
173 hardware_lds_size
= sctx
->b
.chip_class
>= CIK
? 65536 : 32768;
174 *num_patches
= MIN2(*num_patches
, hardware_lds_size
/ (input_patch_size
+
177 /* Make sure the output data fits in the offchip buffer */
178 *num_patches
= MIN2(*num_patches
,
179 (sctx
->screen
->tess_offchip_block_dw_size
* 4) /
182 /* Not necessary for correctness, but improves performance. The
183 * specific value is taken from the proprietary driver.
185 *num_patches
= MIN2(*num_patches
, 40);
187 /* SI bug workaround - limit LS-HS threadgroups to only one wave. */
188 if (sctx
->b
.chip_class
== SI
) {
189 unsigned one_wave
= 64 / MAX2(num_tcs_input_cp
, num_tcs_output_cp
);
190 *num_patches
= MIN2(*num_patches
, one_wave
);
193 sctx
->last_num_patches
= *num_patches
;
195 output_patch0_offset
= input_patch_size
* *num_patches
;
196 perpatch_output_offset
= output_patch0_offset
+ pervertex_output_patch_size
;
198 /* Compute userdata SGPRs. */
199 assert(((input_vertex_size
/ 4) & ~0xff) == 0);
200 assert(((output_vertex_size
/ 4) & ~0xff) == 0);
201 assert(((input_patch_size
/ 4) & ~0x1fff) == 0);
202 assert(((output_patch_size
/ 4) & ~0x1fff) == 0);
203 assert(((output_patch0_offset
/ 16) & ~0xffff) == 0);
204 assert(((perpatch_output_offset
/ 16) & ~0xffff) == 0);
205 assert(num_tcs_input_cp
<= 32);
206 assert(num_tcs_output_cp
<= 32);
208 tcs_in_layout
= S_VS_STATE_LS_OUT_PATCH_SIZE(input_patch_size
/ 4) |
209 S_VS_STATE_LS_OUT_VERTEX_SIZE(input_vertex_size
/ 4);
210 tcs_out_layout
= (output_patch_size
/ 4) |
211 ((output_vertex_size
/ 4) << 13);
212 tcs_out_offsets
= (output_patch0_offset
/ 16) |
213 ((perpatch_output_offset
/ 16) << 16);
214 offchip_layout
= *num_patches
|
215 (num_tcs_output_cp
<< 6) |
216 (pervertex_output_patch_size
* *num_patches
<< 12);
218 /* Compute the LDS size. */
219 lds_size
= output_patch0_offset
+ output_patch_size
* *num_patches
;
221 if (sctx
->b
.chip_class
>= CIK
) {
222 assert(lds_size
<= 65536);
223 lds_size
= align(lds_size
, 512) / 512;
225 assert(lds_size
<= 32768);
226 lds_size
= align(lds_size
, 256) / 256;
229 /* Set SI_SGPR_VS_STATE_BITS. */
230 sctx
->current_vs_state
&= C_VS_STATE_LS_OUT_PATCH_SIZE
&
231 C_VS_STATE_LS_OUT_VERTEX_SIZE
;
232 sctx
->current_vs_state
|= tcs_in_layout
;
234 if (sctx
->b
.chip_class
>= GFX9
) {
235 unsigned hs_rsrc2
= ls_current
->config
.rsrc2
|
236 S_00B42C_LDS_SIZE(lds_size
);
238 radeon_set_sh_reg(cs
, R_00B42C_SPI_SHADER_PGM_RSRC2_HS
, hs_rsrc2
);
240 /* Set userdata SGPRs for merged LS-HS. */
241 radeon_set_sh_reg_seq(cs
,
242 R_00B430_SPI_SHADER_USER_DATA_LS_0
+
243 GFX9_SGPR_TCS_OFFCHIP_LAYOUT
* 4, 3);
244 radeon_emit(cs
, offchip_layout
);
245 radeon_emit(cs
, tcs_out_offsets
);
246 radeon_emit(cs
, tcs_out_layout
| (num_tcs_input_cp
<< 26));
248 unsigned ls_rsrc2
= ls_current
->config
.rsrc2
;
250 si_multiwave_lds_size_workaround(sctx
->screen
, &lds_size
);
251 ls_rsrc2
|= S_00B52C_LDS_SIZE(lds_size
);
253 /* Due to a hw bug, RSRC2_LS must be written twice with another
254 * LS register written in between. */
255 if (sctx
->b
.chip_class
== CIK
&& sctx
->b
.family
!= CHIP_HAWAII
)
256 radeon_set_sh_reg(cs
, R_00B52C_SPI_SHADER_PGM_RSRC2_LS
, ls_rsrc2
);
257 radeon_set_sh_reg_seq(cs
, R_00B528_SPI_SHADER_PGM_RSRC1_LS
, 2);
258 radeon_emit(cs
, ls_current
->config
.rsrc1
);
259 radeon_emit(cs
, ls_rsrc2
);
261 /* Set userdata SGPRs for TCS. */
262 radeon_set_sh_reg_seq(cs
,
263 R_00B430_SPI_SHADER_USER_DATA_HS_0
+ GFX6_SGPR_TCS_OFFCHIP_LAYOUT
* 4, 4);
264 radeon_emit(cs
, offchip_layout
);
265 radeon_emit(cs
, tcs_out_offsets
);
266 radeon_emit(cs
, tcs_out_layout
| (num_tcs_input_cp
<< 26));
267 radeon_emit(cs
, tcs_in_layout
);
270 /* Set userdata SGPRs for TES. */
271 radeon_set_sh_reg_seq(cs
, tes_sh_base
+ SI_SGPR_TES_OFFCHIP_LAYOUT
* 4, 2);
272 radeon_emit(cs
, offchip_layout
);
273 radeon_emit(cs
, r600_resource(sctx
->tess_offchip_ring
)->gpu_address
>> 16);
275 ls_hs_config
= S_028B58_NUM_PATCHES(*num_patches
) |
276 S_028B58_HS_NUM_INPUT_CP(num_tcs_input_cp
) |
277 S_028B58_HS_NUM_OUTPUT_CP(num_tcs_output_cp
);
279 if (sctx
->b
.chip_class
>= CIK
)
280 radeon_set_context_reg_idx(cs
, R_028B58_VGT_LS_HS_CONFIG
, 2,
283 radeon_set_context_reg(cs
, R_028B58_VGT_LS_HS_CONFIG
,
287 static unsigned si_num_prims_for_vertices(const struct pipe_draw_info
*info
)
289 switch (info
->mode
) {
290 case PIPE_PRIM_PATCHES
:
291 return info
->count
/ info
->vertices_per_patch
;
292 case R600_PRIM_RECTANGLE_LIST
:
293 return info
->count
/ 3;
295 return u_prims_for_vertices(info
->mode
, info
->count
);
300 si_get_init_multi_vgt_param(struct si_screen
*sscreen
,
301 union si_vgt_param_key
*key
)
303 STATIC_ASSERT(sizeof(union si_vgt_param_key
) == 4);
304 unsigned max_primgroup_in_wave
= 2;
306 /* SWITCH_ON_EOP(0) is always preferable. */
307 bool wd_switch_on_eop
= false;
308 bool ia_switch_on_eop
= false;
309 bool ia_switch_on_eoi
= false;
310 bool partial_vs_wave
= false;
311 bool partial_es_wave
= false;
313 if (key
->u
.uses_tess
) {
314 /* SWITCH_ON_EOI must be set if PrimID is used. */
315 if (key
->u
.tcs_tes_uses_prim_id
)
316 ia_switch_on_eoi
= true;
318 /* Bug with tessellation and GS on Bonaire and older 2 SE chips. */
319 if ((sscreen
->b
.family
== CHIP_TAHITI
||
320 sscreen
->b
.family
== CHIP_PITCAIRN
||
321 sscreen
->b
.family
== CHIP_BONAIRE
) &&
323 partial_vs_wave
= true;
325 /* Needed for 028B6C_DISTRIBUTION_MODE != 0 */
326 if (sscreen
->has_distributed_tess
) {
327 if (key
->u
.uses_gs
) {
328 if (sscreen
->b
.chip_class
<= VI
)
329 partial_es_wave
= true;
331 /* GPU hang workaround. */
332 if (sscreen
->b
.family
== CHIP_TONGA
||
333 sscreen
->b
.family
== CHIP_FIJI
||
334 sscreen
->b
.family
== CHIP_POLARIS10
||
335 sscreen
->b
.family
== CHIP_POLARIS11
)
336 partial_vs_wave
= true;
338 partial_vs_wave
= true;
343 /* This is a hardware requirement. */
344 if (key
->u
.line_stipple_enabled
||
345 (sscreen
->b
.debug_flags
& DBG_SWITCH_ON_EOP
)) {
346 ia_switch_on_eop
= true;
347 wd_switch_on_eop
= true;
350 if (sscreen
->b
.chip_class
>= CIK
) {
351 /* WD_SWITCH_ON_EOP has no effect on GPUs with less than
352 * 4 shader engines. Set 1 to pass the assertion below.
353 * The other cases are hardware requirements.
355 * Polaris supports primitive restart with WD_SWITCH_ON_EOP=0
356 * for points, line strips, and tri strips.
358 if (sscreen
->b
.info
.max_se
< 4 ||
359 key
->u
.prim
== PIPE_PRIM_POLYGON
||
360 key
->u
.prim
== PIPE_PRIM_LINE_LOOP
||
361 key
->u
.prim
== PIPE_PRIM_TRIANGLE_FAN
||
362 key
->u
.prim
== PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY
||
363 (key
->u
.primitive_restart
&&
364 (sscreen
->b
.family
< CHIP_POLARIS10
||
365 (key
->u
.prim
!= PIPE_PRIM_POINTS
&&
366 key
->u
.prim
!= PIPE_PRIM_LINE_STRIP
&&
367 key
->u
.prim
!= PIPE_PRIM_TRIANGLE_STRIP
))) ||
368 key
->u
.count_from_stream_output
)
369 wd_switch_on_eop
= true;
371 /* Hawaii hangs if instancing is enabled and WD_SWITCH_ON_EOP is 0.
372 * We don't know that for indirect drawing, so treat it as
373 * always problematic. */
374 if (sscreen
->b
.family
== CHIP_HAWAII
&&
375 key
->u
.uses_instancing
)
376 wd_switch_on_eop
= true;
378 /* Performance recommendation for 4 SE Gfx7-8 parts if
379 * instances are smaller than a primgroup.
380 * Assume indirect draws always use small instances.
381 * This is needed for good VS wave utilization.
383 if (sscreen
->b
.chip_class
<= VI
&&
384 sscreen
->b
.info
.max_se
== 4 &&
385 key
->u
.multi_instances_smaller_than_primgroup
)
386 wd_switch_on_eop
= true;
388 /* Required on CIK and later. */
389 if (sscreen
->b
.info
.max_se
> 2 && !wd_switch_on_eop
)
390 ia_switch_on_eoi
= true;
392 /* Required by Hawaii and, for some special cases, by VI. */
393 if (ia_switch_on_eoi
&&
394 (sscreen
->b
.family
== CHIP_HAWAII
||
395 (sscreen
->b
.chip_class
== VI
&&
396 (key
->u
.uses_gs
|| max_primgroup_in_wave
!= 2))))
397 partial_vs_wave
= true;
399 /* Instancing bug on Bonaire. */
400 if (sscreen
->b
.family
== CHIP_BONAIRE
&& ia_switch_on_eoi
&&
401 key
->u
.uses_instancing
)
402 partial_vs_wave
= true;
404 /* If the WD switch is false, the IA switch must be false too. */
405 assert(wd_switch_on_eop
|| !ia_switch_on_eop
);
408 /* If SWITCH_ON_EOI is set, PARTIAL_ES_WAVE must be set too. */
409 if (sscreen
->b
.chip_class
<= VI
&& ia_switch_on_eoi
)
410 partial_es_wave
= true;
412 return S_028AA8_SWITCH_ON_EOP(ia_switch_on_eop
) |
413 S_028AA8_SWITCH_ON_EOI(ia_switch_on_eoi
) |
414 S_028AA8_PARTIAL_VS_WAVE_ON(partial_vs_wave
) |
415 S_028AA8_PARTIAL_ES_WAVE_ON(partial_es_wave
) |
416 S_028AA8_WD_SWITCH_ON_EOP(sscreen
->b
.chip_class
>= CIK
? wd_switch_on_eop
: 0) |
417 /* The following field was moved to VGT_SHADER_STAGES_EN in GFX9. */
418 S_028AA8_MAX_PRIMGRP_IN_WAVE(sscreen
->b
.chip_class
== VI
?
419 max_primgroup_in_wave
: 0) |
420 S_030960_EN_INST_OPT_BASIC(sscreen
->b
.chip_class
>= GFX9
) |
421 S_030960_EN_INST_OPT_ADV(sscreen
->b
.chip_class
>= GFX9
);
424 void si_init_ia_multi_vgt_param_table(struct si_context
*sctx
)
426 for (int prim
= 0; prim
<= R600_PRIM_RECTANGLE_LIST
; prim
++)
427 for (int uses_instancing
= 0; uses_instancing
< 2; uses_instancing
++)
428 for (int multi_instances
= 0; multi_instances
< 2; multi_instances
++)
429 for (int primitive_restart
= 0; primitive_restart
< 2; primitive_restart
++)
430 for (int count_from_so
= 0; count_from_so
< 2; count_from_so
++)
431 for (int line_stipple
= 0; line_stipple
< 2; line_stipple
++)
432 for (int uses_tess
= 0; uses_tess
< 2; uses_tess
++)
433 for (int tess_uses_primid
= 0; tess_uses_primid
< 2; tess_uses_primid
++)
434 for (int uses_gs
= 0; uses_gs
< 2; uses_gs
++) {
435 union si_vgt_param_key key
;
439 key
.u
.uses_instancing
= uses_instancing
;
440 key
.u
.multi_instances_smaller_than_primgroup
= multi_instances
;
441 key
.u
.primitive_restart
= primitive_restart
;
442 key
.u
.count_from_stream_output
= count_from_so
;
443 key
.u
.line_stipple_enabled
= line_stipple
;
444 key
.u
.uses_tess
= uses_tess
;
445 key
.u
.tcs_tes_uses_prim_id
= tess_uses_primid
;
446 key
.u
.uses_gs
= uses_gs
;
448 sctx
->ia_multi_vgt_param
[key
.index
] =
449 si_get_init_multi_vgt_param(sctx
->screen
, &key
);
453 static unsigned si_get_ia_multi_vgt_param(struct si_context
*sctx
,
454 const struct pipe_draw_info
*info
,
455 unsigned num_patches
)
457 union si_vgt_param_key key
= sctx
->ia_multi_vgt_param_key
;
458 unsigned primgroup_size
;
459 unsigned ia_multi_vgt_param
;
461 if (sctx
->tes_shader
.cso
) {
462 primgroup_size
= num_patches
; /* must be a multiple of NUM_PATCHES */
463 } else if (sctx
->gs_shader
.cso
) {
464 primgroup_size
= 64; /* recommended with a GS */
466 primgroup_size
= 128; /* recommended without a GS and tess */
469 key
.u
.prim
= info
->mode
;
470 key
.u
.uses_instancing
= info
->indirect
|| info
->instance_count
> 1;
471 key
.u
.multi_instances_smaller_than_primgroup
=
473 (info
->instance_count
> 1 &&
474 (info
->count_from_stream_output
||
475 si_num_prims_for_vertices(info
) < primgroup_size
));
476 key
.u
.primitive_restart
= info
->primitive_restart
;
477 key
.u
.count_from_stream_output
= info
->count_from_stream_output
!= NULL
;
479 ia_multi_vgt_param
= sctx
->ia_multi_vgt_param
[key
.index
] |
480 S_028AA8_PRIMGROUP_SIZE(primgroup_size
- 1);
482 if (sctx
->gs_shader
.cso
) {
483 /* GS requirement. */
484 if (sctx
->b
.chip_class
<= VI
&&
485 SI_GS_PER_ES
/ primgroup_size
>= sctx
->screen
->gs_table_depth
- 3)
486 ia_multi_vgt_param
|= S_028AA8_PARTIAL_ES_WAVE_ON(1);
488 /* GS hw bug with single-primitive instances and SWITCH_ON_EOI.
489 * The hw doc says all multi-SE chips are affected, but Vulkan
490 * only applies it to Hawaii. Do what Vulkan does.
492 if (sctx
->b
.family
== CHIP_HAWAII
&&
493 G_028AA8_SWITCH_ON_EOI(ia_multi_vgt_param
) &&
495 (info
->instance_count
> 1 &&
496 (info
->count_from_stream_output
||
497 si_num_prims_for_vertices(info
) <= 1))))
498 sctx
->b
.flags
|= SI_CONTEXT_VGT_FLUSH
;
501 return ia_multi_vgt_param
;
504 /* rast_prim is the primitive type after GS. */
505 static void si_emit_rasterizer_prim_state(struct si_context
*sctx
)
507 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
508 enum pipe_prim_type rast_prim
= sctx
->current_rast_prim
;
509 struct si_state_rasterizer
*rs
= sctx
->emitted
.named
.rasterizer
;
511 /* Skip this if not rendering lines. */
512 if (rast_prim
!= PIPE_PRIM_LINES
&&
513 rast_prim
!= PIPE_PRIM_LINE_LOOP
&&
514 rast_prim
!= PIPE_PRIM_LINE_STRIP
&&
515 rast_prim
!= PIPE_PRIM_LINES_ADJACENCY
&&
516 rast_prim
!= PIPE_PRIM_LINE_STRIP_ADJACENCY
)
519 if (rast_prim
== sctx
->last_rast_prim
&&
520 rs
->pa_sc_line_stipple
== sctx
->last_sc_line_stipple
)
523 /* For lines, reset the stipple pattern at each primitive. Otherwise,
524 * reset the stipple pattern at each packet (line strips, line loops).
526 radeon_set_context_reg(cs
, R_028A0C_PA_SC_LINE_STIPPLE
,
527 rs
->pa_sc_line_stipple
|
528 S_028A0C_AUTO_RESET_CNTL(rast_prim
== PIPE_PRIM_LINES
? 1 : 2));
530 sctx
->last_rast_prim
= rast_prim
;
531 sctx
->last_sc_line_stipple
= rs
->pa_sc_line_stipple
;
534 static void si_emit_vs_state(struct si_context
*sctx
,
535 const struct pipe_draw_info
*info
)
537 sctx
->current_vs_state
&= C_VS_STATE_INDEXED
;
538 sctx
->current_vs_state
|= S_VS_STATE_INDEXED(!!info
->indexed
);
540 if (sctx
->current_vs_state
!= sctx
->last_vs_state
) {
541 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
543 radeon_set_sh_reg(cs
,
544 sctx
->shader_userdata
.sh_base
[PIPE_SHADER_VERTEX
] +
545 SI_SGPR_VS_STATE_BITS
* 4,
546 sctx
->current_vs_state
);
548 sctx
->last_vs_state
= sctx
->current_vs_state
;
552 static void si_emit_draw_registers(struct si_context
*sctx
,
553 const struct pipe_draw_info
*info
,
554 unsigned num_patches
)
556 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
557 unsigned prim
= si_conv_pipe_prim(info
->mode
);
558 unsigned gs_out_prim
= si_conv_prim_to_gs_out(sctx
->current_rast_prim
);
559 unsigned ia_multi_vgt_param
;
561 ia_multi_vgt_param
= si_get_ia_multi_vgt_param(sctx
, info
, num_patches
);
564 if (ia_multi_vgt_param
!= sctx
->last_multi_vgt_param
) {
565 if (sctx
->b
.chip_class
>= GFX9
)
566 radeon_set_uconfig_reg_idx(cs
, R_030960_IA_MULTI_VGT_PARAM
, 4, ia_multi_vgt_param
);
567 else if (sctx
->b
.chip_class
>= CIK
)
568 radeon_set_context_reg_idx(cs
, R_028AA8_IA_MULTI_VGT_PARAM
, 1, ia_multi_vgt_param
);
570 radeon_set_context_reg(cs
, R_028AA8_IA_MULTI_VGT_PARAM
, ia_multi_vgt_param
);
572 sctx
->last_multi_vgt_param
= ia_multi_vgt_param
;
574 if (prim
!= sctx
->last_prim
) {
575 if (sctx
->b
.chip_class
>= CIK
)
576 radeon_set_uconfig_reg_idx(cs
, R_030908_VGT_PRIMITIVE_TYPE
, 1, prim
);
578 radeon_set_config_reg(cs
, R_008958_VGT_PRIMITIVE_TYPE
, prim
);
580 sctx
->last_prim
= prim
;
583 if (gs_out_prim
!= sctx
->last_gs_out_prim
) {
584 radeon_set_context_reg(cs
, R_028A6C_VGT_GS_OUT_PRIM_TYPE
, gs_out_prim
);
585 sctx
->last_gs_out_prim
= gs_out_prim
;
588 /* Primitive restart. */
589 if (info
->primitive_restart
!= sctx
->last_primitive_restart_en
) {
590 if (sctx
->b
.chip_class
>= GFX9
)
591 radeon_set_uconfig_reg(cs
, R_03092C_VGT_MULTI_PRIM_IB_RESET_EN
,
592 info
->primitive_restart
);
594 radeon_set_context_reg(cs
, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN
,
595 info
->primitive_restart
);
597 sctx
->last_primitive_restart_en
= info
->primitive_restart
;
600 if (info
->primitive_restart
&&
601 (info
->restart_index
!= sctx
->last_restart_index
||
602 sctx
->last_restart_index
== SI_RESTART_INDEX_UNKNOWN
)) {
603 radeon_set_context_reg(cs
, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX
,
604 info
->restart_index
);
605 sctx
->last_restart_index
= info
->restart_index
;
609 static void si_emit_draw_packets(struct si_context
*sctx
,
610 const struct pipe_draw_info
*info
,
611 const struct pipe_index_buffer
*ib
)
613 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
614 unsigned sh_base_reg
= sctx
->shader_userdata
.sh_base
[PIPE_SHADER_VERTEX
];
615 bool render_cond_bit
= sctx
->b
.render_cond
&& !sctx
->b
.render_cond_force_off
;
616 uint32_t index_max_size
= 0;
617 uint64_t index_va
= 0;
619 if (info
->count_from_stream_output
) {
620 struct r600_so_target
*t
=
621 (struct r600_so_target
*)info
->count_from_stream_output
;
622 uint64_t va
= t
->buf_filled_size
->gpu_address
+
623 t
->buf_filled_size_offset
;
625 radeon_set_context_reg(cs
, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE
,
628 radeon_emit(cs
, PKT3(PKT3_COPY_DATA
, 4, 0));
629 radeon_emit(cs
, COPY_DATA_SRC_SEL(COPY_DATA_MEM
) |
630 COPY_DATA_DST_SEL(COPY_DATA_REG
) |
631 COPY_DATA_WR_CONFIRM
);
632 radeon_emit(cs
, va
); /* src address lo */
633 radeon_emit(cs
, va
>> 32); /* src address hi */
634 radeon_emit(cs
, R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE
>> 2);
635 radeon_emit(cs
, 0); /* unused */
637 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
,
638 t
->buf_filled_size
, RADEON_USAGE_READ
,
639 RADEON_PRIO_SO_FILLED_SIZE
);
644 if (ib
->index_size
!= sctx
->last_index_size
) {
648 switch (ib
->index_size
) {
650 index_type
= V_028A7C_VGT_INDEX_8
;
653 index_type
= V_028A7C_VGT_INDEX_16
|
654 (SI_BIG_ENDIAN
&& sctx
->b
.chip_class
<= CIK
?
655 V_028A7C_VGT_DMA_SWAP_16_BIT
: 0);
658 index_type
= V_028A7C_VGT_INDEX_32
|
659 (SI_BIG_ENDIAN
&& sctx
->b
.chip_class
<= CIK
?
660 V_028A7C_VGT_DMA_SWAP_32_BIT
: 0);
663 assert(!"unreachable");
667 if (sctx
->b
.chip_class
>= GFX9
) {
668 radeon_set_uconfig_reg_idx(cs
, R_03090C_VGT_INDEX_TYPE
,
671 radeon_emit(cs
, PKT3(PKT3_INDEX_TYPE
, 0, 0));
672 radeon_emit(cs
, index_type
);
675 sctx
->last_index_size
= ib
->index_size
;
678 index_max_size
= (ib
->buffer
->width0
- ib
->offset
) /
680 index_va
= r600_resource(ib
->buffer
)->gpu_address
+ ib
->offset
;
682 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
,
683 (struct r600_resource
*)ib
->buffer
,
684 RADEON_USAGE_READ
, RADEON_PRIO_INDEX_BUFFER
);
686 /* On CI and later, non-indexed draws overwrite VGT_INDEX_TYPE,
687 * so the state must be re-emitted before the next indexed draw.
689 if (sctx
->b
.chip_class
>= CIK
)
690 sctx
->last_index_size
= -1;
693 if (info
->indirect
) {
694 uint64_t indirect_va
= r600_resource(info
->indirect
)->gpu_address
;
696 assert(indirect_va
% 8 == 0);
698 si_invalidate_draw_sh_constants(sctx
);
700 radeon_emit(cs
, PKT3(PKT3_SET_BASE
, 2, 0));
702 radeon_emit(cs
, indirect_va
);
703 radeon_emit(cs
, indirect_va
>> 32);
705 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
,
706 (struct r600_resource
*)info
->indirect
,
707 RADEON_USAGE_READ
, RADEON_PRIO_DRAW_INDIRECT
);
709 unsigned di_src_sel
= info
->indexed
? V_0287F0_DI_SRC_SEL_DMA
710 : V_0287F0_DI_SRC_SEL_AUTO_INDEX
;
712 assert(info
->indirect_offset
% 4 == 0);
715 radeon_emit(cs
, PKT3(PKT3_INDEX_BASE
, 1, 0));
716 radeon_emit(cs
, index_va
);
717 radeon_emit(cs
, index_va
>> 32);
719 radeon_emit(cs
, PKT3(PKT3_INDEX_BUFFER_SIZE
, 0, 0));
720 radeon_emit(cs
, index_max_size
);
723 if (!sctx
->screen
->has_draw_indirect_multi
) {
724 radeon_emit(cs
, PKT3(info
->indexed
? PKT3_DRAW_INDEX_INDIRECT
725 : PKT3_DRAW_INDIRECT
,
726 3, render_cond_bit
));
727 radeon_emit(cs
, info
->indirect_offset
);
728 radeon_emit(cs
, (sh_base_reg
+ SI_SGPR_BASE_VERTEX
* 4 - SI_SH_REG_OFFSET
) >> 2);
729 radeon_emit(cs
, (sh_base_reg
+ SI_SGPR_START_INSTANCE
* 4 - SI_SH_REG_OFFSET
) >> 2);
730 radeon_emit(cs
, di_src_sel
);
732 uint64_t count_va
= 0;
734 if (info
->indirect_params
) {
735 struct r600_resource
*params_buf
=
736 (struct r600_resource
*)info
->indirect_params
;
738 radeon_add_to_buffer_list(
739 &sctx
->b
, &sctx
->b
.gfx
, params_buf
,
740 RADEON_USAGE_READ
, RADEON_PRIO_DRAW_INDIRECT
);
742 count_va
= params_buf
->gpu_address
+ info
->indirect_params_offset
;
745 radeon_emit(cs
, PKT3(info
->indexed
? PKT3_DRAW_INDEX_INDIRECT_MULTI
:
746 PKT3_DRAW_INDIRECT_MULTI
,
747 8, render_cond_bit
));
748 radeon_emit(cs
, info
->indirect_offset
);
749 radeon_emit(cs
, (sh_base_reg
+ SI_SGPR_BASE_VERTEX
* 4 - SI_SH_REG_OFFSET
) >> 2);
750 radeon_emit(cs
, (sh_base_reg
+ SI_SGPR_START_INSTANCE
* 4 - SI_SH_REG_OFFSET
) >> 2);
751 radeon_emit(cs
, ((sh_base_reg
+ SI_SGPR_DRAWID
* 4 - SI_SH_REG_OFFSET
) >> 2) |
752 S_2C3_DRAW_INDEX_ENABLE(1) |
753 S_2C3_COUNT_INDIRECT_ENABLE(!!info
->indirect_params
));
754 radeon_emit(cs
, info
->indirect_count
);
755 radeon_emit(cs
, count_va
);
756 radeon_emit(cs
, count_va
>> 32);
757 radeon_emit(cs
, info
->indirect_stride
);
758 radeon_emit(cs
, di_src_sel
);
763 radeon_emit(cs
, PKT3(PKT3_NUM_INSTANCES
, 0, 0));
764 radeon_emit(cs
, info
->instance_count
);
766 /* Base vertex and start instance. */
767 base_vertex
= info
->indexed
? info
->index_bias
: info
->start
;
769 if (base_vertex
!= sctx
->last_base_vertex
||
770 sctx
->last_base_vertex
== SI_BASE_VERTEX_UNKNOWN
||
771 info
->start_instance
!= sctx
->last_start_instance
||
772 info
->drawid
!= sctx
->last_drawid
||
773 sh_base_reg
!= sctx
->last_sh_base_reg
) {
774 radeon_set_sh_reg_seq(cs
, sh_base_reg
+ SI_SGPR_BASE_VERTEX
* 4, 3);
775 radeon_emit(cs
, base_vertex
);
776 radeon_emit(cs
, info
->start_instance
);
777 radeon_emit(cs
, info
->drawid
);
779 sctx
->last_base_vertex
= base_vertex
;
780 sctx
->last_start_instance
= info
->start_instance
;
781 sctx
->last_drawid
= info
->drawid
;
782 sctx
->last_sh_base_reg
= sh_base_reg
;
786 index_va
+= info
->start
* ib
->index_size
;
788 radeon_emit(cs
, PKT3(PKT3_DRAW_INDEX_2
, 4, render_cond_bit
));
789 radeon_emit(cs
, index_max_size
);
790 radeon_emit(cs
, index_va
);
791 radeon_emit(cs
, index_va
>> 32);
792 radeon_emit(cs
, info
->count
);
793 radeon_emit(cs
, V_0287F0_DI_SRC_SEL_DMA
);
795 radeon_emit(cs
, PKT3(PKT3_DRAW_INDEX_AUTO
, 1, render_cond_bit
));
796 radeon_emit(cs
, info
->count
);
797 radeon_emit(cs
, V_0287F0_DI_SRC_SEL_AUTO_INDEX
|
798 S_0287F0_USE_OPAQUE(!!info
->count_from_stream_output
));
803 static void si_emit_surface_sync(struct r600_common_context
*rctx
,
804 unsigned cp_coher_cntl
)
806 struct radeon_winsys_cs
*cs
= rctx
->gfx
.cs
;
808 if (rctx
->chip_class
>= GFX9
) {
809 /* Flush caches and wait for the caches to assert idle. */
810 radeon_emit(cs
, PKT3(PKT3_ACQUIRE_MEM
, 5, 0));
811 radeon_emit(cs
, cp_coher_cntl
); /* CP_COHER_CNTL */
812 radeon_emit(cs
, 0xffffffff); /* CP_COHER_SIZE */
813 radeon_emit(cs
, 0xffffff); /* CP_COHER_SIZE_HI */
814 radeon_emit(cs
, 0); /* CP_COHER_BASE */
815 radeon_emit(cs
, 0); /* CP_COHER_BASE_HI */
816 radeon_emit(cs
, 0x0000000A); /* POLL_INTERVAL */
818 /* ACQUIRE_MEM is only required on a compute ring. */
819 radeon_emit(cs
, PKT3(PKT3_SURFACE_SYNC
, 3, 0));
820 radeon_emit(cs
, cp_coher_cntl
); /* CP_COHER_CNTL */
821 radeon_emit(cs
, 0xffffffff); /* CP_COHER_SIZE */
822 radeon_emit(cs
, 0); /* CP_COHER_BASE */
823 radeon_emit(cs
, 0x0000000A); /* POLL_INTERVAL */
827 void si_emit_cache_flush(struct si_context
*sctx
)
829 struct r600_common_context
*rctx
= &sctx
->b
;
830 struct radeon_winsys_cs
*cs
= rctx
->gfx
.cs
;
831 uint32_t cp_coher_cntl
= 0;
832 uint32_t flush_cb_db
= rctx
->flags
& (SI_CONTEXT_FLUSH_AND_INV_CB
|
833 SI_CONTEXT_FLUSH_AND_INV_DB
);
835 if (rctx
->flags
& (SI_CONTEXT_FLUSH_AND_INV_CB
|
836 SI_CONTEXT_FLUSH_AND_INV_DB
))
837 sctx
->b
.num_fb_cache_flushes
++;
839 /* SI has a bug that it always flushes ICACHE and KCACHE if either
840 * bit is set. An alternative way is to write SQC_CACHES, but that
841 * doesn't seem to work reliably. Since the bug doesn't affect
842 * correctness (it only does more work than necessary) and
843 * the performance impact is likely negligible, there is no plan
844 * to add a workaround for it.
847 if (rctx
->flags
& SI_CONTEXT_INV_ICACHE
)
848 cp_coher_cntl
|= S_0085F0_SH_ICACHE_ACTION_ENA(1);
849 if (rctx
->flags
& SI_CONTEXT_INV_SMEM_L1
)
850 cp_coher_cntl
|= S_0085F0_SH_KCACHE_ACTION_ENA(1);
852 if (rctx
->chip_class
<= VI
) {
853 if (rctx
->flags
& SI_CONTEXT_FLUSH_AND_INV_CB
) {
854 cp_coher_cntl
|= S_0085F0_CB_ACTION_ENA(1) |
855 S_0085F0_CB0_DEST_BASE_ENA(1) |
856 S_0085F0_CB1_DEST_BASE_ENA(1) |
857 S_0085F0_CB2_DEST_BASE_ENA(1) |
858 S_0085F0_CB3_DEST_BASE_ENA(1) |
859 S_0085F0_CB4_DEST_BASE_ENA(1) |
860 S_0085F0_CB5_DEST_BASE_ENA(1) |
861 S_0085F0_CB6_DEST_BASE_ENA(1) |
862 S_0085F0_CB7_DEST_BASE_ENA(1);
864 /* Necessary for DCC */
865 if (rctx
->chip_class
== VI
)
866 r600_gfx_write_event_eop(rctx
, V_028A90_FLUSH_AND_INV_CB_DATA_TS
,
867 0, 0, NULL
, 0, 0, 0);
869 if (rctx
->flags
& SI_CONTEXT_FLUSH_AND_INV_DB
)
870 cp_coher_cntl
|= S_0085F0_DB_ACTION_ENA(1) |
871 S_0085F0_DB_DEST_BASE_ENA(1);
874 if (rctx
->flags
& SI_CONTEXT_FLUSH_AND_INV_CB
) {
875 /* Flush CMASK/FMASK/DCC. SURFACE_SYNC will wait for idle. */
876 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
877 radeon_emit(cs
, EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_META
) | EVENT_INDEX(0));
879 if (rctx
->flags
& SI_CONTEXT_FLUSH_AND_INV_DB
) {
880 /* Flush HTILE. SURFACE_SYNC will wait for idle. */
881 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
882 radeon_emit(cs
, EVENT_TYPE(V_028A90_FLUSH_AND_INV_DB_META
) | EVENT_INDEX(0));
885 /* Wait for shader engines to go idle.
886 * VS and PS waits are unnecessary if SURFACE_SYNC is going to wait
887 * for everything including CB/DB cache flushes.
890 if (rctx
->flags
& SI_CONTEXT_PS_PARTIAL_FLUSH
) {
891 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
892 radeon_emit(cs
, EVENT_TYPE(V_028A90_PS_PARTIAL_FLUSH
) | EVENT_INDEX(4));
893 /* Only count explicit shader flushes, not implicit ones
894 * done by SURFACE_SYNC.
896 rctx
->num_vs_flushes
++;
897 rctx
->num_ps_flushes
++;
898 } else if (rctx
->flags
& SI_CONTEXT_VS_PARTIAL_FLUSH
) {
899 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
900 radeon_emit(cs
, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH
) | EVENT_INDEX(4));
901 rctx
->num_vs_flushes
++;
905 if (rctx
->flags
& SI_CONTEXT_CS_PARTIAL_FLUSH
&&
906 sctx
->compute_is_busy
) {
907 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
908 radeon_emit(cs
, EVENT_TYPE(V_028A90_CS_PARTIAL_FLUSH
| EVENT_INDEX(4)));
909 rctx
->num_cs_flushes
++;
910 sctx
->compute_is_busy
= false;
913 /* VGT state synchronization. */
914 if (rctx
->flags
& SI_CONTEXT_VGT_FLUSH
) {
915 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
916 radeon_emit(cs
, EVENT_TYPE(V_028A90_VGT_FLUSH
) | EVENT_INDEX(0));
918 if (rctx
->flags
& SI_CONTEXT_VGT_STREAMOUT_SYNC
) {
919 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
920 radeon_emit(cs
, EVENT_TYPE(V_028A90_VGT_STREAMOUT_SYNC
) | EVENT_INDEX(0));
923 /* GFX9: Wait for idle if we're flushing CB or DB. ACQUIRE_MEM doesn't
924 * wait for idle on GFX9. We have to use a TS event.
926 if (sctx
->b
.chip_class
>= GFX9
&& flush_cb_db
) {
927 struct r600_resource
*rbuf
= NULL
;
929 unsigned offset
= 0, tc_flags
, cb_db_event
;
931 /* Set the CB/DB flush event. */
932 switch (flush_cb_db
) {
933 case SI_CONTEXT_FLUSH_AND_INV_CB
:
934 cb_db_event
= V_028A90_FLUSH_AND_INV_CB_DATA_TS
;
936 case SI_CONTEXT_FLUSH_AND_INV_DB
:
937 cb_db_event
= V_028A90_FLUSH_AND_INV_DB_DATA_TS
;
941 cb_db_event
= V_028A90_CACHE_FLUSH_AND_INV_TS_EVENT
;
944 /* TC | TC_WB = invalidate L2 data
945 * TC_MD | TC_WB = invalidate L2 metadata
946 * TC | TC_WB | TC_MD = invalidate L2 data & metadata
948 * The metadata cache must always be invalidated for coherency
949 * between CB/DB and shaders. (metadata = HTILE, CMASK, DCC)
951 * TC must be invalidated on GFX9 only if the CB/DB surface is
952 * not pipe-aligned. If the surface is RB-aligned, it might not
953 * strictly be pipe-aligned since RB alignment takes precendence.
955 tc_flags
= EVENT_TC_WB_ACTION_ENA
|
956 EVENT_TC_MD_ACTION_ENA
;
958 /* Ideally flush TC together with CB/DB. */
959 if (rctx
->flags
& SI_CONTEXT_INV_GLOBAL_L2
) {
960 tc_flags
|= EVENT_TC_ACTION_ENA
|
961 EVENT_TCL1_ACTION_ENA
;
963 /* Clear the flags. */
964 rctx
->flags
&= ~(SI_CONTEXT_INV_GLOBAL_L2
|
965 SI_CONTEXT_WRITEBACK_GLOBAL_L2
|
966 SI_CONTEXT_INV_VMEM_L1
);
969 /* Allocate memory for the fence. */
970 u_suballocator_alloc(rctx
->allocator_zeroed_memory
, 4, 4,
971 &offset
, (struct pipe_resource
**)&rbuf
);
972 va
= rbuf
->gpu_address
+ offset
;
974 r600_gfx_write_event_eop(rctx
, cb_db_event
, tc_flags
, 1,
976 r600_gfx_wait_fence(rctx
, va
, 1, 0xffffffff);
979 /* Make sure ME is idle (it executes most packets) before continuing.
980 * This prevents read-after-write hazards between PFP and ME.
983 (rctx
->flags
& (SI_CONTEXT_CS_PARTIAL_FLUSH
|
984 SI_CONTEXT_INV_VMEM_L1
|
985 SI_CONTEXT_INV_GLOBAL_L2
|
986 SI_CONTEXT_WRITEBACK_GLOBAL_L2
))) {
987 radeon_emit(cs
, PKT3(PKT3_PFP_SYNC_ME
, 0, 0));
992 * When one of the CP_COHER_CNTL.DEST_BASE flags is set, SURFACE_SYNC
993 * waits for idle, so it should be last. SURFACE_SYNC is done in PFP.
995 * cp_coher_cntl should contain all necessary flags except TC flags
998 * SI-CIK don't support L2 write-back.
1000 if (rctx
->flags
& SI_CONTEXT_INV_GLOBAL_L2
||
1001 (rctx
->chip_class
<= CIK
&&
1002 (rctx
->flags
& SI_CONTEXT_WRITEBACK_GLOBAL_L2
))) {
1003 /* Invalidate L1 & L2. (L1 is always invalidated on SI)
1004 * WB must be set on VI+ when TC_ACTION is set.
1006 si_emit_surface_sync(rctx
, cp_coher_cntl
|
1007 S_0085F0_TC_ACTION_ENA(1) |
1008 S_0085F0_TCL1_ACTION_ENA(1) |
1009 S_0301F0_TC_WB_ACTION_ENA(rctx
->chip_class
>= VI
));
1011 sctx
->b
.num_L2_invalidates
++;
1013 /* L1 invalidation and L2 writeback must be done separately,
1014 * because both operations can't be done together.
1016 if (rctx
->flags
& SI_CONTEXT_WRITEBACK_GLOBAL_L2
) {
1018 * NC = apply to non-coherent MTYPEs
1019 * (i.e. MTYPE <= 1, which is what we use everywhere)
1021 * WB doesn't work without NC.
1023 si_emit_surface_sync(rctx
, cp_coher_cntl
|
1024 S_0301F0_TC_WB_ACTION_ENA(1) |
1025 S_0301F0_TC_NC_ACTION_ENA(1));
1027 sctx
->b
.num_L2_writebacks
++;
1029 if (rctx
->flags
& SI_CONTEXT_INV_VMEM_L1
) {
1030 /* Invalidate per-CU VMEM L1. */
1031 si_emit_surface_sync(rctx
, cp_coher_cntl
|
1032 S_0085F0_TCL1_ACTION_ENA(1));
1037 /* If TC flushes haven't cleared this... */
1039 si_emit_surface_sync(rctx
, cp_coher_cntl
);
1041 if (rctx
->flags
& R600_CONTEXT_START_PIPELINE_STATS
) {
1042 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
1043 radeon_emit(cs
, EVENT_TYPE(V_028A90_PIPELINESTAT_START
) |
1045 } else if (rctx
->flags
& R600_CONTEXT_STOP_PIPELINE_STATS
) {
1046 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
1047 radeon_emit(cs
, EVENT_TYPE(V_028A90_PIPELINESTAT_STOP
) |
1054 static void si_get_draw_start_count(struct si_context
*sctx
,
1055 const struct pipe_draw_info
*info
,
1056 unsigned *start
, unsigned *count
)
1058 if (info
->indirect
) {
1059 unsigned indirect_count
;
1060 struct pipe_transfer
*transfer
;
1061 unsigned begin
, end
;
1065 if (info
->indirect_params
) {
1066 data
= pipe_buffer_map_range(&sctx
->b
.b
,
1067 info
->indirect_params
,
1068 info
->indirect_params_offset
,
1070 PIPE_TRANSFER_READ
, &transfer
);
1072 indirect_count
= *data
;
1074 pipe_buffer_unmap(&sctx
->b
.b
, transfer
);
1076 indirect_count
= info
->indirect_count
;
1079 if (!indirect_count
) {
1080 *start
= *count
= 0;
1084 map_size
= (indirect_count
- 1) * info
->indirect_stride
+ 3 * sizeof(unsigned);
1085 data
= pipe_buffer_map_range(&sctx
->b
.b
, info
->indirect
,
1086 info
->indirect_offset
, map_size
,
1087 PIPE_TRANSFER_READ
, &transfer
);
1092 for (unsigned i
= 0; i
< indirect_count
; ++i
) {
1093 unsigned count
= data
[0];
1094 unsigned start
= data
[2];
1097 begin
= MIN2(begin
, start
);
1098 end
= MAX2(end
, start
+ count
);
1101 data
+= info
->indirect_stride
/ sizeof(unsigned);
1104 pipe_buffer_unmap(&sctx
->b
.b
, transfer
);
1108 *count
= end
- begin
;
1110 *start
= *count
= 0;
1113 *start
= info
->start
;
1114 *count
= info
->count
;
1118 void si_ce_pre_draw_synchronization(struct si_context
*sctx
)
1120 if (sctx
->ce_need_synchronization
) {
1121 radeon_emit(sctx
->ce_ib
, PKT3(PKT3_INCREMENT_CE_COUNTER
, 0, 0));
1122 radeon_emit(sctx
->ce_ib
, 1);
1124 radeon_emit(sctx
->b
.gfx
.cs
, PKT3(PKT3_WAIT_ON_CE_COUNTER
, 0, 0));
1125 radeon_emit(sctx
->b
.gfx
.cs
, 1);
1129 void si_ce_post_draw_synchronization(struct si_context
*sctx
)
1131 if (sctx
->ce_need_synchronization
) {
1132 radeon_emit(sctx
->b
.gfx
.cs
, PKT3(PKT3_INCREMENT_DE_COUNTER
, 0, 0));
1133 radeon_emit(sctx
->b
.gfx
.cs
, 0);
1135 sctx
->ce_need_synchronization
= false;
1139 void si_draw_vbo(struct pipe_context
*ctx
, const struct pipe_draw_info
*info
)
1141 struct si_context
*sctx
= (struct si_context
*)ctx
;
1142 struct si_state_rasterizer
*rs
= sctx
->queued
.named
.rasterizer
;
1143 const struct pipe_index_buffer
*ib
= &sctx
->index_buffer
;
1144 struct pipe_index_buffer ib_tmp
; /* for index buffer uploads only */
1145 unsigned mask
, dirty_tex_counter
;
1146 enum pipe_prim_type rast_prim
;
1147 unsigned num_patches
= 0;
1149 if (likely(!info
->indirect
)) {
1150 /* SI-CI treat instance_count==0 as instance_count==1. There is
1151 * no workaround for indirect draws, but we can at least skip
1154 if (unlikely(!info
->instance_count
))
1157 /* Handle count == 0. */
1158 if (unlikely(!info
->count
&&
1159 (info
->indexed
|| !info
->count_from_stream_output
)))
1163 if (unlikely(!sctx
->vs_shader
.cso
)) {
1167 if (unlikely(!sctx
->ps_shader
.cso
&& (!rs
|| !rs
->rasterizer_discard
))) {
1171 if (unlikely(!!sctx
->tes_shader
.cso
!= (info
->mode
== PIPE_PRIM_PATCHES
))) {
1176 /* Recompute and re-emit the texture resource states if needed. */
1177 dirty_tex_counter
= p_atomic_read(&sctx
->b
.screen
->dirty_tex_counter
);
1178 if (unlikely(dirty_tex_counter
!= sctx
->b
.last_dirty_tex_counter
)) {
1179 sctx
->b
.last_dirty_tex_counter
= dirty_tex_counter
;
1180 sctx
->framebuffer
.dirty_cbufs
|=
1181 ((1 << sctx
->framebuffer
.state
.nr_cbufs
) - 1);
1182 sctx
->framebuffer
.dirty_zsbuf
= true;
1183 sctx
->framebuffer
.do_update_surf_dirtiness
= true;
1184 si_mark_atom_dirty(sctx
, &sctx
->framebuffer
.atom
);
1185 si_update_all_texture_descriptors(sctx
);
1188 si_decompress_graphics_textures(sctx
);
1190 /* Set the rasterization primitive type.
1192 * This must be done after si_decompress_textures, which can call
1193 * draw_vbo recursively, and before si_update_shaders, which uses
1194 * current_rast_prim for this draw_vbo call. */
1195 if (sctx
->gs_shader
.cso
)
1196 rast_prim
= sctx
->gs_shader
.cso
->gs_output_prim
;
1197 else if (sctx
->tes_shader
.cso
)
1198 rast_prim
= sctx
->tes_shader
.cso
->info
.properties
[TGSI_PROPERTY_TES_PRIM_MODE
];
1200 rast_prim
= info
->mode
;
1202 if (rast_prim
!= sctx
->current_rast_prim
) {
1203 sctx
->current_rast_prim
= rast_prim
;
1204 sctx
->do_update_shaders
= true;
1207 if (sctx
->gs_shader
.cso
) {
1208 /* Determine whether the GS triangle strip adjacency fix should
1209 * be applied. Rotate every other triangle if
1210 * - triangle strips with adjacency are fed to the GS and
1211 * - primitive restart is disabled (the rotation doesn't help
1212 * when the restart occurs after an odd number of triangles).
1214 bool gs_tri_strip_adj_fix
=
1215 !sctx
->tes_shader
.cso
&&
1216 info
->mode
== PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY
&&
1217 !info
->primitive_restart
;
1219 if (gs_tri_strip_adj_fix
!= sctx
->gs_tri_strip_adj_fix
) {
1220 sctx
->gs_tri_strip_adj_fix
= gs_tri_strip_adj_fix
;
1221 sctx
->do_update_shaders
= true;
1225 if (sctx
->do_update_shaders
&& !si_update_shaders(sctx
))
1228 if (!si_upload_graphics_shader_descriptors(sctx
))
1231 ib_tmp
.buffer
= NULL
;
1233 if (info
->indexed
) {
1234 /* Translate or upload, if needed. */
1235 /* 8-bit indices are supported on VI. */
1236 if (sctx
->b
.chip_class
<= CIK
&& ib
->index_size
== 1) {
1237 unsigned start
, count
, start_offset
, size
;
1240 si_get_draw_start_count(sctx
, info
, &start
, &count
);
1241 start_offset
= start
* 2;
1244 u_upload_alloc(ctx
->stream_uploader
, start_offset
,
1246 si_optimal_tcc_alignment(sctx
, size
),
1247 &ib_tmp
.offset
, &ib_tmp
.buffer
, &ptr
);
1251 util_shorten_ubyte_elts_to_userptr(&sctx
->b
.b
, ib
, 0, 0,
1255 /* info->start will be added by the drawing code */
1256 ib_tmp
.offset
-= start_offset
;
1257 ib_tmp
.index_size
= 2;
1259 } else if (ib
->user_buffer
&& !ib
->buffer
) {
1260 unsigned start_offset
;
1262 assert(!info
->indirect
);
1263 start_offset
= info
->start
* ib
->index_size
;
1265 u_upload_data(ctx
->stream_uploader
, start_offset
,
1266 info
->count
* ib
->index_size
,
1267 sctx
->screen
->b
.info
.tcc_cache_line_size
,
1268 (char*)ib
->user_buffer
+ start_offset
,
1269 &ib_tmp
.offset
, &ib_tmp
.buffer
);
1273 /* info->start will be added by the drawing code */
1274 ib_tmp
.offset
-= start_offset
;
1275 ib_tmp
.index_size
= ib
->index_size
;
1277 } else if (sctx
->b
.chip_class
<= CIK
&&
1278 r600_resource(ib
->buffer
)->TC_L2_dirty
) {
1279 /* VI reads index buffers through TC L2, so it doesn't
1281 sctx
->b
.flags
|= SI_CONTEXT_WRITEBACK_GLOBAL_L2
;
1282 r600_resource(ib
->buffer
)->TC_L2_dirty
= false;
1286 if (info
->indirect
) {
1287 /* Add the buffer size for memory checking in need_cs_space. */
1288 r600_context_add_resource_size(ctx
, info
->indirect
);
1290 if (r600_resource(info
->indirect
)->TC_L2_dirty
) {
1291 sctx
->b
.flags
|= SI_CONTEXT_WRITEBACK_GLOBAL_L2
;
1292 r600_resource(info
->indirect
)->TC_L2_dirty
= false;
1295 if (info
->indirect_params
&&
1296 r600_resource(info
->indirect_params
)->TC_L2_dirty
) {
1297 sctx
->b
.flags
|= SI_CONTEXT_WRITEBACK_GLOBAL_L2
;
1298 r600_resource(info
->indirect_params
)->TC_L2_dirty
= false;
1302 si_need_cs_space(sctx
);
1304 /* Since we've called r600_context_add_resource_size for vertex buffers,
1305 * this must be called after si_need_cs_space, because we must let
1306 * need_cs_space flush before we add buffers to the buffer list.
1308 if (!si_upload_vertex_buffer_descriptors(sctx
))
1311 /* GFX9 scissor bug workaround. There is also a more efficient but
1312 * more involved alternative workaround. */
1313 if (sctx
->b
.chip_class
== GFX9
&&
1314 si_is_atom_dirty(sctx
, &sctx
->b
.scissors
.atom
))
1315 sctx
->b
.flags
|= SI_CONTEXT_PS_PARTIAL_FLUSH
;
1317 /* Flush caches before the first state atom, which does L2 prefetches. */
1319 si_emit_cache_flush(sctx
);
1321 /* Emit state atoms. */
1322 mask
= sctx
->dirty_atoms
;
1324 struct r600_atom
*atom
= sctx
->atoms
.array
[u_bit_scan(&mask
)];
1326 atom
->emit(&sctx
->b
, atom
);
1328 sctx
->dirty_atoms
= 0;
1331 mask
= sctx
->dirty_states
;
1333 unsigned i
= u_bit_scan(&mask
);
1334 struct si_pm4_state
*state
= sctx
->queued
.array
[i
];
1336 if (!state
|| sctx
->emitted
.array
[i
] == state
)
1339 si_pm4_emit(sctx
, state
);
1340 sctx
->emitted
.array
[i
] = state
;
1342 sctx
->dirty_states
= 0;
1344 si_emit_rasterizer_prim_state(sctx
);
1345 if (sctx
->tes_shader
.cso
)
1346 si_emit_derived_tess_state(sctx
, info
, &num_patches
);
1347 si_emit_vs_state(sctx
, info
);
1348 si_emit_draw_registers(sctx
, info
, num_patches
);
1350 si_ce_pre_draw_synchronization(sctx
);
1351 si_emit_draw_packets(sctx
, info
, ib
);
1352 si_ce_post_draw_synchronization(sctx
);
1354 if (sctx
->trace_buf
)
1355 si_trace_emit(sctx
);
1357 /* Workaround for a VGT hang when streamout is enabled.
1358 * It must be done after drawing. */
1359 if ((sctx
->b
.family
== CHIP_HAWAII
||
1360 sctx
->b
.family
== CHIP_TONGA
||
1361 sctx
->b
.family
== CHIP_FIJI
) &&
1362 r600_get_strmout_en(&sctx
->b
)) {
1363 sctx
->b
.flags
|= SI_CONTEXT_VGT_STREAMOUT_SYNC
;
1366 if (sctx
->framebuffer
.do_update_surf_dirtiness
) {
1367 /* Set the depth buffer as dirty. */
1368 if (sctx
->framebuffer
.state
.zsbuf
) {
1369 struct pipe_surface
*surf
= sctx
->framebuffer
.state
.zsbuf
;
1370 struct r600_texture
*rtex
= (struct r600_texture
*)surf
->texture
;
1372 if (!rtex
->tc_compatible_htile
)
1373 rtex
->dirty_level_mask
|= 1 << surf
->u
.tex
.level
;
1375 if (rtex
->surface
.flags
& RADEON_SURF_SBUFFER
)
1376 rtex
->stencil_dirty_level_mask
|= 1 << surf
->u
.tex
.level
;
1378 if (sctx
->framebuffer
.compressed_cb_mask
) {
1379 struct pipe_surface
*surf
;
1380 struct r600_texture
*rtex
;
1381 unsigned mask
= sctx
->framebuffer
.compressed_cb_mask
;
1384 unsigned i
= u_bit_scan(&mask
);
1385 surf
= sctx
->framebuffer
.state
.cbufs
[i
];
1386 rtex
= (struct r600_texture
*)surf
->texture
;
1388 if (rtex
->fmask
.size
)
1389 rtex
->dirty_level_mask
|= 1 << surf
->u
.tex
.level
;
1390 if (rtex
->dcc_gather_statistics
)
1391 rtex
->separate_dcc_dirty
= true;
1394 sctx
->framebuffer
.do_update_surf_dirtiness
= false;
1397 pipe_resource_reference(&ib_tmp
.buffer
, NULL
);
1398 sctx
->b
.num_draw_calls
++;
1399 if (G_0286E8_WAVESIZE(sctx
->spi_tmpring_size
))
1400 sctx
->b
.num_spill_draw_calls
++;
1403 void si_trace_emit(struct si_context
*sctx
)
1405 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
1408 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
, sctx
->trace_buf
,
1409 RADEON_USAGE_READWRITE
, RADEON_PRIO_TRACE
);
1410 radeon_emit(cs
, PKT3(PKT3_WRITE_DATA
, 3, 0));
1411 radeon_emit(cs
, S_370_DST_SEL(V_370_MEMORY_SYNC
) |
1412 S_370_WR_CONFIRM(1) |
1413 S_370_ENGINE_SEL(V_370_ME
));
1414 radeon_emit(cs
, sctx
->trace_buf
->gpu_address
);
1415 radeon_emit(cs
, sctx
->trace_buf
->gpu_address
>> 32);
1416 radeon_emit(cs
, sctx
->trace_id
);
1417 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
1418 radeon_emit(cs
, AC_ENCODE_TRACE_POINT(sctx
->trace_id
));