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radeonsi/gfx9: set up shader registers for merged LS-HS
[mesa.git] / src / gallium / drivers / radeonsi / si_state_draw.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Christian König <christian.koenig@amd.com>
25 */
26
27 #include "si_pipe.h"
28 #include "radeon/r600_cs.h"
29 #include "sid.h"
30 #include "gfx9d.h"
31
32 #include "util/u_index_modify.h"
33 #include "util/u_upload_mgr.h"
34 #include "util/u_prim.h"
35
36 #include "ac_debug.h"
37
38 static unsigned si_conv_pipe_prim(unsigned mode)
39 {
40 static const unsigned prim_conv[] = {
41 [PIPE_PRIM_POINTS] = V_008958_DI_PT_POINTLIST,
42 [PIPE_PRIM_LINES] = V_008958_DI_PT_LINELIST,
43 [PIPE_PRIM_LINE_LOOP] = V_008958_DI_PT_LINELOOP,
44 [PIPE_PRIM_LINE_STRIP] = V_008958_DI_PT_LINESTRIP,
45 [PIPE_PRIM_TRIANGLES] = V_008958_DI_PT_TRILIST,
46 [PIPE_PRIM_TRIANGLE_STRIP] = V_008958_DI_PT_TRISTRIP,
47 [PIPE_PRIM_TRIANGLE_FAN] = V_008958_DI_PT_TRIFAN,
48 [PIPE_PRIM_QUADS] = V_008958_DI_PT_QUADLIST,
49 [PIPE_PRIM_QUAD_STRIP] = V_008958_DI_PT_QUADSTRIP,
50 [PIPE_PRIM_POLYGON] = V_008958_DI_PT_POLYGON,
51 [PIPE_PRIM_LINES_ADJACENCY] = V_008958_DI_PT_LINELIST_ADJ,
52 [PIPE_PRIM_LINE_STRIP_ADJACENCY] = V_008958_DI_PT_LINESTRIP_ADJ,
53 [PIPE_PRIM_TRIANGLES_ADJACENCY] = V_008958_DI_PT_TRILIST_ADJ,
54 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY] = V_008958_DI_PT_TRISTRIP_ADJ,
55 [PIPE_PRIM_PATCHES] = V_008958_DI_PT_PATCH,
56 [R600_PRIM_RECTANGLE_LIST] = V_008958_DI_PT_RECTLIST
57 };
58 assert(mode < ARRAY_SIZE(prim_conv));
59 return prim_conv[mode];
60 }
61
62 static unsigned si_conv_prim_to_gs_out(unsigned mode)
63 {
64 static const int prim_conv[] = {
65 [PIPE_PRIM_POINTS] = V_028A6C_OUTPRIM_TYPE_POINTLIST,
66 [PIPE_PRIM_LINES] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
67 [PIPE_PRIM_LINE_LOOP] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
68 [PIPE_PRIM_LINE_STRIP] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
69 [PIPE_PRIM_TRIANGLES] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
70 [PIPE_PRIM_TRIANGLE_STRIP] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
71 [PIPE_PRIM_TRIANGLE_FAN] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
72 [PIPE_PRIM_QUADS] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
73 [PIPE_PRIM_QUAD_STRIP] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
74 [PIPE_PRIM_POLYGON] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
75 [PIPE_PRIM_LINES_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
76 [PIPE_PRIM_LINE_STRIP_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
77 [PIPE_PRIM_TRIANGLES_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
78 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
79 [PIPE_PRIM_PATCHES] = V_028A6C_OUTPRIM_TYPE_POINTLIST,
80 [R600_PRIM_RECTANGLE_LIST] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
81 };
82 assert(mode < ARRAY_SIZE(prim_conv));
83
84 return prim_conv[mode];
85 }
86
87 /**
88 * This calculates the LDS size for tessellation shaders (VS, TCS, TES).
89 * LS.LDS_SIZE is shared by all 3 shader stages.
90 *
91 * The information about LDS and other non-compile-time parameters is then
92 * written to userdata SGPRs.
93 */
94 static void si_emit_derived_tess_state(struct si_context *sctx,
95 const struct pipe_draw_info *info,
96 unsigned *num_patches)
97 {
98 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
99 struct si_shader *ls_current;
100 struct si_shader_selector *ls;
101 /* The TES pointer will only be used for sctx->last_tcs.
102 * It would be wrong to think that TCS = TES. */
103 struct si_shader_selector *tcs =
104 sctx->tcs_shader.cso ? sctx->tcs_shader.cso : sctx->tes_shader.cso;
105 unsigned tes_sh_base = sctx->shader_userdata.sh_base[PIPE_SHADER_TESS_EVAL];
106 unsigned num_tcs_input_cp = info->vertices_per_patch;
107 unsigned num_tcs_output_cp, num_tcs_inputs, num_tcs_outputs;
108 unsigned num_tcs_patch_outputs;
109 unsigned input_vertex_size, output_vertex_size, pervertex_output_patch_size;
110 unsigned input_patch_size, output_patch_size, output_patch0_offset;
111 unsigned perpatch_output_offset, lds_size;
112 unsigned tcs_in_layout, tcs_out_layout, tcs_out_offsets;
113 unsigned offchip_layout, hardware_lds_size, ls_hs_config;
114
115 /* Since GFX9 has merged LS-HS in the TCS state, set LS = TCS. */
116 if (sctx->b.chip_class >= GFX9) {
117 if (sctx->tcs_shader.cso)
118 ls_current = sctx->tcs_shader.current;
119 else
120 ls_current = sctx->fixed_func_tcs_shader.current;
121
122 ls = ls_current->key.part.tcs.ls;
123 } else {
124 ls_current = sctx->vs_shader.current;
125 ls = sctx->vs_shader.cso;
126 }
127
128 if (sctx->last_ls == ls_current &&
129 sctx->last_tcs == tcs &&
130 sctx->last_tes_sh_base == tes_sh_base &&
131 sctx->last_num_tcs_input_cp == num_tcs_input_cp) {
132 *num_patches = sctx->last_num_patches;
133 return;
134 }
135
136 sctx->last_ls = ls_current;
137 sctx->last_tcs = tcs;
138 sctx->last_tes_sh_base = tes_sh_base;
139 sctx->last_num_tcs_input_cp = num_tcs_input_cp;
140
141 /* This calculates how shader inputs and outputs among VS, TCS, and TES
142 * are laid out in LDS. */
143 num_tcs_inputs = util_last_bit64(ls->outputs_written);
144
145 if (sctx->tcs_shader.cso) {
146 num_tcs_outputs = util_last_bit64(tcs->outputs_written);
147 num_tcs_output_cp = tcs->info.properties[TGSI_PROPERTY_TCS_VERTICES_OUT];
148 num_tcs_patch_outputs = util_last_bit64(tcs->patch_outputs_written);
149 } else {
150 /* No TCS. Route varyings from LS to TES. */
151 num_tcs_outputs = num_tcs_inputs;
152 num_tcs_output_cp = num_tcs_input_cp;
153 num_tcs_patch_outputs = 2; /* TESSINNER + TESSOUTER */
154 }
155
156 input_vertex_size = num_tcs_inputs * 16;
157 output_vertex_size = num_tcs_outputs * 16;
158
159 input_patch_size = num_tcs_input_cp * input_vertex_size;
160
161 pervertex_output_patch_size = num_tcs_output_cp * output_vertex_size;
162 output_patch_size = pervertex_output_patch_size + num_tcs_patch_outputs * 16;
163
164 /* Ensure that we only need one wave per SIMD so we don't need to check
165 * resource usage. Also ensures that the number of tcs in and out
166 * vertices per threadgroup are at most 256.
167 */
168 *num_patches = 64 / MAX2(num_tcs_input_cp, num_tcs_output_cp) * 4;
169
170 /* Make sure that the data fits in LDS. This assumes the shaders only
171 * use LDS for the inputs and outputs.
172 */
173 hardware_lds_size = sctx->b.chip_class >= CIK ? 65536 : 32768;
174 *num_patches = MIN2(*num_patches, hardware_lds_size / (input_patch_size +
175 output_patch_size));
176
177 /* Make sure the output data fits in the offchip buffer */
178 *num_patches = MIN2(*num_patches,
179 (sctx->screen->tess_offchip_block_dw_size * 4) /
180 output_patch_size);
181
182 /* Not necessary for correctness, but improves performance. The
183 * specific value is taken from the proprietary driver.
184 */
185 *num_patches = MIN2(*num_patches, 40);
186
187 /* SI bug workaround - limit LS-HS threadgroups to only one wave. */
188 if (sctx->b.chip_class == SI) {
189 unsigned one_wave = 64 / MAX2(num_tcs_input_cp, num_tcs_output_cp);
190 *num_patches = MIN2(*num_patches, one_wave);
191 }
192
193 sctx->last_num_patches = *num_patches;
194
195 output_patch0_offset = input_patch_size * *num_patches;
196 perpatch_output_offset = output_patch0_offset + pervertex_output_patch_size;
197
198 /* Compute userdata SGPRs. */
199 assert(((input_vertex_size / 4) & ~0xff) == 0);
200 assert(((output_vertex_size / 4) & ~0xff) == 0);
201 assert(((input_patch_size / 4) & ~0x1fff) == 0);
202 assert(((output_patch_size / 4) & ~0x1fff) == 0);
203 assert(((output_patch0_offset / 16) & ~0xffff) == 0);
204 assert(((perpatch_output_offset / 16) & ~0xffff) == 0);
205 assert(num_tcs_input_cp <= 32);
206 assert(num_tcs_output_cp <= 32);
207
208 tcs_in_layout = S_VS_STATE_LS_OUT_PATCH_SIZE(input_patch_size / 4) |
209 S_VS_STATE_LS_OUT_VERTEX_SIZE(input_vertex_size / 4);
210 tcs_out_layout = (output_patch_size / 4) |
211 ((output_vertex_size / 4) << 13);
212 tcs_out_offsets = (output_patch0_offset / 16) |
213 ((perpatch_output_offset / 16) << 16);
214 offchip_layout = (pervertex_output_patch_size * *num_patches << 16) |
215 (num_tcs_output_cp << 9) | *num_patches;
216
217 /* Compute the LDS size. */
218 lds_size = output_patch0_offset + output_patch_size * *num_patches;
219
220 if (sctx->b.chip_class >= CIK) {
221 assert(lds_size <= 65536);
222 lds_size = align(lds_size, 512) / 512;
223 } else {
224 assert(lds_size <= 32768);
225 lds_size = align(lds_size, 256) / 256;
226 }
227
228 /* Set SI_SGPR_VS_STATE_BITS. */
229 sctx->current_vs_state &= C_VS_STATE_LS_OUT_PATCH_SIZE &
230 C_VS_STATE_LS_OUT_VERTEX_SIZE;
231 sctx->current_vs_state |= tcs_in_layout;
232
233 if (sctx->b.chip_class >= GFX9) {
234 unsigned hs_rsrc2 = ls_current->config.rsrc2 |
235 S_00B42C_LDS_SIZE(lds_size);
236
237 radeon_set_sh_reg(cs, R_00B42C_SPI_SHADER_PGM_RSRC2_HS, hs_rsrc2);
238 } else {
239 unsigned ls_rsrc2 = ls_current->config.rsrc2;
240
241 si_multiwave_lds_size_workaround(sctx->screen, &lds_size);
242 ls_rsrc2 |= S_00B52C_LDS_SIZE(lds_size);
243
244 /* Due to a hw bug, RSRC2_LS must be written twice with another
245 * LS register written in between. */
246 if (sctx->b.chip_class == CIK && sctx->b.family != CHIP_HAWAII)
247 radeon_set_sh_reg(cs, R_00B52C_SPI_SHADER_PGM_RSRC2_LS, ls_rsrc2);
248 radeon_set_sh_reg_seq(cs, R_00B528_SPI_SHADER_PGM_RSRC1_LS, 2);
249 radeon_emit(cs, ls_current->config.rsrc1);
250 radeon_emit(cs, ls_rsrc2);
251
252 /* Set userdata SGPRs for TCS. */
253 radeon_set_sh_reg_seq(cs,
254 R_00B430_SPI_SHADER_USER_DATA_HS_0 + SI_SGPR_TCS_OFFCHIP_LAYOUT * 4, 4);
255 radeon_emit(cs, offchip_layout);
256 radeon_emit(cs, tcs_out_offsets);
257 radeon_emit(cs, tcs_out_layout | (num_tcs_input_cp << 26));
258 radeon_emit(cs, tcs_in_layout);
259 }
260
261 /* Set userdata SGPRs for TES. */
262 radeon_set_sh_reg_seq(cs, tes_sh_base + SI_SGPR_TCS_OFFCHIP_LAYOUT * 4, 1);
263 radeon_emit(cs, offchip_layout);
264
265 ls_hs_config = S_028B58_NUM_PATCHES(*num_patches) |
266 S_028B58_HS_NUM_INPUT_CP(num_tcs_input_cp) |
267 S_028B58_HS_NUM_OUTPUT_CP(num_tcs_output_cp);
268
269 if (sctx->b.chip_class >= CIK)
270 radeon_set_context_reg_idx(cs, R_028B58_VGT_LS_HS_CONFIG, 2,
271 ls_hs_config);
272 else
273 radeon_set_context_reg(cs, R_028B58_VGT_LS_HS_CONFIG,
274 ls_hs_config);
275 }
276
277 static unsigned si_num_prims_for_vertices(const struct pipe_draw_info *info)
278 {
279 switch (info->mode) {
280 case PIPE_PRIM_PATCHES:
281 return info->count / info->vertices_per_patch;
282 case R600_PRIM_RECTANGLE_LIST:
283 return info->count / 3;
284 default:
285 return u_prims_for_vertices(info->mode, info->count);
286 }
287 }
288
289 static unsigned
290 si_get_init_multi_vgt_param(struct si_screen *sscreen,
291 union si_vgt_param_key *key)
292 {
293 STATIC_ASSERT(sizeof(union si_vgt_param_key) == 4);
294 unsigned max_primgroup_in_wave = 2;
295
296 /* SWITCH_ON_EOP(0) is always preferable. */
297 bool wd_switch_on_eop = false;
298 bool ia_switch_on_eop = false;
299 bool ia_switch_on_eoi = false;
300 bool partial_vs_wave = false;
301 bool partial_es_wave = false;
302
303 if (key->u.uses_tess) {
304 /* SWITCH_ON_EOI must be set if PrimID is used. */
305 if (key->u.tcs_tes_uses_prim_id)
306 ia_switch_on_eoi = true;
307
308 /* Bug with tessellation and GS on Bonaire and older 2 SE chips. */
309 if ((sscreen->b.family == CHIP_TAHITI ||
310 sscreen->b.family == CHIP_PITCAIRN ||
311 sscreen->b.family == CHIP_BONAIRE) &&
312 key->u.uses_gs)
313 partial_vs_wave = true;
314
315 /* Needed for 028B6C_DISTRIBUTION_MODE != 0 */
316 if (sscreen->has_distributed_tess) {
317 if (key->u.uses_gs) {
318 if (sscreen->b.chip_class <= VI)
319 partial_es_wave = true;
320
321 /* GPU hang workaround. */
322 if (sscreen->b.family == CHIP_TONGA ||
323 sscreen->b.family == CHIP_FIJI ||
324 sscreen->b.family == CHIP_POLARIS10 ||
325 sscreen->b.family == CHIP_POLARIS11)
326 partial_vs_wave = true;
327 } else {
328 partial_vs_wave = true;
329 }
330 }
331 }
332
333 /* This is a hardware requirement. */
334 if (key->u.line_stipple_enabled ||
335 (sscreen->b.debug_flags & DBG_SWITCH_ON_EOP)) {
336 ia_switch_on_eop = true;
337 wd_switch_on_eop = true;
338 }
339
340 if (sscreen->b.chip_class >= CIK) {
341 /* WD_SWITCH_ON_EOP has no effect on GPUs with less than
342 * 4 shader engines. Set 1 to pass the assertion below.
343 * The other cases are hardware requirements.
344 *
345 * Polaris supports primitive restart with WD_SWITCH_ON_EOP=0
346 * for points, line strips, and tri strips.
347 */
348 if (sscreen->b.info.max_se < 4 ||
349 key->u.prim == PIPE_PRIM_POLYGON ||
350 key->u.prim == PIPE_PRIM_LINE_LOOP ||
351 key->u.prim == PIPE_PRIM_TRIANGLE_FAN ||
352 key->u.prim == PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY ||
353 (key->u.primitive_restart &&
354 (sscreen->b.family < CHIP_POLARIS10 ||
355 (key->u.prim != PIPE_PRIM_POINTS &&
356 key->u.prim != PIPE_PRIM_LINE_STRIP &&
357 key->u.prim != PIPE_PRIM_TRIANGLE_STRIP))) ||
358 key->u.count_from_stream_output)
359 wd_switch_on_eop = true;
360
361 /* Hawaii hangs if instancing is enabled and WD_SWITCH_ON_EOP is 0.
362 * We don't know that for indirect drawing, so treat it as
363 * always problematic. */
364 if (sscreen->b.family == CHIP_HAWAII &&
365 key->u.uses_instancing)
366 wd_switch_on_eop = true;
367
368 /* Performance recommendation for 4 SE Gfx7-8 parts if
369 * instances are smaller than a primgroup.
370 * Assume indirect draws always use small instances.
371 * This is needed for good VS wave utilization.
372 */
373 if (sscreen->b.chip_class <= VI &&
374 sscreen->b.info.max_se == 4 &&
375 key->u.multi_instances_smaller_than_primgroup)
376 wd_switch_on_eop = true;
377
378 /* Required on CIK and later. */
379 if (sscreen->b.info.max_se > 2 && !wd_switch_on_eop)
380 ia_switch_on_eoi = true;
381
382 /* Required by Hawaii and, for some special cases, by VI. */
383 if (ia_switch_on_eoi &&
384 (sscreen->b.family == CHIP_HAWAII ||
385 (sscreen->b.chip_class == VI &&
386 (key->u.uses_gs || max_primgroup_in_wave != 2))))
387 partial_vs_wave = true;
388
389 /* Instancing bug on Bonaire. */
390 if (sscreen->b.family == CHIP_BONAIRE && ia_switch_on_eoi &&
391 key->u.uses_instancing)
392 partial_vs_wave = true;
393
394 /* If the WD switch is false, the IA switch must be false too. */
395 assert(wd_switch_on_eop || !ia_switch_on_eop);
396 }
397
398 /* If SWITCH_ON_EOI is set, PARTIAL_ES_WAVE must be set too. */
399 if (sscreen->b.chip_class <= VI && ia_switch_on_eoi)
400 partial_es_wave = true;
401
402 return S_028AA8_SWITCH_ON_EOP(ia_switch_on_eop) |
403 S_028AA8_SWITCH_ON_EOI(ia_switch_on_eoi) |
404 S_028AA8_PARTIAL_VS_WAVE_ON(partial_vs_wave) |
405 S_028AA8_PARTIAL_ES_WAVE_ON(partial_es_wave) |
406 S_028AA8_WD_SWITCH_ON_EOP(sscreen->b.chip_class >= CIK ? wd_switch_on_eop : 0) |
407 /* The following field was moved to VGT_SHADER_STAGES_EN in GFX9. */
408 S_028AA8_MAX_PRIMGRP_IN_WAVE(sscreen->b.chip_class == VI ?
409 max_primgroup_in_wave : 0) |
410 S_030960_EN_INST_OPT_BASIC(sscreen->b.chip_class >= GFX9) |
411 S_030960_EN_INST_OPT_ADV(sscreen->b.chip_class >= GFX9);
412 }
413
414 void si_init_ia_multi_vgt_param_table(struct si_context *sctx)
415 {
416 for (int prim = 0; prim <= R600_PRIM_RECTANGLE_LIST; prim++)
417 for (int uses_instancing = 0; uses_instancing < 2; uses_instancing++)
418 for (int multi_instances = 0; multi_instances < 2; multi_instances++)
419 for (int primitive_restart = 0; primitive_restart < 2; primitive_restart++)
420 for (int count_from_so = 0; count_from_so < 2; count_from_so++)
421 for (int line_stipple = 0; line_stipple < 2; line_stipple++)
422 for (int uses_tess = 0; uses_tess < 2; uses_tess++)
423 for (int tess_uses_primid = 0; tess_uses_primid < 2; tess_uses_primid++)
424 for (int uses_gs = 0; uses_gs < 2; uses_gs++) {
425 union si_vgt_param_key key;
426
427 key.index = 0;
428 key.u.prim = prim;
429 key.u.uses_instancing = uses_instancing;
430 key.u.multi_instances_smaller_than_primgroup = multi_instances;
431 key.u.primitive_restart = primitive_restart;
432 key.u.count_from_stream_output = count_from_so;
433 key.u.line_stipple_enabled = line_stipple;
434 key.u.uses_tess = uses_tess;
435 key.u.tcs_tes_uses_prim_id = tess_uses_primid;
436 key.u.uses_gs = uses_gs;
437
438 sctx->ia_multi_vgt_param[key.index] =
439 si_get_init_multi_vgt_param(sctx->screen, &key);
440 }
441 }
442
443 static unsigned si_get_ia_multi_vgt_param(struct si_context *sctx,
444 const struct pipe_draw_info *info,
445 unsigned num_patches)
446 {
447 union si_vgt_param_key key = sctx->ia_multi_vgt_param_key;
448 unsigned primgroup_size;
449 unsigned ia_multi_vgt_param;
450
451 if (sctx->tes_shader.cso) {
452 primgroup_size = num_patches; /* must be a multiple of NUM_PATCHES */
453 } else if (sctx->gs_shader.cso) {
454 primgroup_size = 64; /* recommended with a GS */
455 } else {
456 primgroup_size = 128; /* recommended without a GS and tess */
457 }
458
459 key.u.prim = info->mode;
460 key.u.uses_instancing = info->indirect || info->instance_count > 1;
461 key.u.multi_instances_smaller_than_primgroup =
462 info->indirect ||
463 (info->instance_count > 1 &&
464 (info->count_from_stream_output ||
465 si_num_prims_for_vertices(info) < primgroup_size));
466 key.u.primitive_restart = info->primitive_restart;
467 key.u.count_from_stream_output = info->count_from_stream_output != NULL;
468
469 ia_multi_vgt_param = sctx->ia_multi_vgt_param[key.index] |
470 S_028AA8_PRIMGROUP_SIZE(primgroup_size - 1);
471
472 if (sctx->gs_shader.cso) {
473 /* GS requirement. */
474 if (SI_GS_PER_ES / primgroup_size >= sctx->screen->gs_table_depth - 3)
475 ia_multi_vgt_param |= S_028AA8_PARTIAL_ES_WAVE_ON(1);
476
477 /* GS hw bug with single-primitive instances and SWITCH_ON_EOI.
478 * The hw doc says all multi-SE chips are affected, but Vulkan
479 * only applies it to Hawaii. Do what Vulkan does.
480 */
481 if (sctx->b.family == CHIP_HAWAII &&
482 G_028AA8_SWITCH_ON_EOI(ia_multi_vgt_param) &&
483 (info->indirect ||
484 (info->instance_count > 1 &&
485 (info->count_from_stream_output ||
486 si_num_prims_for_vertices(info) <= 1))))
487 sctx->b.flags |= SI_CONTEXT_VGT_FLUSH;
488 }
489
490 return ia_multi_vgt_param;
491 }
492
493 /* rast_prim is the primitive type after GS. */
494 static void si_emit_rasterizer_prim_state(struct si_context *sctx)
495 {
496 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
497 enum pipe_prim_type rast_prim = sctx->current_rast_prim;
498 struct si_state_rasterizer *rs = sctx->emitted.named.rasterizer;
499
500 /* Skip this if not rendering lines. */
501 if (rast_prim != PIPE_PRIM_LINES &&
502 rast_prim != PIPE_PRIM_LINE_LOOP &&
503 rast_prim != PIPE_PRIM_LINE_STRIP &&
504 rast_prim != PIPE_PRIM_LINES_ADJACENCY &&
505 rast_prim != PIPE_PRIM_LINE_STRIP_ADJACENCY)
506 return;
507
508 if (rast_prim == sctx->last_rast_prim &&
509 rs->pa_sc_line_stipple == sctx->last_sc_line_stipple)
510 return;
511
512 /* For lines, reset the stipple pattern at each primitive. Otherwise,
513 * reset the stipple pattern at each packet (line strips, line loops).
514 */
515 radeon_set_context_reg(cs, R_028A0C_PA_SC_LINE_STIPPLE,
516 rs->pa_sc_line_stipple |
517 S_028A0C_AUTO_RESET_CNTL(rast_prim == PIPE_PRIM_LINES ? 1 : 2));
518
519 sctx->last_rast_prim = rast_prim;
520 sctx->last_sc_line_stipple = rs->pa_sc_line_stipple;
521 }
522
523 static void si_emit_vs_state(struct si_context *sctx,
524 const struct pipe_draw_info *info)
525 {
526 sctx->current_vs_state &= C_VS_STATE_INDEXED;
527 sctx->current_vs_state |= S_VS_STATE_INDEXED(!!info->indexed);
528
529 if (sctx->current_vs_state != sctx->last_vs_state) {
530 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
531
532 radeon_set_sh_reg(cs,
533 sctx->shader_userdata.sh_base[PIPE_SHADER_VERTEX] +
534 SI_SGPR_VS_STATE_BITS * 4,
535 sctx->current_vs_state);
536
537 sctx->last_vs_state = sctx->current_vs_state;
538 }
539 }
540
541 static void si_emit_draw_registers(struct si_context *sctx,
542 const struct pipe_draw_info *info,
543 unsigned num_patches)
544 {
545 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
546 unsigned prim = si_conv_pipe_prim(info->mode);
547 unsigned gs_out_prim = si_conv_prim_to_gs_out(sctx->current_rast_prim);
548 unsigned ia_multi_vgt_param;
549
550 ia_multi_vgt_param = si_get_ia_multi_vgt_param(sctx, info, num_patches);
551
552 /* Draw state. */
553 if (ia_multi_vgt_param != sctx->last_multi_vgt_param) {
554 if (sctx->b.chip_class >= GFX9)
555 radeon_set_uconfig_reg_idx(cs, R_030960_IA_MULTI_VGT_PARAM, 4, ia_multi_vgt_param);
556 else if (sctx->b.chip_class >= CIK)
557 radeon_set_context_reg_idx(cs, R_028AA8_IA_MULTI_VGT_PARAM, 1, ia_multi_vgt_param);
558 else
559 radeon_set_context_reg(cs, R_028AA8_IA_MULTI_VGT_PARAM, ia_multi_vgt_param);
560
561 sctx->last_multi_vgt_param = ia_multi_vgt_param;
562 }
563 if (prim != sctx->last_prim) {
564 if (sctx->b.chip_class >= CIK)
565 radeon_set_uconfig_reg_idx(cs, R_030908_VGT_PRIMITIVE_TYPE, 1, prim);
566 else
567 radeon_set_config_reg(cs, R_008958_VGT_PRIMITIVE_TYPE, prim);
568
569 sctx->last_prim = prim;
570 }
571
572 if (gs_out_prim != sctx->last_gs_out_prim) {
573 radeon_set_context_reg(cs, R_028A6C_VGT_GS_OUT_PRIM_TYPE, gs_out_prim);
574 sctx->last_gs_out_prim = gs_out_prim;
575 }
576
577 /* Primitive restart. */
578 if (info->primitive_restart != sctx->last_primitive_restart_en) {
579 if (sctx->b.chip_class >= GFX9)
580 radeon_set_uconfig_reg(cs, R_03092C_VGT_MULTI_PRIM_IB_RESET_EN,
581 info->primitive_restart);
582 else
583 radeon_set_context_reg(cs, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN,
584 info->primitive_restart);
585
586 sctx->last_primitive_restart_en = info->primitive_restart;
587
588 }
589 if (info->primitive_restart &&
590 (info->restart_index != sctx->last_restart_index ||
591 sctx->last_restart_index == SI_RESTART_INDEX_UNKNOWN)) {
592 radeon_set_context_reg(cs, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
593 info->restart_index);
594 sctx->last_restart_index = info->restart_index;
595 }
596 }
597
598 static void si_emit_draw_packets(struct si_context *sctx,
599 const struct pipe_draw_info *info,
600 const struct pipe_index_buffer *ib)
601 {
602 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
603 unsigned sh_base_reg = sctx->shader_userdata.sh_base[PIPE_SHADER_VERTEX];
604 bool render_cond_bit = sctx->b.render_cond && !sctx->b.render_cond_force_off;
605 uint32_t index_max_size = 0;
606 uint64_t index_va = 0;
607
608 if (info->count_from_stream_output) {
609 struct r600_so_target *t =
610 (struct r600_so_target*)info->count_from_stream_output;
611 uint64_t va = t->buf_filled_size->gpu_address +
612 t->buf_filled_size_offset;
613
614 radeon_set_context_reg(cs, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE,
615 t->stride_in_dw);
616
617 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
618 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
619 COPY_DATA_DST_SEL(COPY_DATA_REG) |
620 COPY_DATA_WR_CONFIRM);
621 radeon_emit(cs, va); /* src address lo */
622 radeon_emit(cs, va >> 32); /* src address hi */
623 radeon_emit(cs, R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE >> 2);
624 radeon_emit(cs, 0); /* unused */
625
626 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
627 t->buf_filled_size, RADEON_USAGE_READ,
628 RADEON_PRIO_SO_FILLED_SIZE);
629 }
630
631 /* draw packet */
632 if (info->indexed) {
633 if (ib->index_size != sctx->last_index_size) {
634 unsigned index_type;
635
636 /* index type */
637 switch (ib->index_size) {
638 case 1:
639 index_type = V_028A7C_VGT_INDEX_8;
640 break;
641 case 2:
642 index_type = V_028A7C_VGT_INDEX_16 |
643 (SI_BIG_ENDIAN && sctx->b.chip_class <= CIK ?
644 V_028A7C_VGT_DMA_SWAP_16_BIT : 0);
645 break;
646 case 4:
647 index_type = V_028A7C_VGT_INDEX_32 |
648 (SI_BIG_ENDIAN && sctx->b.chip_class <= CIK ?
649 V_028A7C_VGT_DMA_SWAP_32_BIT : 0);
650 break;
651 default:
652 assert(!"unreachable");
653 return;
654 }
655
656 if (sctx->b.chip_class >= GFX9) {
657 radeon_set_uconfig_reg_idx(cs, R_03090C_VGT_INDEX_TYPE,
658 2, index_type);
659 } else {
660 radeon_emit(cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
661 radeon_emit(cs, index_type);
662 }
663
664 sctx->last_index_size = ib->index_size;
665 }
666
667 index_max_size = (ib->buffer->width0 - ib->offset) /
668 ib->index_size;
669 index_va = r600_resource(ib->buffer)->gpu_address + ib->offset;
670
671 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
672 (struct r600_resource *)ib->buffer,
673 RADEON_USAGE_READ, RADEON_PRIO_INDEX_BUFFER);
674 } else {
675 /* On CI and later, non-indexed draws overwrite VGT_INDEX_TYPE,
676 * so the state must be re-emitted before the next indexed draw.
677 */
678 if (sctx->b.chip_class >= CIK)
679 sctx->last_index_size = -1;
680 }
681
682 if (info->indirect) {
683 uint64_t indirect_va = r600_resource(info->indirect)->gpu_address;
684
685 assert(indirect_va % 8 == 0);
686
687 si_invalidate_draw_sh_constants(sctx);
688
689 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
690 radeon_emit(cs, 1);
691 radeon_emit(cs, indirect_va);
692 radeon_emit(cs, indirect_va >> 32);
693
694 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
695 (struct r600_resource *)info->indirect,
696 RADEON_USAGE_READ, RADEON_PRIO_DRAW_INDIRECT);
697
698 unsigned di_src_sel = info->indexed ? V_0287F0_DI_SRC_SEL_DMA
699 : V_0287F0_DI_SRC_SEL_AUTO_INDEX;
700
701 assert(info->indirect_offset % 4 == 0);
702
703 if (info->indexed) {
704 radeon_emit(cs, PKT3(PKT3_INDEX_BASE, 1, 0));
705 radeon_emit(cs, index_va);
706 radeon_emit(cs, index_va >> 32);
707
708 radeon_emit(cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
709 radeon_emit(cs, index_max_size);
710 }
711
712 if (!sctx->screen->has_draw_indirect_multi) {
713 radeon_emit(cs, PKT3(info->indexed ? PKT3_DRAW_INDEX_INDIRECT
714 : PKT3_DRAW_INDIRECT,
715 3, render_cond_bit));
716 radeon_emit(cs, info->indirect_offset);
717 radeon_emit(cs, (sh_base_reg + SI_SGPR_BASE_VERTEX * 4 - SI_SH_REG_OFFSET) >> 2);
718 radeon_emit(cs, (sh_base_reg + SI_SGPR_START_INSTANCE * 4 - SI_SH_REG_OFFSET) >> 2);
719 radeon_emit(cs, di_src_sel);
720 } else {
721 uint64_t count_va = 0;
722
723 if (info->indirect_params) {
724 struct r600_resource *params_buf =
725 (struct r600_resource *)info->indirect_params;
726
727 radeon_add_to_buffer_list(
728 &sctx->b, &sctx->b.gfx, params_buf,
729 RADEON_USAGE_READ, RADEON_PRIO_DRAW_INDIRECT);
730
731 count_va = params_buf->gpu_address + info->indirect_params_offset;
732 }
733
734 radeon_emit(cs, PKT3(info->indexed ? PKT3_DRAW_INDEX_INDIRECT_MULTI :
735 PKT3_DRAW_INDIRECT_MULTI,
736 8, render_cond_bit));
737 radeon_emit(cs, info->indirect_offset);
738 radeon_emit(cs, (sh_base_reg + SI_SGPR_BASE_VERTEX * 4 - SI_SH_REG_OFFSET) >> 2);
739 radeon_emit(cs, (sh_base_reg + SI_SGPR_START_INSTANCE * 4 - SI_SH_REG_OFFSET) >> 2);
740 radeon_emit(cs, ((sh_base_reg + SI_SGPR_DRAWID * 4 - SI_SH_REG_OFFSET) >> 2) |
741 S_2C3_DRAW_INDEX_ENABLE(1) |
742 S_2C3_COUNT_INDIRECT_ENABLE(!!info->indirect_params));
743 radeon_emit(cs, info->indirect_count);
744 radeon_emit(cs, count_va);
745 radeon_emit(cs, count_va >> 32);
746 radeon_emit(cs, info->indirect_stride);
747 radeon_emit(cs, di_src_sel);
748 }
749 } else {
750 int base_vertex;
751
752 radeon_emit(cs, PKT3(PKT3_NUM_INSTANCES, 0, 0));
753 radeon_emit(cs, info->instance_count);
754
755 /* Base vertex and start instance. */
756 base_vertex = info->indexed ? info->index_bias : info->start;
757
758 if (base_vertex != sctx->last_base_vertex ||
759 sctx->last_base_vertex == SI_BASE_VERTEX_UNKNOWN ||
760 info->start_instance != sctx->last_start_instance ||
761 info->drawid != sctx->last_drawid ||
762 sh_base_reg != sctx->last_sh_base_reg) {
763 radeon_set_sh_reg_seq(cs, sh_base_reg + SI_SGPR_BASE_VERTEX * 4, 3);
764 radeon_emit(cs, base_vertex);
765 radeon_emit(cs, info->start_instance);
766 radeon_emit(cs, info->drawid);
767
768 sctx->last_base_vertex = base_vertex;
769 sctx->last_start_instance = info->start_instance;
770 sctx->last_drawid = info->drawid;
771 sctx->last_sh_base_reg = sh_base_reg;
772 }
773
774 if (info->indexed) {
775 index_va += info->start * ib->index_size;
776
777 radeon_emit(cs, PKT3(PKT3_DRAW_INDEX_2, 4, render_cond_bit));
778 radeon_emit(cs, index_max_size);
779 radeon_emit(cs, index_va);
780 radeon_emit(cs, index_va >> 32);
781 radeon_emit(cs, info->count);
782 radeon_emit(cs, V_0287F0_DI_SRC_SEL_DMA);
783 } else {
784 radeon_emit(cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, render_cond_bit));
785 radeon_emit(cs, info->count);
786 radeon_emit(cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
787 S_0287F0_USE_OPAQUE(!!info->count_from_stream_output));
788 }
789 }
790 }
791
792 static void si_emit_surface_sync(struct r600_common_context *rctx,
793 unsigned cp_coher_cntl)
794 {
795 struct radeon_winsys_cs *cs = rctx->gfx.cs;
796
797 if (rctx->chip_class >= GFX9) {
798 /* Flush caches and wait for the caches to assert idle. */
799 radeon_emit(cs, PKT3(PKT3_ACQUIRE_MEM, 5, 0));
800 radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */
801 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
802 radeon_emit(cs, 0xffffff); /* CP_COHER_SIZE_HI */
803 radeon_emit(cs, 0); /* CP_COHER_BASE */
804 radeon_emit(cs, 0); /* CP_COHER_BASE_HI */
805 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
806 } else {
807 /* ACQUIRE_MEM is only required on a compute ring. */
808 radeon_emit(cs, PKT3(PKT3_SURFACE_SYNC, 3, 0));
809 radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */
810 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
811 radeon_emit(cs, 0); /* CP_COHER_BASE */
812 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
813 }
814 }
815
816 void si_emit_cache_flush(struct si_context *sctx)
817 {
818 struct r600_common_context *rctx = &sctx->b;
819 struct radeon_winsys_cs *cs = rctx->gfx.cs;
820 uint32_t cp_coher_cntl = 0;
821 uint32_t flush_cb_db = rctx->flags & (SI_CONTEXT_FLUSH_AND_INV_CB |
822 SI_CONTEXT_FLUSH_AND_INV_DB);
823
824 if (rctx->flags & (SI_CONTEXT_FLUSH_AND_INV_CB |
825 SI_CONTEXT_FLUSH_AND_INV_DB))
826 sctx->b.num_fb_cache_flushes++;
827
828 /* SI has a bug that it always flushes ICACHE and KCACHE if either
829 * bit is set. An alternative way is to write SQC_CACHES, but that
830 * doesn't seem to work reliably. Since the bug doesn't affect
831 * correctness (it only does more work than necessary) and
832 * the performance impact is likely negligible, there is no plan
833 * to add a workaround for it.
834 */
835
836 if (rctx->flags & SI_CONTEXT_INV_ICACHE)
837 cp_coher_cntl |= S_0085F0_SH_ICACHE_ACTION_ENA(1);
838 if (rctx->flags & SI_CONTEXT_INV_SMEM_L1)
839 cp_coher_cntl |= S_0085F0_SH_KCACHE_ACTION_ENA(1);
840
841 if (rctx->chip_class <= VI) {
842 if (rctx->flags & SI_CONTEXT_FLUSH_AND_INV_CB) {
843 cp_coher_cntl |= S_0085F0_CB_ACTION_ENA(1) |
844 S_0085F0_CB0_DEST_BASE_ENA(1) |
845 S_0085F0_CB1_DEST_BASE_ENA(1) |
846 S_0085F0_CB2_DEST_BASE_ENA(1) |
847 S_0085F0_CB3_DEST_BASE_ENA(1) |
848 S_0085F0_CB4_DEST_BASE_ENA(1) |
849 S_0085F0_CB5_DEST_BASE_ENA(1) |
850 S_0085F0_CB6_DEST_BASE_ENA(1) |
851 S_0085F0_CB7_DEST_BASE_ENA(1);
852
853 /* Necessary for DCC */
854 if (rctx->chip_class == VI)
855 r600_gfx_write_event_eop(rctx, V_028A90_FLUSH_AND_INV_CB_DATA_TS,
856 0, 0, NULL, 0, 0, 0);
857 }
858 if (rctx->flags & SI_CONTEXT_FLUSH_AND_INV_DB)
859 cp_coher_cntl |= S_0085F0_DB_ACTION_ENA(1) |
860 S_0085F0_DB_DEST_BASE_ENA(1);
861 }
862
863 if (rctx->flags & SI_CONTEXT_FLUSH_AND_INV_CB) {
864 /* Flush CMASK/FMASK/DCC. SURFACE_SYNC will wait for idle. */
865 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
866 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_META) | EVENT_INDEX(0));
867 }
868 if (rctx->flags & SI_CONTEXT_FLUSH_AND_INV_DB) {
869 /* Flush HTILE. SURFACE_SYNC will wait for idle. */
870 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
871 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_DB_META) | EVENT_INDEX(0));
872 }
873
874 /* Wait for shader engines to go idle.
875 * VS and PS waits are unnecessary if SURFACE_SYNC is going to wait
876 * for everything including CB/DB cache flushes.
877 */
878 if (!flush_cb_db) {
879 if (rctx->flags & SI_CONTEXT_PS_PARTIAL_FLUSH) {
880 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
881 radeon_emit(cs, EVENT_TYPE(V_028A90_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
882 /* Only count explicit shader flushes, not implicit ones
883 * done by SURFACE_SYNC.
884 */
885 rctx->num_vs_flushes++;
886 rctx->num_ps_flushes++;
887 } else if (rctx->flags & SI_CONTEXT_VS_PARTIAL_FLUSH) {
888 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
889 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
890 rctx->num_vs_flushes++;
891 }
892 }
893
894 if (rctx->flags & SI_CONTEXT_CS_PARTIAL_FLUSH &&
895 sctx->compute_is_busy) {
896 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
897 radeon_emit(cs, EVENT_TYPE(V_028A90_CS_PARTIAL_FLUSH | EVENT_INDEX(4)));
898 rctx->num_cs_flushes++;
899 sctx->compute_is_busy = false;
900 }
901
902 /* VGT state synchronization. */
903 if (rctx->flags & SI_CONTEXT_VGT_FLUSH) {
904 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
905 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
906 }
907 if (rctx->flags & SI_CONTEXT_VGT_STREAMOUT_SYNC) {
908 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
909 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_STREAMOUT_SYNC) | EVENT_INDEX(0));
910 }
911
912 /* GFX9: Wait for idle if we're flushing CB or DB. ACQUIRE_MEM doesn't
913 * wait for idle on GFX9. We have to use a TS event.
914 */
915 if (sctx->b.chip_class >= GFX9 && flush_cb_db) {
916 struct r600_resource *rbuf = NULL;
917 uint64_t va;
918 unsigned offset = 0, tc_flags, cb_db_event;
919
920 /* Set the CB/DB flush event. */
921 switch (flush_cb_db) {
922 case SI_CONTEXT_FLUSH_AND_INV_CB:
923 cb_db_event = V_028A90_FLUSH_AND_INV_CB_DATA_TS;
924 break;
925 case SI_CONTEXT_FLUSH_AND_INV_DB:
926 cb_db_event = V_028A90_FLUSH_AND_INV_DB_DATA_TS;
927 break;
928 default:
929 /* both CB & DB */
930 cb_db_event = V_028A90_CACHE_FLUSH_AND_INV_TS_EVENT;
931 }
932
933 /* TC | TC_WB = invalidate L2 data
934 * TC_MD | TC_WB = invalidate L2 metadata
935 * TC | TC_WB | TC_MD = invalidate L2 data & metadata
936 *
937 * The metadata cache must always be invalidated for coherency
938 * between CB/DB and shaders. (metadata = HTILE, CMASK, DCC)
939 *
940 * TC must be invalidated on GFX9 only if the CB/DB surface is
941 * not pipe-aligned. If the surface is RB-aligned, it might not
942 * strictly be pipe-aligned since RB alignment takes precendence.
943 */
944 tc_flags = EVENT_TC_WB_ACTION_ENA |
945 EVENT_TC_MD_ACTION_ENA;
946
947 /* Ideally flush TC together with CB/DB. */
948 if (rctx->flags & SI_CONTEXT_INV_GLOBAL_L2) {
949 tc_flags |= EVENT_TC_ACTION_ENA |
950 EVENT_TCL1_ACTION_ENA;
951
952 /* Clear the flags. */
953 rctx->flags &= ~(SI_CONTEXT_INV_GLOBAL_L2 |
954 SI_CONTEXT_WRITEBACK_GLOBAL_L2 |
955 SI_CONTEXT_INV_VMEM_L1);
956 }
957
958 /* Allocate memory for the fence. */
959 u_suballocator_alloc(rctx->allocator_zeroed_memory, 4, 4,
960 &offset, (struct pipe_resource**)&rbuf);
961 va = rbuf->gpu_address + offset;
962
963 r600_gfx_write_event_eop(rctx, cb_db_event, tc_flags, 1,
964 rbuf, va, 0, 1);
965 r600_gfx_wait_fence(rctx, va, 1, 0xffffffff);
966 }
967
968 /* Make sure ME is idle (it executes most packets) before continuing.
969 * This prevents read-after-write hazards between PFP and ME.
970 */
971 if (cp_coher_cntl ||
972 (rctx->flags & (SI_CONTEXT_CS_PARTIAL_FLUSH |
973 SI_CONTEXT_INV_VMEM_L1 |
974 SI_CONTEXT_INV_GLOBAL_L2 |
975 SI_CONTEXT_WRITEBACK_GLOBAL_L2))) {
976 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
977 radeon_emit(cs, 0);
978 }
979
980 /* SI-CI-VI only:
981 * When one of the CP_COHER_CNTL.DEST_BASE flags is set, SURFACE_SYNC
982 * waits for idle, so it should be last. SURFACE_SYNC is done in PFP.
983 *
984 * cp_coher_cntl should contain all necessary flags except TC flags
985 * at this point.
986 *
987 * SI-CIK don't support L2 write-back.
988 */
989 if (rctx->flags & SI_CONTEXT_INV_GLOBAL_L2 ||
990 (rctx->chip_class <= CIK &&
991 (rctx->flags & SI_CONTEXT_WRITEBACK_GLOBAL_L2))) {
992 /* Invalidate L1 & L2. (L1 is always invalidated on SI)
993 * WB must be set on VI+ when TC_ACTION is set.
994 */
995 si_emit_surface_sync(rctx, cp_coher_cntl |
996 S_0085F0_TC_ACTION_ENA(1) |
997 S_0085F0_TCL1_ACTION_ENA(1) |
998 S_0301F0_TC_WB_ACTION_ENA(rctx->chip_class >= VI));
999 cp_coher_cntl = 0;
1000 sctx->b.num_L2_invalidates++;
1001 } else {
1002 /* L1 invalidation and L2 writeback must be done separately,
1003 * because both operations can't be done together.
1004 */
1005 if (rctx->flags & SI_CONTEXT_WRITEBACK_GLOBAL_L2) {
1006 /* WB = write-back
1007 * NC = apply to non-coherent MTYPEs
1008 * (i.e. MTYPE <= 1, which is what we use everywhere)
1009 *
1010 * WB doesn't work without NC.
1011 */
1012 si_emit_surface_sync(rctx, cp_coher_cntl |
1013 S_0301F0_TC_WB_ACTION_ENA(1) |
1014 S_0301F0_TC_NC_ACTION_ENA(1));
1015 cp_coher_cntl = 0;
1016 sctx->b.num_L2_writebacks++;
1017 }
1018 if (rctx->flags & SI_CONTEXT_INV_VMEM_L1) {
1019 /* Invalidate per-CU VMEM L1. */
1020 si_emit_surface_sync(rctx, cp_coher_cntl |
1021 S_0085F0_TCL1_ACTION_ENA(1));
1022 cp_coher_cntl = 0;
1023 }
1024 }
1025
1026 /* If TC flushes haven't cleared this... */
1027 if (cp_coher_cntl)
1028 si_emit_surface_sync(rctx, cp_coher_cntl);
1029
1030 if (rctx->flags & R600_CONTEXT_START_PIPELINE_STATS) {
1031 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1032 radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_START) |
1033 EVENT_INDEX(0));
1034 } else if (rctx->flags & R600_CONTEXT_STOP_PIPELINE_STATS) {
1035 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1036 radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_STOP) |
1037 EVENT_INDEX(0));
1038 }
1039
1040 rctx->flags = 0;
1041 }
1042
1043 static void si_get_draw_start_count(struct si_context *sctx,
1044 const struct pipe_draw_info *info,
1045 unsigned *start, unsigned *count)
1046 {
1047 if (info->indirect) {
1048 unsigned indirect_count;
1049 struct pipe_transfer *transfer;
1050 unsigned begin, end;
1051 unsigned map_size;
1052 unsigned *data;
1053
1054 if (info->indirect_params) {
1055 data = pipe_buffer_map_range(&sctx->b.b,
1056 info->indirect_params,
1057 info->indirect_params_offset,
1058 sizeof(unsigned),
1059 PIPE_TRANSFER_READ, &transfer);
1060
1061 indirect_count = *data;
1062
1063 pipe_buffer_unmap(&sctx->b.b, transfer);
1064 } else {
1065 indirect_count = info->indirect_count;
1066 }
1067
1068 if (!indirect_count) {
1069 *start = *count = 0;
1070 return;
1071 }
1072
1073 map_size = (indirect_count - 1) * info->indirect_stride + 3 * sizeof(unsigned);
1074 data = pipe_buffer_map_range(&sctx->b.b, info->indirect,
1075 info->indirect_offset, map_size,
1076 PIPE_TRANSFER_READ, &transfer);
1077
1078 begin = UINT_MAX;
1079 end = 0;
1080
1081 for (unsigned i = 0; i < indirect_count; ++i) {
1082 unsigned count = data[0];
1083 unsigned start = data[2];
1084
1085 if (count > 0) {
1086 begin = MIN2(begin, start);
1087 end = MAX2(end, start + count);
1088 }
1089
1090 data += info->indirect_stride / sizeof(unsigned);
1091 }
1092
1093 pipe_buffer_unmap(&sctx->b.b, transfer);
1094
1095 if (begin < end) {
1096 *start = begin;
1097 *count = end - begin;
1098 } else {
1099 *start = *count = 0;
1100 }
1101 } else {
1102 *start = info->start;
1103 *count = info->count;
1104 }
1105 }
1106
1107 void si_ce_pre_draw_synchronization(struct si_context *sctx)
1108 {
1109 if (sctx->ce_need_synchronization) {
1110 radeon_emit(sctx->ce_ib, PKT3(PKT3_INCREMENT_CE_COUNTER, 0, 0));
1111 radeon_emit(sctx->ce_ib, 1);
1112
1113 radeon_emit(sctx->b.gfx.cs, PKT3(PKT3_WAIT_ON_CE_COUNTER, 0, 0));
1114 radeon_emit(sctx->b.gfx.cs, 1);
1115 }
1116 }
1117
1118 void si_ce_post_draw_synchronization(struct si_context *sctx)
1119 {
1120 if (sctx->ce_need_synchronization) {
1121 radeon_emit(sctx->b.gfx.cs, PKT3(PKT3_INCREMENT_DE_COUNTER, 0, 0));
1122 radeon_emit(sctx->b.gfx.cs, 0);
1123
1124 sctx->ce_need_synchronization = false;
1125 }
1126 }
1127
1128 void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info)
1129 {
1130 struct si_context *sctx = (struct si_context *)ctx;
1131 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
1132 const struct pipe_index_buffer *ib = &sctx->index_buffer;
1133 struct pipe_index_buffer ib_tmp; /* for index buffer uploads only */
1134 unsigned mask, dirty_tex_counter;
1135 enum pipe_prim_type rast_prim;
1136 unsigned num_patches = 0;
1137
1138 if (likely(!info->indirect)) {
1139 /* SI-CI treat instance_count==0 as instance_count==1. There is
1140 * no workaround for indirect draws, but we can at least skip
1141 * direct draws.
1142 */
1143 if (unlikely(!info->instance_count))
1144 return;
1145
1146 /* Handle count == 0. */
1147 if (unlikely(!info->count &&
1148 (info->indexed || !info->count_from_stream_output)))
1149 return;
1150 }
1151
1152 if (unlikely(!sctx->vs_shader.cso)) {
1153 assert(0);
1154 return;
1155 }
1156 if (unlikely(!sctx->ps_shader.cso && (!rs || !rs->rasterizer_discard))) {
1157 assert(0);
1158 return;
1159 }
1160 if (unlikely(!!sctx->tes_shader.cso != (info->mode == PIPE_PRIM_PATCHES))) {
1161 assert(0);
1162 return;
1163 }
1164
1165 /* Recompute and re-emit the texture resource states if needed. */
1166 dirty_tex_counter = p_atomic_read(&sctx->b.screen->dirty_tex_counter);
1167 if (unlikely(dirty_tex_counter != sctx->b.last_dirty_tex_counter)) {
1168 sctx->b.last_dirty_tex_counter = dirty_tex_counter;
1169 sctx->framebuffer.dirty_cbufs |=
1170 ((1 << sctx->framebuffer.state.nr_cbufs) - 1);
1171 sctx->framebuffer.dirty_zsbuf = true;
1172 sctx->framebuffer.do_update_surf_dirtiness = true;
1173 si_mark_atom_dirty(sctx, &sctx->framebuffer.atom);
1174 si_update_all_texture_descriptors(sctx);
1175 }
1176
1177 si_decompress_graphics_textures(sctx);
1178
1179 /* Set the rasterization primitive type.
1180 *
1181 * This must be done after si_decompress_textures, which can call
1182 * draw_vbo recursively, and before si_update_shaders, which uses
1183 * current_rast_prim for this draw_vbo call. */
1184 if (sctx->gs_shader.cso)
1185 rast_prim = sctx->gs_shader.cso->gs_output_prim;
1186 else if (sctx->tes_shader.cso)
1187 rast_prim = sctx->tes_shader.cso->info.properties[TGSI_PROPERTY_TES_PRIM_MODE];
1188 else
1189 rast_prim = info->mode;
1190
1191 if (rast_prim != sctx->current_rast_prim) {
1192 sctx->current_rast_prim = rast_prim;
1193 sctx->do_update_shaders = true;
1194 }
1195
1196 if (sctx->gs_shader.cso) {
1197 /* Determine whether the GS triangle strip adjacency fix should
1198 * be applied. Rotate every other triangle if
1199 * - triangle strips with adjacency are fed to the GS and
1200 * - primitive restart is disabled (the rotation doesn't help
1201 * when the restart occurs after an odd number of triangles).
1202 */
1203 bool gs_tri_strip_adj_fix =
1204 !sctx->tes_shader.cso &&
1205 info->mode == PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY &&
1206 !info->primitive_restart;
1207
1208 if (gs_tri_strip_adj_fix != sctx->gs_tri_strip_adj_fix) {
1209 sctx->gs_tri_strip_adj_fix = gs_tri_strip_adj_fix;
1210 sctx->do_update_shaders = true;
1211 }
1212 }
1213
1214 if (sctx->do_update_shaders && !si_update_shaders(sctx))
1215 return;
1216
1217 if (!si_upload_graphics_shader_descriptors(sctx))
1218 return;
1219
1220 ib_tmp.buffer = NULL;
1221
1222 if (info->indexed) {
1223 /* Translate or upload, if needed. */
1224 /* 8-bit indices are supported on VI. */
1225 if (sctx->b.chip_class <= CIK && ib->index_size == 1) {
1226 unsigned start, count, start_offset, size;
1227 void *ptr;
1228
1229 si_get_draw_start_count(sctx, info, &start, &count);
1230 start_offset = start * 2;
1231 size = count * 2;
1232
1233 u_upload_alloc(ctx->stream_uploader, start_offset,
1234 size,
1235 si_optimal_tcc_alignment(sctx, size),
1236 &ib_tmp.offset, &ib_tmp.buffer, &ptr);
1237 if (!ib_tmp.buffer)
1238 return;
1239
1240 util_shorten_ubyte_elts_to_userptr(&sctx->b.b, ib, 0, 0,
1241 ib->offset + start,
1242 count, ptr);
1243
1244 /* info->start will be added by the drawing code */
1245 ib_tmp.offset -= start_offset;
1246 ib_tmp.index_size = 2;
1247 ib = &ib_tmp;
1248 } else if (ib->user_buffer && !ib->buffer) {
1249 unsigned start_offset;
1250
1251 assert(!info->indirect);
1252 start_offset = info->start * ib->index_size;
1253
1254 u_upload_data(ctx->stream_uploader, start_offset,
1255 info->count * ib->index_size,
1256 sctx->screen->b.info.tcc_cache_line_size,
1257 (char*)ib->user_buffer + start_offset,
1258 &ib_tmp.offset, &ib_tmp.buffer);
1259 if (!ib_tmp.buffer)
1260 return;
1261
1262 /* info->start will be added by the drawing code */
1263 ib_tmp.offset -= start_offset;
1264 ib_tmp.index_size = ib->index_size;
1265 ib = &ib_tmp;
1266 } else if (sctx->b.chip_class <= CIK &&
1267 r600_resource(ib->buffer)->TC_L2_dirty) {
1268 /* VI reads index buffers through TC L2, so it doesn't
1269 * need this. */
1270 sctx->b.flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
1271 r600_resource(ib->buffer)->TC_L2_dirty = false;
1272 }
1273 }
1274
1275 if (info->indirect) {
1276 /* Add the buffer size for memory checking in need_cs_space. */
1277 r600_context_add_resource_size(ctx, info->indirect);
1278
1279 if (r600_resource(info->indirect)->TC_L2_dirty) {
1280 sctx->b.flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
1281 r600_resource(info->indirect)->TC_L2_dirty = false;
1282 }
1283
1284 if (info->indirect_params &&
1285 r600_resource(info->indirect_params)->TC_L2_dirty) {
1286 sctx->b.flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
1287 r600_resource(info->indirect_params)->TC_L2_dirty = false;
1288 }
1289 }
1290
1291 si_need_cs_space(sctx);
1292
1293 /* Since we've called r600_context_add_resource_size for vertex buffers,
1294 * this must be called after si_need_cs_space, because we must let
1295 * need_cs_space flush before we add buffers to the buffer list.
1296 */
1297 if (!si_upload_vertex_buffer_descriptors(sctx))
1298 return;
1299
1300 /* GFX9 scissor bug workaround. There is also a more efficient but
1301 * more involved alternative workaround. */
1302 if (sctx->b.chip_class == GFX9 &&
1303 si_is_atom_dirty(sctx, &sctx->b.scissors.atom))
1304 sctx->b.flags |= SI_CONTEXT_PS_PARTIAL_FLUSH;
1305
1306 /* Flush caches before the first state atom, which does L2 prefetches. */
1307 if (sctx->b.flags)
1308 si_emit_cache_flush(sctx);
1309
1310 /* Emit state atoms. */
1311 mask = sctx->dirty_atoms;
1312 while (mask) {
1313 struct r600_atom *atom = sctx->atoms.array[u_bit_scan(&mask)];
1314
1315 atom->emit(&sctx->b, atom);
1316 }
1317 sctx->dirty_atoms = 0;
1318
1319 /* Emit states. */
1320 mask = sctx->dirty_states;
1321 while (mask) {
1322 unsigned i = u_bit_scan(&mask);
1323 struct si_pm4_state *state = sctx->queued.array[i];
1324
1325 if (!state || sctx->emitted.array[i] == state)
1326 continue;
1327
1328 si_pm4_emit(sctx, state);
1329 sctx->emitted.array[i] = state;
1330 }
1331 sctx->dirty_states = 0;
1332
1333 si_emit_rasterizer_prim_state(sctx);
1334 if (sctx->tes_shader.cso)
1335 si_emit_derived_tess_state(sctx, info, &num_patches);
1336 si_emit_vs_state(sctx, info);
1337 si_emit_draw_registers(sctx, info, num_patches);
1338
1339 si_ce_pre_draw_synchronization(sctx);
1340 si_emit_draw_packets(sctx, info, ib);
1341 si_ce_post_draw_synchronization(sctx);
1342
1343 if (sctx->trace_buf)
1344 si_trace_emit(sctx);
1345
1346 /* Workaround for a VGT hang when streamout is enabled.
1347 * It must be done after drawing. */
1348 if ((sctx->b.family == CHIP_HAWAII ||
1349 sctx->b.family == CHIP_TONGA ||
1350 sctx->b.family == CHIP_FIJI) &&
1351 r600_get_strmout_en(&sctx->b)) {
1352 sctx->b.flags |= SI_CONTEXT_VGT_STREAMOUT_SYNC;
1353 }
1354
1355 if (sctx->framebuffer.do_update_surf_dirtiness) {
1356 /* Set the depth buffer as dirty. */
1357 if (sctx->framebuffer.state.zsbuf) {
1358 struct pipe_surface *surf = sctx->framebuffer.state.zsbuf;
1359 struct r600_texture *rtex = (struct r600_texture *)surf->texture;
1360
1361 if (!rtex->tc_compatible_htile)
1362 rtex->dirty_level_mask |= 1 << surf->u.tex.level;
1363
1364 if (rtex->surface.flags & RADEON_SURF_SBUFFER)
1365 rtex->stencil_dirty_level_mask |= 1 << surf->u.tex.level;
1366 }
1367 if (sctx->framebuffer.compressed_cb_mask) {
1368 struct pipe_surface *surf;
1369 struct r600_texture *rtex;
1370 unsigned mask = sctx->framebuffer.compressed_cb_mask;
1371
1372 do {
1373 unsigned i = u_bit_scan(&mask);
1374 surf = sctx->framebuffer.state.cbufs[i];
1375 rtex = (struct r600_texture*)surf->texture;
1376
1377 if (rtex->fmask.size)
1378 rtex->dirty_level_mask |= 1 << surf->u.tex.level;
1379 if (rtex->dcc_gather_statistics)
1380 rtex->separate_dcc_dirty = true;
1381 } while (mask);
1382 }
1383 sctx->framebuffer.do_update_surf_dirtiness = false;
1384 }
1385
1386 pipe_resource_reference(&ib_tmp.buffer, NULL);
1387 sctx->b.num_draw_calls++;
1388 if (G_0286E8_WAVESIZE(sctx->spi_tmpring_size))
1389 sctx->b.num_spill_draw_calls++;
1390 }
1391
1392 void si_trace_emit(struct si_context *sctx)
1393 {
1394 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
1395
1396 sctx->trace_id++;
1397 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, sctx->trace_buf,
1398 RADEON_USAGE_READWRITE, RADEON_PRIO_TRACE);
1399 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
1400 radeon_emit(cs, S_370_DST_SEL(V_370_MEMORY_SYNC) |
1401 S_370_WR_CONFIRM(1) |
1402 S_370_ENGINE_SEL(V_370_ME));
1403 radeon_emit(cs, sctx->trace_buf->gpu_address);
1404 radeon_emit(cs, sctx->trace_buf->gpu_address >> 32);
1405 radeon_emit(cs, sctx->trace_id);
1406 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1407 radeon_emit(cs, AC_ENCODE_TRACE_POINT(sctx->trace_id));
1408 }